The Tegra210 XUSB subsystem has 3 power partitions which are XUSBA
(super-speed logic), XUSBB (USB device logic) and XUSBC (USB host
logic). Populate the device-tree nodes for these XUSB partitions.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the DPAUX pinctrl states for the DPAUX nodes defining all three
possible states of "aux", "i2c" and "off". Also add the 'i2c-bus'
node for the DPAUX nodes so that the I2C driver core does not attempt
to parse the pinctrl state nodes.
Populate the nodes for the pinctrl clients of the DPAUX pin controller.
There are two clients for each DPAUX instance, namely the SOR and one of
the I2C adapters. The SOR clients may used the DPAUX pins in either AUX
or I2C modes and so for these devices we don't define any of the generic
pinctrl states (default, idle, etc) because the SOR driver will directly
set the state needed. For I2C clients only the I2C mode is used and so
we can simplify matters by using the generic pinctrl states for default
and idle.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the ACONNECT bus node for Tegra210 which is used to interface to
the various devices in the Audio Processing Engine (APE).
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add regulators to the Tegra210 Smaug DTS file including support for the
MAX77620 PMIC.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The XUSB mailbox interrupt for Tegra210 is 40 and not 49 which is for
the XUSB pad controller. For some Tegra210 boards, this is causing USB
connect and disconnect events to go undetected. Fix this by changing the
interrupt number for the XUSB mailbox to 40.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable the XUSB controller on Jetson TX1. One of the USB 3.0 lanes goes
to an internal ethernet interface, while a second USB 3.0 lane supports
the USB-A receptacle on the I/O board.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a chosen node to the device tree that contains a stdout-path
property which defines the debug serial port.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a device tree node for the Tegra XUSB controller. It contains a
phandle to the XUSB pad controller for control of the PHYs assigned
to the USB ports.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add power supplies for the SD/MMC card slot. Note that vmmc-supply is
currently restricted to 3.3 V because we don't support switching the
mode yet.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a device tree node for the MAX77620 PMIC found on the p2180
processor module (Jetson TX1). Also add supporting power supplies,
such as the main 5 V system supply.
Signed-off-by: Thierry Reding <treding@nvidia.com>
1. Adjust the voltage of CPU buck regulator so scaling could work.
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Merge tag 'samsung-dt64-4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64
Merge "Samsung DeviceTree changes for ARM64 for v4.8" from Krzysztof Kozlowski:
1. Adjust the voltage of CPU buck regulator so scaling could work.
* tag 'samsung-dt64-4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Modify the voltage range for BUCK2 for exynos7
1. Adds various CoreSight debug components on Juno boards
2. Adds SCPI device power domains and use them for coresight components
3. Adds thermal zones for SCPI sensors on Juno
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Merge tag 'juno-dt-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64
Merge "Juno platform DT updates for v4.8" from Sudeep Holla:
1. Adds various CoreSight debug components on Juno boards
2. Adds SCPI device power domains and use them for coresight components
3. Adds thermal zones for SCPI sensors on Juno
* tag 'juno-dt-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: add thermal zones for scpi sensors
arm64: dts: juno: add SCPI power domains for device power management
arm64: dts: juno: add coresight support
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Merge tag 'v4.7-rc6' into patchwork
Linux 4.7-rc6
* tag 'v4.7-rc6': (1245 commits)
Linux 4.7-rc6
ovl: warn instead of error if d_type is not supported
MIPS: Fix possible corruption of cache mode by mprotect.
locks: use file_inode()
usb: dwc3: st: Use explicit reset_control_get_exclusive() API
phy: phy-stih407-usb: Use explicit reset_control_get_exclusive() API
phy: miphy28lp: Inform the reset framework that our reset line may be shared
namespace: update event counter when umounting a deleted dentry
9p: use file_dentry()
lockd: unregister notifier blocks if the service fails to come up completely
ACPI,PCI,IRQ: correct operator precedence
fuse: serialize dirops by default
drm/i915: Fix missing unlock on error in i915_ppgtt_info()
powerpc: Initialise pci_io_base as early as possible
mfd: da9053: Fix compiler warning message for uninitialised variable
mfd: max77620: Fix FPS switch statements
phy: phy-stih407-usb: Inform the reset framework that our reset line may be shared
usb: dwc3: st: Inform the reset framework that our reset line may be shared
usb: host: ehci-st: Inform the reset framework that our reset line may be shared
usb: host: ohci-st: Inform the reset framework that our reset line may be shared
...
Add video encoder node for MT8173
Signed-off-by: Tiffany Lin <tiffany.lin@mediatek.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
This reverts commit f3abd62961, which caused a build regression:
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi:48:41: fatal error: dt-bindings/clock/gxbb-clkc.h: No such file or directory
We should apply this patch one merge window later, once the clk branch
is merged as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
changes for 4.8. Please note that this pull request contains changes from the
ARM 32-bits port and ARM 64-bits port as well:
- Lubomir updates all BCM2835 (Raspberry Pi family) Device Tree source files with
their proper information about the on-board USB Ethernet adapter so there is
appropriate binding between this USB device and a device_node (useful for MAC
address fetching and stuff), this commit is also present for the ARM DT pull
request
- Eric adds support for the Raspberry Pi 3 aka BCM2837 and provides the binding
information and the basic SoC DT include file required to boot to a prompt
- Gerd updates the Raspberry Pi 3 DT with Ethernet information based on the
earlier change from Lubomir
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Merge tag 'arm-soc/for-4.8/devicetree-arm64-part2' of http://github.com/Broadcom/stblinux into next/dt64
Merge "Broadcom ARM64 Device Tree changes for 4.8 (part 2)" from Florian Fainelli:
This pull request contains the second part of the Broadcom ARM64-based SoCs
changes for 4.8. Please note that this pull request contains changes from the
ARM 32-bits port and ARM 64-bits port as well:
- Lubomir updates all BCM2835 (Raspberry Pi family) Device Tree source files with
their proper information about the on-board USB Ethernet adapter so there is
appropriate binding between this USB device and a device_node (useful for MAC
address fetching and stuff), this commit is also present for the ARM DT pull
request
- Eric adds support for the Raspberry Pi 3 aka BCM2837 and provides the binding
information and the basic SoC DT include file required to boot to a prompt
- Gerd updates the Raspberry Pi 3 DT with Ethernet information based on the
earlier change from Lubomir
* tag 'arm-soc/for-4.8/devicetree-arm64-part2' of http://github.com/Broadcom/stblinux:
ARM: bcm2837: dt: Add the ethernet to the device trees
ARM: bcm2835: Add devicetree for the Raspberry Pi 3.
dt-bindings: Add root properties for Raspberry Pi 3
ARM: bcm2835: dt: Add the ethernet to the device trees
Pull the clockevents/clocksource tree from Daniel Lezcano:
- Convert the clocksource-probe init functions to return a value in order to
prepare the consolidation of the drivers using the DT. It is a big patchset
but went through 01.org (kbuild bot), linux next and kernel-ci (continuous
integration) (Daniel Lezcano)
- Fix a bad error handling by returning the right value for cadence_ttc
(Christophe Jaillet)
- Fix typo in the Kconfig for the Samsung pwm (Alexandre Belloni)
- Change functions to static for armada-370-xp and digicolor (Ben Dooks)
- Add support for the rk3399 SoC timer by adding bindings and a slight
change in the base address. Take the opportunity to add the DYNIRQ flag
(Huang Tao)
- Fix endian accessors for the Samsung pwm timer (Matthew Leach)
- Add Oxford Semiconductor RPS Dual Timer driver (Neil Armstrong)
- Add a kernel parameter to swich on/off the event stream feature of the arch
arm timer (Will Deacon)
- update dt with mv-xor-v2 found in the Armada 7K/8K SoCs
- update dt with the clocks found in the Armada 3700 SoCs
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Merge tag 'mvebu-dt64-4.8-1' of git://git.infradead.org/linux-mvebu into next/dt64
Merge "mvebu dt64 for 4.8 (part 1)" from Gregory CLEMENT:
- update dt with mv-xor-v2 found in the Armada 7K/8K SoCs
- update dt with the clocks found in the Armada 3700 SoCs
* tag 'mvebu-dt64-4.8-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: add peripherals clocks for Armada 37xx
arm64: dts: marvell: add tbg clocks for Armada 37xx
arm64: dts: marvell: Add xtal clock support for Armada 3700
arm64: dts: marvell: add XOR engine description for Armada 7K/8K CP
arm64: dts: marvell: adjust to the latest mv-xor-v2 DT binding
Enable the Watchdog Timer (WDT) controller on the Renesas Salvator-X
board equipped with an R-Car M3-W (r8a7796) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a device node for the Watchdog Timer (WDT) controller on the Renesas
R-Car M3-W (r8a7796) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Hook up all devices that are part of the CPG/MSSR Clock Domain to the
SYSC "always-on" PM Domain, for a more consistent device-power-area
description in DT.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a device node for the System Controller.
Hook up the Cortex-A57 CPU core and L2 cache/SCU to their respective PM
Domains.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Basic support for the Gen 3 R-Car M3-W SoC.
Based on work for the r8a7795 and r8a7796 SoCs by
Takeshi Kihara, Dirk Behme and Geert Uytterhoeven.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Adds CAN FD controller node for r8a7795.
Note: CAN FD controller register base address specified in R-Car Gen3
Hardware User Manual v0.5E is incorrect. The correct address is:
CAN FD - 0xe66c0000
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
For consistency with a57_0/a57_1 cpu nodes, and all other nodes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
i2c and core io-domain nodes and some reasonable default rates
for core clocks. The rk3368 also gets io-domains for its r88 board
as well as a small fix for the gic's memory regions.
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Merge tag 'v4.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
The rk3399 gets support for its emmc controller as well as thermal,
i2c and core io-domain nodes and some reasonable default rates
for core clocks. The rk3368 also gets io-domains for its r88 board
as well as a small fix for the gic's memory regions.
* tag 'v4.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: add ap_pwroff and ddrio_pwroff pins for rk3399
arm64: dts: rockchip: Provide emmcclk to PHY for rk3399
arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399
arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368
arm64: dts: rockchip: add i2c nodes for rk3399
arm64: dts: rockchip: add thermal nodes for rk3399 SoCs
arm64: dts: rockchip: add rk3399 io-domain core nodes
arm64: dts: rockchip: add rk3368-r88 iodomains
arm64: dts: rockchip: add rk3368 io-domain core nodes
arm64: dts: rockchip: make rk3368 grf syscons simple-mfds
arm64: dts: rockchip: enable eMMC for rk3399 EVB
arm64: dts: rockchip: add sdhci/emmc for rk3399
arm64: dts: rockchip: make rk3399's grf a "simple-mfd"
arm64: dts: rockchip: assign default rates for core rk3399 clocks
Signed-off-by: Olof Johansson <olof@lixom.net>
Change the BUCK2 (vdd_atlas) voltage range to '500 - 1200mv' since
CPU DVFS requires it.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
- name the GPIO lines
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Merge tag 'hi6220-dt-for-4.8' of git://github.com/hisilicon/linux-hisi into next/dt64
ARM64: DT: Hisilicon Hi6220 hikey board updates for 4.8
- name the GPIO lines
* tag 'hi6220-dt-for-4.8' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hikey: name the GPIO lines
Signed-off-by: Olof Johansson <olof@lixom.net>
- Update address-cells and reg properties of cpu nodes, considering
MPIDR_EL1[63:32] bits are not used for CPUs identification on ls1043a
and ls2080a
- Adds the cache nodes and next-level-cache property for ls1043a and
ls2080a to get cacheinfo work on these platforms
- Add dma-coherent for ls1043a PCI nodes to utilize the hardware
capability on data coherency
- Add dis_rxdet_inp3_quirk property for USB3 device to disable rx
detection in P3 PHY mode
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Merge tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
The Freescale arm64 device tree updates for 4.8:
- Update address-cells and reg properties of cpu nodes, considering
MPIDR_EL1[63:32] bits are not used for CPUs identification on ls1043a
and ls2080a
- Adds the cache nodes and next-level-cache property for ls1043a and
ls2080a to get cacheinfo work on these platforms
- Add dma-coherent for ls1043a PCI nodes to utilize the hardware
capability on data coherency
- Add dis_rxdet_inp3_quirk property for USB3 device to disable rx
detection in P3 PHY mode
* tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: ls2080a: Add cache nodes for cacheinfo support
arm64: dts: ls1043a: Add cache nodes for cacheinfo support
arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes
bindings: PCI: layerscape: Add 'dma-coherent' property
arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 node
arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 node
arm64: dts: fsl: Update address-cells and reg properties of cpu nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
support. Note that it also merges in the ethernet DT changes so that
the Pi3's ethernet can also get the MAC address.
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Merge tag 'bcm2835-dt-64-next-2016-07-03' into devicetree-arm64/next
This pull request brings in the Raspberry Pi 3 DT for its arm64
support. Note that it also merges in the ethernet DT changes so that
the Pi3's ethernet can also get the MAC address.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add two new blocks of clocks. The peripheral clocks are the source clocks
of the peripheral of the Armada 3700 SoC.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add a new block of clocks. The Time Base Generators clocks can be the
parent of the peripheral clocks.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The configuration of the clock depend of the gpio latch. This information
is stored in the gpio block registers. That's why the block is shared
using a syscon node.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This adds basic chip support for MT6755 SoC.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit adds the Device Tree description for the two XOR engines
found in the CP part of the Armada 7K/8K SoC.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
As suggested by Rob Herring, we should:
1/ Use a SoC-specific compatible string in addition to the more generic
one.
2/ The generic compatible string has been changed from
"marvell,mv-xor-v2" to "marvell,xor-v2".
We simply reflect the changes made to the Device Tree bindings to the
relevant Marvell 7K/8K Device Tree files.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Several cases of overlapping changes, except the packet scheduler
conflicts which deal with the addition of the free list parameter
to qdisc_enqueue().
Signed-off-by: David S. Miller <davem@davemloft.net>
This names the GPIO lines on the HiKey board in accordance with
the 96Board Specification for especially the Low Speed External
Connector: "GPIO-A" thru "GPIO-L".
This will make these line names reflect through to userspace
so that they can easily be identified and used with the new
character device ABI.
Some care has been taken to name all lines, not just those used
by the external connectors, also lines that are muxed into some
other function than GPIO: these are named "[FOO]" so that users
can see with lsgpio what all lines are used for.
Cc: devicetree@vger.kernel.org
Cc: John Stultz <john.stultz@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: David Mandala <david.mandala@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add a 'rktimer' node in the device treee for the ARM64 rk3399 SoC.
Signed-off-by: Huang Tao <huangtao@rock-chips.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Tested-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
There are two sleep related pins on rk3399: ap_pwroff and ddrio_pwroff.
Let's add the definition of these two pins to rk3399's main dtsi file so
that boards can use them.
These two pins are similar to the global_pwroff and ddrio_pwroff pins in
rk3288 and are expected to be used in the same way: boards will likely
want to configure these pinctrl settings in their global pinctrl hog
list.
Note that on rk3288 there were two additional pins in the "sleep"
section: "ddr0_retention" and "ddr1_retention". On rk3288 designs these
pins appeared to actually route from rk3288 back to rk3288. Presumably
on rk3399 this is simply not needed since the pins don't appear to exist
there.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch adds support to sdc2 sdhci controller, which is used on some
of the boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds pinctrl required for sdhci for external sd card
controller.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support to blsp2_spi5 device, which is used in some of
the APQ8096 based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support to blsp1_spi0 which is used on some of APQ8096
based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support to blsp2_i2c0, which is used on some of the
APQ8096 based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support to blsp2_i2c0 pinctrl.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support to blsp2_i2c1, which is used in one of the
apq8096 based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support to blsp2_i2c1 pinctrl nodes.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds blsp1_i2c2 support, as this bus is used on some of the
apq8096 boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds bslp2_uart2 node in soc so that boards that use this
uart can enable it.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds 2pin and 4 pin uart pinctrl support for blsp2_uart1
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds msmgpio label for pin and gpio controller so that
it can referenced in dedicated pins file and other board level gpios.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the clock controller node for the AmLogic GXBB machine.
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Previous changes in this series allowed exposing the card clock from the
rk3399 SDHCI device and allowed consuming the card clock in the rk3399
eMMC PHY. Hook things up in the main rk3399 dtsi file.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component. Specify the syscon to enable that.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The juno dts have entries for the hwmon scpi, let's create thermal zones
for the temperature sensors described in the Juno ARM Development
Platform Implementation Details.
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Javi Merino <javi.merino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This patch adds power domain information to coresight devices using
SCPI power domains.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Most of the debug-related components on Juno are located in the coreSight
subsystem while others are located in the Cortex-Axx clusters, the SCP
subsystem, and in the main system.
Each core in the two processor clusters contain an Embedded Trace
Macrocell(ETM) which generates real-time trace information that trace
tools can use and an ATB trace output that is sent to a funnel before
going to the CoreSight subsystem.
The trace output signals combine with two trace expansions using another
funnel and fed into the Embedded Trace FIFO(ETF0).
The output trace data stream of the funnel is then replicated before it
is sent to either the:
- Trace Port Interface Unit(TPIU), that sends it out using the trace port.
- ETR that can write the trace data to memory located in the application
memory space
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Adds the cache nodes and next-level-cache property for the
cacheinfo to work.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Adds the cache nodes and next-level-cache property for the
cacheinfo to work.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Unit addresses should not have a leading '0x'. Remove them.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Duc Dang <dhdang@apm.com>
The convention in these files is to use lowercase for "0x" prefixes and for
the hex constants themselves, but a few changes didn't follow that
convention, which makes the file annoying to read.
Use lowercase consistently for the hex constants. No functional change
intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Duc Dang <dhdang@apm.com>
- Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs
- Dhanajay enables pinctrl for the Northstar2 SoCs
- Jon Mason enables all of the UART peripherals found in the NS2 SVK and
finally adds the CCI-400 and PMU nodes
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Merge tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64
This pull request contains Device Tree changes for Broadcom ARM64-based SoCS:
- Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs
- Dhanajay enables pinctrl for the Northstar2 SoCs
- Jon Mason enables all of the UART peripherals found in the NS2 SVK and
finally adds the CCI-400 and PMU nodes
* tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux:
arm64: dts: NS2: Add CCI-400 PMU support
arm64: dts: NS2: Add all of the UARTs
arm64: dts: Enable GPIO for Broadcom NS2 SoC
arm64: dts: enable pinctrl for Broadcom NS2 SoC
arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2
dt-bindings: ata: add compatible string for iProc AHCI controller
Signed-off-by: Olof Johansson <olof@lixom.net>
The 2nd additional region is the GIC virtual cpu interface register
base and size.
As the gic400 of rk3368 says, the cpu interface register map as below
:
-0x0000 GICC_CTRL
.
.
.
-0x00fc GICC_IIDR
-0x1000 GICC_IDR
Obviously, the region size should be greater than 0x1000.
So we should make sure to include the GICC_IDR since the kernel will access
it in some cases.
Fixes: b790c2cab5 ("arm64: dts: add Rockchip rk3368 core dtsi and board dts for the r88 board")
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Cc: stable@vger.kernel.org
[added Fixes and stable-cc]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We've got 9 (count em!) i2c controllers on rk3399, some of which are in
the PMU power domain and some of which are normal peripherals. Add them
all to the main rk3399 dtsi file so future patches can turn them on in
the board dts files.
Note: by default we try to set the i2c clock rate to 200 MHz so that we
can achieve good i2c functional clock rates. 200 MHz gives us the
ability to make very close to 100 kHz / 400 kHz / 1 MHz rates. If
boards want to tune clock rates further they can always override.
Possibly boards could want to tune this if:
- they wanted to save an infinitesimal amount of power and they knew
their i2c bus was slow anyway. Since we gate the functional clock
when the i2c bus is not active, power savings would only be while i2c
transfers were happening and probably won't be very big anyway.
- they wanted to eek out a bit more speed by carefully tuning the source
clock to make divisions work out perfectly, accounting for the rise /
fall time measured on an actual board.
Note also that we still request 200 MHz for the PMU i2c busses even
though we expect that we won't make that exactly (currently PPLL is 676
MHz which gives us 169 MHz).
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
[dianders: wrote desc; put in assigned-clocks; reordered nodes]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.
The PCI IP block of ls1043a has this capability, so adding this
feature to improve the PCI performance.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
As Documentation/arm64/booting.txt says, the cpu-release-addr
location should be reserved.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
At first, 256 byte of the head of DRAM space was reserved for some
reasons. However, as the progress of development, it turned out
unnecessary, and it was never used in the end. Move the CPU release
address to leave no space.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This node consists of various system-level configuration registers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Update reserved-memory in accordance with memory the detailed memory map
for 8916, so that we will be able to reference the firmware memory
regions.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds the devicetree node for the SCM firmware.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Add the PMU so we can get proper perf event support on this SoC.
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add device bindings for CPUs to suspend using PSCI as the enable-method.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Tested-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch enables bam dma node, dma is used for both tx and rx on spi
and on high speed serial.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the necessary properties to enable the SD-card on db410c boards.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add integrated MDIO multiplexer driver node which contains
two mux PCIe bus and one ethernet bus along with phys
lying on these bus.
Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and
LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1,
since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update
the #address-cells and reg properties accordingly.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
While this devicetree also works for booting in 32-bit mode, it's
placed in arm64 since it's a 64-bit CPU (as suggested by Arnd).
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org> (v1)
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
LS1043A has a SEC v5.4 security engine.
For now don't add rtic or sec_mon subnodes, since these features
haven't been tested yet.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This adds thermal zone and tsadc nodes to rk3399 dtsi, rk3399 thermal
data is including the cpu and gpu sensor zone node.
The thermal zone node is the node containing all the required info
for describing a thermal zone, including its cooling device bindings.
The thermal zone node must contain, apart from its own properties, one
sub-node containing trip nodes and one sub-node containing all the zone
cooling maps.
The following is the parameter is introduced:
* polling-delay:
The maximum number of milliseconds to wait between polls
* polling-delay-passive:
The maximum number of milliseconds to wait between polls when performing
passive cooling.
* trips:
A sub-node which is a container of only trip point nodes required to
describe the thermal zone.
* cooling-maps:
A sub-node which is a container of only cooling device map nodes, used to
describe the relation between trips and cooling devices.
* cooling-device:
A phandle of a cooling device with its specifier, referring to which
cooling device is used in this cooling specifier binding. In the cooling
specifier, the first cell is the minimum cooling state and the second cell
is the maximum cooling state used in this map.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add dtsi file to support lg1313 SoC which based on Cortex-A53.
Also add dts file to support lg1312 reference board which based
on lg1313 SoC.
Signed-off-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Tree-wide replacement was done by commit 2ef7d5f342 (ARM, ARM64:
dts: drop "arm,amba-bus" in favor of "simple-bus"), but we have some
new users of "arm,amba-bus" at Linux 4.7-rc1. Eliminate them now.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds the device nodes for the DISP function blocks
comprising the display subsystem.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Cawa Cheng <cawa.cheng@mediatek.com>
Signed-off-by: Jie Qiu <jie.qiu@mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Update DTSI file to add the reset controller node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add node for ethernet interface and pinctrl pins.
Enable on odroid-C2 and P20x boards.
Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add DT nodes for additional UARTs (UART B & C in EE domain) and add pins
for all EE domain UARTs.
Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Update DTS and DTSI files to enable the pin controller. We also now
support the blinking blue LED on the Odroid-C2.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add two new buses in the DTS: hiu and periphs buses.
In the Amlogic S905/GXBB SoC several devices (clock / eth / pin
controllers, etc...) are mapped under these two buses. Add them in the
DT before starting to add new devices.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add support to the Northstar 2 Device tree file for the ARM CCI-400 PMU.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add all of the UARTs present on NS2 and enable them in the SVK device
tree file. Also, do some magic to make sure that uart3 is discovered as
ttyS0 (as that is the console UART).
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This enables the GPIO support for Broadcom NS2 SoC
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
We have one dual-port SATA3 AHCI controller present in
NS2 SoC.
This patch enables SATA3 AHCI controller and SATA3 PHY
for NS2 SoC in NS2 DT.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add the core io-domain nodes to grf and pmugrf which individual
boards than just have to enable and add the necessary supplies to.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the core io-domain nodes to grf and pmugrf which individual
boards than just have to enable and add the necessary supplies to.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The general register files do contain a lot of separate functions and
while some really are only registers with a lot of different 1-bit
settings, there are also a lot of them containing some bigger function
blocks. To be able to define these as sub-devices, make them simple-mfds.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: David Wu <david.wu@rock-chips.com>
Rockchip's rk3399 evaluation board has eMMC. Let's enable the
newly-added nodes.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add description for the SDHCI v5.1 eMMC controller on rk3399. Fix it to
200 MHz, to support all supported timing modes.
Note that 'rockchip,rk3399-sdhci-5.1' is not documented; we presumably
have a compliant Arasan controller, but let's have a rockchip property
as the canonical backup/precautionary measure. Per Heiko's previous
suggestion, let's not clutter the arasan doc with it.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Per the examples in
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt, we need the
grf node to be a simple-mfd in order to properly enumerate child devices
like our eMMC PHY.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
[directly mimic for the pmugrf, which will need the same change later
and there is no need to pollute commit history with another patch]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
These clocks are all core clocks used by many blocks/peripherals, many
of whose drivers don't set their clock rates at all. Let's assign
reasonable default clock rates for these core clocks, so that these
peripherals get something reasonable by default, and also so that if
child devices want to select a clock rate themselves, their muxes have
some reasonable parent clock rates to branch off of (rather than just
the boot-time defaults).
This helps the eMMC PHY, for one, to get a reasonable ACLK rate.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Drop 0x from unit address of gic as this is the desired form for
a unit address.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Warning (unit_address_vs_reg): Node /regulator@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /regulator@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /regulator@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /regulator@4 has a unit name, but no reg property
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /cache-controller@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,dvc/dvc@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,dvc/dvc@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@6 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@7 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@8 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,src/src@9 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@6 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@7 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@8 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@ec500000/rcar_sound,ssi/ssi@9 has a unit name, but no reg property
Move the cache-controller nodes under the cpus node, and make their unit
names and reg properties match the MPIDR values.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Hook up the RWDT device node to the SYSC "always-on" PM Domain, for a
more consistent device-power-area description in DT.
Cfr. commit 38dbb45ee4 ("arm64: dts: r8a7795: Use SYSC "always-on" PM
Domain")
Fixes: f43838a7ae014cba ("arm64: dts: r8a7795: Add RWDT node")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
There are some requirements about the GIC-400 memory layout and its
mapping if using 64k aligned base addresses like on r8a7795.
See e.g.
http://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=21550029f709072aacf3b9
Map the whole memory range instead of only 0x2000. This will fix
the issue that some hypervisors, e.g. Xen, fail to handle the
interrupts correctly.
Signed-off-by: Pooya Keshavarzi <Pooya.Keshavarzi@de.bosch.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
On the Salvator-X development board, the RTS and CTS pins of debug
serial-1 port SCIF1 are wired to the CP2102 Serial-USB bridge. Reflect
this in the DTS by adding the "uart-has-rtscts" property to the scif1
device node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This is a collection of a few late fixes and other misc. stuff that
had dependencies on things being merged from other trees.
The Renesas R-Car power domain handling, and the Nvidia Tegra USB
support both hand notable changes that required changing the DT binding
in a way that only provides compatibility with old DT blobs on new
kernels but not vice versa. As a consequence, the DT changes
are based on top of the driver changes and are now in this branch.
For NXP i.MX and Samsung Exynos, the changes in here depend on
other changes that got merged through the clk maintainer tree.
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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late DT updates from Arnd Bergmann:
"This is a collection of a few late fixes and other misc stuff that had
dependencies on things being merged from other trees.
The Renesas R-Car power domain handling, and the Nvidia Tegra USB
support both hand notable changes that required changing the DT
binding in a way that only provides compatibility with old DT blobs on
new kernels but not vice versa. As a consequence, the DT changes are
based on top of the driver changes and are now in this branch.
For NXP i.MX and Samsung Exynos, the changes in here depend on other
changes that got merged through the clk maintainer tree"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (35 commits)
ARM: dts: exynos: Add support of Bus frequency using VDD_INT for exynos5422-odroidxu3
ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos542x SoC
ARM: dts: exynos: Add NoC Probe dt node for Exynos542x SoC
ARM: dts: exynos: Add support of bus frequency for exynos4412-trats/odroidu3
ARM: dts: exynos: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
ARM: dts: exynos: Add support of bus frequency using VDD_INT for exynos3250-rinato
ARM: dts: exynos: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodes
ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4210
ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos4x12
ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4x12
ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos3250
ARM: dts: exynos: Add DMC bus frequency for exynos3250-rinato/monk
ARM: dts: exynos: Add DMC bus node for Exynos3250
ARM: tegra: Enable XUSB on Nyan
ARM: tegra: Enable XUSB on Jetson TK1
ARM: tegra: Enable XUSB on Venice2
ARM: tegra: Add Tegra124 XUSB controller
ARM: tegra: Move Tegra124 to the new XUSB pad controller binding
ARM: dts: r8a7794: Use SYSC "always-on" PM Domain
ARM: dts: r8a7793: Use SYSC "always-on" PM Domain
...
We continue ramping up platform support for 64-bit ARM machines,
with 111 individual non-merge changesets touching 21 platforms.
The LG1312 platform is completely new and is the first ARM
platform by LG that we support in the mainline kernel. Two other
SoCs got added that are updated versions of existing SoC
families, so the port mainly consists of new dts files:
- The Hisilicon Hip06/D03 is the latest server platform
from Huawei/Hisilicon, and follows the Hip05/D02 platform.
- Rockchip RK3399 follows the 32-bit RK3288 that is popular
in low-end Chromebooks and the 64-bit RK3368 that is mainly
found in chinese Android TV boxes.
The 96Boards HiKey based on the Hisilicon Hi6220 (Kirin 620)
gets a long-awaited overhaul with a lot of devices enabled in
the DT, so it should be much more usable with a mainline kernel
now. See also
https://plus.google.com/111524780435806926688/posts/PeGb2VsNhJd
A lot of work went into enabling new device drivers on existing
machines, but we also have a couple of new commercially
available machines:
- Google Pixel C laptop based on Tegra210
- Hardkernel Odroid C2 Based on Amlogic Meson GXBB (S905)
- Geekbuying GeekBox based on Rockchip RK3368
And finally, a couple of reference or development platforms
that are not end-user platforms but are used for trying out
the respective SoC platforms:
- Amlogic Meson GXBB P200 and P201 development systems
- NXP Layerscape 1043A QDS development board
- Hisilicon Hip06 D03 server board, as mentioned above
- LG1312 Reference Design
- RK3399 Evaluation Board
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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann:
"We continue ramping up platform support for 64-bit ARM machines, with
111 individual non-merge changesets touching 21 platforms.
The LG1312 platform is completely new and is the first ARM platform by
LG that we support in the mainline kernel. Two other SoCs got added
that are updated versions of existing SoC families, so the port mainly
consists of new dts files:
- The Hisilicon Hip06/D03 is the latest server platform from
Huawei/Hisilicon, and follows the Hip05/D02 platform.
- Rockchip RK3399 follows the 32-bit RK3288 that is popular in
low-end Chromebooks and the 64-bit RK3368 that is mainly found in
chinese Android TV boxes.
The 96Boards HiKey based on the Hisilicon Hi6220 (Kirin 620) gets a
long-awaited overhaul with a lot of devices enabled in the DT, so it
should be much more usable with a mainline kernel now. See also
https://plus.google.com/111524780435806926688/posts/PeGb2VsNhJd
A lot of work went into enabling new device drivers on existing
machines, but we also have a couple of new commercially available
machines:
- Google Pixel C laptop based on Tegra210
- Hardkernel Odroid C2 Based on Amlogic Meson GXBB (S905)
- Geekbuying GeekBox based on Rockchip RK3368
And finally, a couple of reference or development platforms that are
not end-user platforms but are used for trying out the respective SoC
platforms:
- Amlogic Meson GXBB P200 and P201 development systems
- NXP Layerscape 1043A QDS development board
- Hisilicon Hip06 D03 server board, as mentioned above
- LG1312 Reference Design
- RK3399 Evaluation Board"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (104 commits)
arm64: dts: marvell: add XOR node for Armada 3700 SoC
dt-bindings: document rockchip rk3399-evb board
arm64: dts: rockchip: add dts file for RK3399 evaluation board
arm64: dts: rockchip: add core dtsi file for RK3399 SoCs
dt-bindings: rockchip-dw-mshc: add description for rk3399
arm64: dts: marvell: Use a SoC-specific compatible for xHCI on Armada37xx
arm64: dts: marvell: Rename armada-37xx USB node
arm64: dts: marvell: Clean up armada-3720-db
Documentation: arm64: Add Hisilicon Hip06 D03 dts binding
arm64: dts: Add initial dts for Hisilicon Hip06 D03 board
arm64: dts: hip05: Add nor flash support
arm64: dts: hip05: fix its node without msi-cells
arm64: dts: r8a7795: Don't disable referenced optional clocks
arm64: dts: salvator-x: populate EXTALR
arm64: dts: r8a7795: enable PCIe on Salvator-X
arm64: dts: r8a7795: Add PCIe nodes
arm64: tegra: Add IOMMU node to GM20B on Tegra210
arm64: tegra: Add reference clock to GM20B on Tegra210
dt-bindings: Add documentation for GM20B GPU
dt-bindings: gk20a: Document iommus property
...
These are all the updates to device tree files for 32-bit platforms,
which as usual makes up the bulk of the ARM SoC changes: 462 non-merge
changesets, 450 files changed, 23340 insertions, 5216 deletions.
The three platforms that are added with the "soc" branch are here as well,
and we add some related machine files:
- For Aspeed AST2400/AST2500, we get the evaluation platform and
the Tyan Palmetto POWER8 mainboard that uses the AST2400 BMC
- For Oxnas 810SE, the Western Digital "My Book World Edition"
is added as the only platform at the moment.
- For ARM MPS2, the AN385 (Cortex-M3) and AN399 (Cortex-M7)
are supported
On the ARM Realview development platform, we now support all machines
with device tree, previously only the board files were supported, which
in turn will likely be removed soon.
Qualcomm IPQ4019 is the second generation ARM based "Internet Processor",
following the IPQ806x that is used in many high-end WiFi routers. This one
integrates two ath10k wifi radios that were previously on separate chips.
Other boards that got added for existing chips are:
- On Ti OMAP family:
- Amazon Kindle Fire, first generation, tablet and ebook reader
- OnRISC Baltos iR 2110 and 3220 embedded industrial PCs
- TI AM5728 IDK, TI AM3359 ICE-V2, and TI DRA722 Rev C EVM
development systems
- On Samsung EXYNOS platform:
- Samsung ARTIK5 evaluation board, see
https://www.artik.io/modules/overview/artik-5/
- On NXP i.MX platforms:
- Ka-Ro electronics TX6S-8034, TX6S-8035, TX6U-8033, TX6U-81xx,
TX6Q-1036, TX6Q-1110/-1130, TXUL-0010 and TXUL-0011 industrial
SoM modules
- Embest MarS Board i.MX6Dual DIY platform
- Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX and
SoloX Nitrogen6sx embedded boards
- Technexion Pico i.MX6UL compute module
- ZII VF610 Development Board
- On Marvell embedded (mvebu, orion, kirkwood) platforms:
- Linksys Viper (E4200v2 / EA4500) WiFi router
- Buffalo Kurobox Pro NAS
- On Qualcomm Snapdragon:
- Arrow DragonBoard 600c (96boards) with APQ8064 Snapdragon 600
- On Rockchips platform:
- mqmaker MiQi single-board computer
- On Altera SoCFPGA:
- samtec VIN|ING 1000 vehicle communication interface
- On Allwinner Sunxi platforms:
- Dserve DSRV9703C tablet
- Difrnce DIT4350 tablet
- Colorfly E708 Q1 tablet
- Polaroid MID2809PXE04 tablet
- Olimex A20 OLinuXino LIME2 single board computer
- Xunlong Orange Pi 2, Orange Pi One, and Orange Pi PC
single board computers
Across many platforms, bug fixes went in to address warnings that
dtc now emits with 'make dtbs W=1'. Further changes for device enablement
went into Ti OMAP, bcm283x (Raspberry Pi), bcm47xx (wifi router),
Ti Davinci, Samsung EXYNOS, Marvell mvebu/kirkwood/orion, NXP i.MX/Vybrid
NXP LPC18xx, NXP LPC32xx, Renesas shmobile/r-mobile/r-car, Rockchips
rk3xxx, ST Ux500, ST STi, Atmel AT91/SAMA5, Altera SoCFPGA, Allwinner
Sunxi, Sigma Designs Tango, NVIDIA Tegra, Socionext Uniphier and ARM
Versatile Express.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"These are all the updates to device tree files for 32-bit platforms,
which as usual makes up the bulk of the ARM SoC changes: 462 non-merge
changesets, 450 files changed, 23340 insertions, 5216 deletions.
The three platforms that are added with the "soc" branch are here as
well, and we add some related machine files:
- For Aspeed AST2400/AST2500, we get the evaluation platform and the
Tyan Palmetto POWER8 mainboard that uses the AST2400 BMC
- For Oxnas 810SE, the Western Digital "My Book World Edition" is
added as the only platform at the moment.
- For ARM MPS2, the AN385 (Cortex-M3) and AN399 (Cortex-M7) are
supported
On the ARM Realview development platform, we now support all machines
with device tree, previously only the board files were supported,
which in turn will likely be removed soon.
Qualcomm IPQ4019 is the second generation ARM based "Internet
Processor", following the IPQ806x that is used in many high-end WiFi
routers. This one integrates two ath10k wifi radios that were
previously on separate chips.
Other boards that got added for existing chips are:
Ti OMAP family:
- Amazon Kindle Fire, first generation, tablet and ebook reader
- OnRISC Baltos iR 2110 and 3220 embedded industrial PCs
- TI AM5728 IDK, TI AM3359 ICE-V2, and TI DRA722 Rev C EVM
development systems
Samsung EXYNOS platform:
- Samsung ARTIK5 evaluation board, see
https://www.artik.io/modules/overview/artik-5/
NXP i.MX platforms:
- Ka-Ro electronics TX6S-8034, TX6S-8035, TX6U-8033, TX6U-81xx,
TX6Q-1036, TX6Q-1110/-1130, TXUL-0010 and TXUL-0011 industrial
SoM modules
- Embest MarS Board i.MX6Dual DIY platform
- Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX and SoloX
Nitrogen6sx embedded boards
- Technexion Pico i.MX6UL compute module
- ZII VF610 Development Board
Marvell embedded (mvebu, orion, kirkwood) platforms:
- Linksys Viper (E4200v2 / EA4500) WiFi router
- Buffalo Kurobox Pro NAS
Qualcomm Snapdragon:
- Arrow DragonBoard 600c (96boards) with APQ8064 Snapdragon 600
Rockchips platform:
- mqmaker MiQi single-board computer
Altera SoCFPGA:
- samtec VIN|ING 1000 vehicle communication interface
Allwinner Sunxi platforms:
- Dserve DSRV9703C tablet
- Difrnce DIT4350 tablet
- Colorfly E708 Q1 tablet
- Polaroid MID2809PXE04 tablet
- Olimex A20 OLinuXino LIME2 single board computer
- Xunlong Orange Pi 2, Orange Pi One, and Orange Pi PC single board
computers
Across many platforms, bug fixes went in to address warnings that dtc
now emits with 'make dtbs W=1'. Further changes for device enablement
went into Ti OMAP, bcm283x (Raspberry Pi), bcm47xx (wifi router), Ti
Davinci, Samsung EXYNOS, Marvell mvebu/kirkwood/orion, NXP i.MX/Vybrid
NXP LPC18xx, NXP LPC32xx, Renesas shmobile/r-mobile/r-car, Rockchips
rk3xxx, ST Ux500, ST STi, Atmel AT91/SAMA5, Altera SoCFPGA, Allwinner
Sunxi, Sigma Designs Tango, NVIDIA Tegra, Socionext Uniphier and ARM
Versatile Express"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (458 commits)
ARM: dts: tango4: Import watchdog node
ARM: dts: tango4: Update cpus node for cpufreq
ARM: dts: tango4: Update DT to match clk driver
ARM: dts: tango4: Initial thermal support
arm/dst: Add Aspeed ast2500 device tree
arm/dts: Add Aspeed ast2400 device tree
ARM: sun7i: dt: Add pll3 and pll7 clocks
ARM: dts: sunxi: Add a olinuxino-lime2-emmc
ARM: dts: at91: sama5d4: add trng node
ARM: dts: at91: sama5d3: add trng node
ARM: dts: at91: sama5d2: add trng node
ARM: dts: at91: at91sam9g45 family: reduce the trng register map size
ARM: sun4i: dt: Add pll3 and pll7 clocks
ARM: sun5i: chip: Enable the TV Encoder
ARM: sun5i: r8: Add display blocks to the DTSI
ARM: sun5i: a13: Add display and TCON clocks
ARM: dts: ux500: configure the accelerometers open drain
ARM: mx5: dts: Enable USB OTG on M53EVK
ARM: dts: imx6ul-14x14-evk: Add audio support
ARM: dts: imx6qdl: Remove unneeded unit-addresses
...
Pull networking updates from David Miller:
"Highlights:
1) Support SPI based w5100 devices, from Akinobu Mita.
2) Partial Segmentation Offload, from Alexander Duyck.
3) Add GMAC4 support to stmmac driver, from Alexandre TORGUE.
4) Allow cls_flower stats offload, from Amir Vadai.
5) Implement bpf blinding, from Daniel Borkmann.
6) Optimize _ASYNC_ bit twiddling on sockets, unless the socket is
actually using FASYNC these atomics are superfluous. From Eric
Dumazet.
7) Run TCP more preemptibly, also from Eric Dumazet.
8) Support LED blinking, EEPROM dumps, and rxvlan offloading in mlx5e
driver, from Gal Pressman.
9) Allow creating ppp devices via rtnetlink, from Guillaume Nault.
10) Improve BPF usage documentation, from Jesper Dangaard Brouer.
11) Support tunneling offloads in qed, from Manish Chopra.
12) aRFS offloading in mlx5e, from Maor Gottlieb.
13) Add RFS and RPS support to SCTP protocol, from Marcelo Ricardo
Leitner.
14) Add MSG_EOR support to TCP, this allows controlling packet
coalescing on application record boundaries for more accurate
socket timestamp sampling. From Martin KaFai Lau.
15) Fix alignment of 64-bit netlink attributes across the board, from
Nicolas Dichtel.
16) Per-vlan stats in bridging, from Nikolay Aleksandrov.
17) Several conversions of drivers to ethtool ksettings, from Philippe
Reynes.
18) Checksum neutral ILA in ipv6, from Tom Herbert.
19) Factorize all of the various marvell dsa drivers into one, from
Vivien Didelot
20) Add VF support to qed driver, from Yuval Mintz"
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1649 commits)
Revert "phy dp83867: Fix compilation with CONFIG_OF_MDIO=m"
Revert "phy dp83867: Make rgmii parameters optional"
r8169: default to 64-bit DMA on recent PCIe chips
phy dp83867: Make rgmii parameters optional
phy dp83867: Fix compilation with CONFIG_OF_MDIO=m
bpf: arm64: remove callee-save registers use for tmp registers
asix: Fix offset calculation in asix_rx_fixup() causing slow transmissions
switchdev: pass pointer to fib_info instead of copy
net_sched: close another race condition in tcf_mirred_release()
tipc: fix nametable publication field in nl compat
drivers: net: Don't print unpopulated net_device name
qed: add support for dcbx.
ravb: Add missing free_irq() calls to ravb_close()
qed: Remove a stray tab
net: ethernet: fec-mpc52xx: use phy_ethtool_{get|set}_link_ksettings
net: ethernet: fec-mpc52xx: use phydev from struct net_device
bpf, doc: fix typo on bpf_asm descriptions
stmmac: hardware TX COE doesn't work when force_thresh_dma_mode is set
net: ethernet: fs-enet: use phy_ethtool_{get|set}_link_ksettings
net: ethernet: fs-enet: use phydev from struct net_device
...
- Support for the PMU in Broadcom's Vulcan CPU
- Dynamic event detection using the PMCEIDn_EL0 ID registers
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Merge tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 perf updates from Will Deacon:
"The main addition here is support for Broadcom's Vulcan core using the
architected ID registers for discovering supported events.
- Support for the PMU in Broadcom's Vulcan CPU
- Dynamic event detection using the PMCEIDn_EL0 ID registers"
* tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: perf: don't expose CHAIN event in sysfs
arm64/perf: Add Broadcom Vulcan PMU support
arm64/perf: Filter common events based on PMCEIDn_EL0
arm64/perf: Access pmu register using <read/write>_sys_reg
arm64/perf: Define complete ARMv8 recommended implementation defined events
arm64/perf: Changed events naming as per the ARM ARM
arm64: dts: Add Broadcom Vulcan PMU in dts
Documentation: arm64: pmu: Add Broadcom Vulcan PMU binding
- New board support of LS1043a-QDS from Freescale/NXP
- Add new compatible for LS1043A and LS2080A GPIO devices
- Update device tree bindings and sources for LS2080A fsl-mc device
- Update QSPI and DSPI support on LS1043A and LS2080A
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Merge tag 'imx-dt64-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
Merge "The Freescale/NXP arm64 device tree updates for 4.7" from Shawn Guo:
- New board support of LS1043a-QDS from Freescale/NXP
- Add new compatible for LS1043A and LS2080A GPIO devices
- Update device tree bindings and sources for LS2080A fsl-mc device
- Update QSPI and DSPI support on LS1043A and LS2080A
* tag 'imx-dt64-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: ls2080a: fsl-mc dt node updates
Documentation: fsl-mc: binding updates for MSIs, ranges, PHYs
arm64: dts: ls1043a: add the DTS node for QSPI support
Documentation: fsl-quadspi: Add fsl,ls1043a-qspi compatible string
arm64: dts: ls2080a: Add compatible "fsl,ls2080a-gpio" for ls2080a gpio nodes
arm64: dts: ls1043a: Add compatible "fsl,qoriq-gpio" for ls1043a gpio nodes
arm64: dts: ls2080a: update the DTS for QSPI and DSPI support
Documentation: fsl: dspi: Add fsl,ls2080a-dspi compatible string
arm64: dts: ls1043a-rdb: add the DTS for DSPI support
arm64: dts: add LS1043a-QDS board support
Documentation: DT: Add entry for Freescale LS1043a-QDS board
Complement the GM20B GPU device tree node on Tegra210 with missing
properties to make it usable.
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Merge tag 'tegra-for-4.7-gm20b' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64
Merge "arm64: tegra: Enable GM20B GPU on Tegra210" from Thierry Reding:
Complement the GM20B GPU device tree node on Tegra210 with missing
properties to make it usable.
* tag 'tegra-for-4.7-gm20b' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Add IOMMU node to GM20B on Tegra210
arm64: tegra: Add reference clock to GM20B on Tegra210
dt-bindings: Add documentation for GM20B GPU
dt-bindings: gk20a: Document iommus property
dt-bindings: gk20a: Fix typo in compatible name
- switch to label in the mvebu arm64 device tree
- use new clock binding on Armada 7K/8K
- improve SPI and I2C description on Armada 7K/8k
- add CP110 block adding PCIe, SATA and USB3
- add XOR support on Armada 3700
- few more little fix
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Merge tag 'mvebu-dt64-4.7-1' of git://git.infradead.org/linux-mvebu into next/dt64
Merge "mvebu dt64 for 4.7" from Gregory CLEMENT:
- switch to label in the mvebu arm64 device tree
- use new clock binding on Armada 7K/8K
- improve SPI and I2C description on Armada 7K/8k
- add CP110 block adding PCIe, SATA and USB3
- add XOR support on Armada 3700
- few more little fix
* tag 'mvebu-dt64-4.7-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: add XOR node for Armada 3700 SoC
arm64: dts: marvell: Use a SoC-specific compatible for xHCI on Armada37xx
arm64: dts: marvell: Rename armada-37xx USB node
arm64: dts: marvell: Clean up armada-3720-db
arm64: dts: marvell: enable several CP interfaces on Armada 7040-DB
arm64: dts: marvell: initial DT description of Armada 7K/8K CP110 master
arm64: dts: marvell: use the proper I2C controller compatible string for 7K/8K
arm64: dts: marvell: improve SPI flash description on Armada 7040-DB
arm64: dts: marvell: use new clock binding on Armada AP806
arm64: dts: marvell: add UART aliases and define stdout-path
arm64: dts: marvell: rename armada-ap806 XOR nodes
arm64: dts: marvell: clean up armada-7040-db
dts for the evaluation board of this chip and similar to the arm32
side also move the rk3368 thermal data into the core soc dtsi, as
there really is no need to keep it separate.
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Merge tag 'v4.7-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
Merge "Rockchip dts64 updates for v4.7 - part2" from Heiko Stübner:
Adding the new rk3399 core devicetree support as well as a board
dts for the evaluation board of this chip and similar to the arm32
side also move the rk3368 thermal data into the core soc dtsi, as
there really is no need to keep it separate.
* tag 'v4.7-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
dt-bindings: document rockchip rk3399-evb board
arm64: dts: rockchip: add dts file for RK3399 evaluation board
arm64: dts: rockchip: add core dtsi file for RK3399 SoCs
dt-bindings: rockchip-dw-mshc: add description for rk3399
clk: rockchip: export some necessary rk3399 clock ids
clk: rockchip: rename rga clock-id on rk3399
clk: rockchip: add general gpu soft-reset on rk3399
arm64: dts: rockchip: move the rk3368 thermal data into rk3368.dtsi
clk: rockchip: fix checkpatch errors in rk3399 dt-binding header
clk: rockchip: add dt-binding header for rk3399
In netdevice.h we removed the structure in net-next that is being
changes in 'net'. In macsec.c and rtnetlink.c we have overlaps
between fixes in 'net' and the u64 attribute changes in 'net-next'.
The mlx5 conflicts have to do with vxlan support dependencies.
Signed-off-by: David S. Miller <davem@davemloft.net>
are for the OMAP platforms, quoting Tony Lindgren:
Fixes for omaps for v4.6-rc cycle. All dts fixes, mostly
affecting voltages and pinctrl for various device drivers:
- Regulator minimum voltage fixes for omap5
- ISP syscon register offset fix for omap3
- Fix regulator initial modes for n900
- Fix omap5 pinctrl wkup instance size
The rest are all for different platforms:
- Allwinner:
Remove incorrect constraints from a dcdc1 regulator
- Alltera SoCFPGA:
Fix compilation in thumb2 mode
- Samsung exynos:
Fix a potential oops in the pm-domain error handling
- Davinci:
Avoid a link error if NVMEM is disabled
- Renesas:
Do not mark an external uart clock as disabled, to allow
probing the uarts
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann:
"Here are a couple last-minute fixes for ARM SoCs. Most of them are
for the OMAP platforms, the rest are all for different platforms.
OMAP:
All dts fixes, mostly affecting voltages and pinctrl for various
device drivers:
- Regulator minimum voltage fixes for omap5
- ISP syscon register offset fix for omap3
- Fix regulator initial modes for n900
- Fix omap5 pinctrl wkup instance size
Allwinner:
Remove incorrect constraints from a dcdc1 regulator
Alltera SoCFPGA:
Fix compilation in thumb2 mode
Samsung exynos:
Fix a potential oops in the pm-domain error handling
Davinci:
Avoid a link error if NVMEM is disabled
Renesas:
Do not mark an external uart clock as disabled, to allow probing
the uarts"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: davinci: only use NVMEM when available
ARM: SoCFPGA: Fix secondary CPU startup in thumb2 kernel
ARM: dts: omap5: fix range of permitted wakeup pinmux registers
ARM: dts: omap3-n900: Specify peripherals LDO regulators initial mode
ARM: dts: omap3: Fix ISP syscon register offset
ARM: dts: omap5-cm-t54: fix ldo1_reg and ldo4_reg ranges
ARM: dts: omap5-board-common: fix ldo1_reg and ldo4_reg ranges
arm64: dts: r8a7795: Don't disable referenced optional scif clock
ARM: EXYNOS: Properly skip unitialized parent clock in power domain on
ARM: dts: sun8i-q8-common: Do not set constraints on dc1sw regulator
Added 'channel' property, describing ethernet to CPU channel number.
Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Indexes should generally be avoided. This patch changes property port-id
to reg in dsaf port node.
Signed-off-by: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Armada 3700 SoC comprise one dual-channel XOR engine and this
patch adds its according representation.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This patch adds core dtsi file for Rockchip RK3399 SoCs.
The RK3399 has big/little architecture, which needs a separate
node for the PMU of each microarchitecture, for now it missing
the pmu node since the old one could not work well.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Tested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
- Fix its node without msi-cells for hip05
- Add nor flash node for hip05 D02 board
- Add initial dts for hip06 D03 board
- Reorder and add the hip06 D03 binding in the binding document
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Merge tag 'hip0x-dt-for-4.7' of git://github.com/hisilicon/linux-hisi into next/dt64
Merge "ARM64: DT: Hisilicon hip05 and hip06 updates for 4.7" Wei Xu:
- Fix its node without msi-cells for hip05
- Add nor flash node for hip05 D02 board
- Add initial dts for hip06 D03 board
- Reorder and add the hip06 D03 binding in the binding document
* tag 'hip0x-dt-for-4.7' of git://github.com/hisilicon/linux-hisi:
Documentation: arm64: Add Hisilicon Hip06 D03 dts binding
arm64: dts: Add initial dts for Hisilicon Hip06 D03 board
arm64: dts: hip05: Add nor flash support
arm64: dts: hip05: fix its node without msi-cells
Minor overlapping changes in the conflicts.
In the macsec case, the change of the default ID macro
name overlapped with the 64-bit netlink attribute alignment
fixes in net-next.
Signed-off-by: David S. Miller <davem@davemloft.net>
Even if the Armada 37xx does not any specific setup, the device tree
binding documentation requires to use a SoC-specific version
corresponding to the platform first followed by the generic version.
This patch introduce this new compatible string and updates the
documentation accordingly.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
No need to reflect the USB version in the node name.
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
[gregory.clement@free-electrons.com: drop Fixes tag as it is not a bug fix.]
Instead of duplicating the SoC's node hierarchy, including a bus node
named "internal-regs", reference the actually desired nodes by label,
like Berlin already does. Add labels where necessary.
Drop an inconsistent white line while at it.
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
[gregory.clement@free-electrons.com: drop Fixes tag as it is not a bug fix.]
The Hip06 soc has same cpu topology compared with Hip05, four clusters
and each cluster has quard Cortex-A57, but with different IO part,
like HNS, SAS and PCI, they are all upgraded. There are also not same
in ITS, MBIGEN and SMMU, etc.
This patch adds the initial dts for hip06 d03 board.
Note, there is no serial, because the soc use LPC uart, the serial node
is not needed.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This patch is to add support nor-flash. Notice, the pre-defined
partitions may not be used.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Fix commit abf9c25d55 ("arm64: dts: hip05: Append all gicv3 ITS
entries"), it forgets the property msi-cell, see arm,gic-v3.txt.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Hook up all devices that are part of the CPG/MSSR Clock Domain to the
SYSC "always-on" PM Domain, for a more consistent device-power-area
description in DT.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a device node for the System Controller.
Hook up the Cortex-A57 CPU cores and the Cortex-A57 and Cortex A53 L2
caches/SCUs to their respective PM Domains.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
clk_get() on a disabled clock node will return -EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their devices' clocks properties.
Update the various disabled external clock nodes to default to a
frequency of 0, but don't disable them, to prevent this.
Reported-by: Jürg Billeter <j@bitron.ch>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
It can be used for the watchdog.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The operating system driver can take advantage of the IOMMU to remove
the need for physically contiguous memory buffers.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This clock is required for the GPU to operate.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit enables several interfaces of the CP side of the Armada
7040 for the Armada 7040 DB board:
- one PCIe interface
- one SPI controller with an attached SPI flash
- one I2C controller
- one SATA controller
- two USB3 controllers
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit adds an initial Device Tree description for the CP110
master that is found in the Armada 7K and 8K SoCs. This initial
description describes:
- the system controller (to provide clocks)
- three PCIe interfaces
- the SATA interface
- the I2C controllers
- the SPI controllers
For the record, the organization of the SoCs is as follows:
- 7020: dual-core AP, one CP110 (master)
- 7040: quad-core AP, one CP110 (master)
- 8020: dual-core AP, two CP110s (master and slave)
- 8040: quad-core AP, two CP110s (master and slave)
For this reason, all of the 7020, 7040, 8020 and 8040 include
armada-cp110-master.dtsi. When support for the second CP110 (slave)
used in 8020 and 8040 will be added, the .dtsi files for those SoCs
will in addition include armada-cp110-slave.dtsi.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The I2C controller found in the Marvell Armada 7K/8K provides the
bridge/offloading features, so the Device Tree should use the
marvell,mv78230-i2c compatible string instead of marvell,mv64xxx-i2c.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit slightly improves the description of the SPI flash
connected to the SPI controller of the Armada 7040, by:
- Using the more generic "jedec,spi-nor" compatible string, which
lets the driver auto-detect the exact SPI flash type.
- Removing the silly comment about the Chip Select, since reg = <0>
is explicit enough.
- Switching to the new Device Tree binding to describe flash
partitions.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit updates the Marvell AP806 Device Tree description to make
use of the accepted clock Device Tree binding.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit adds the necessary UART aliases to the main Armada 7K/8K
.dtsi file, and uses them to define the /chosen/stdout-path property
on the Armada 7040 DB board.
Suggested-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Node names should not contain an instance number, the unit address
serves to distinguish nodes of the same name. So rename the XOR nodes
to just xor@<address>.
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
[Thomas:
- remove labels, they are really not needed for XOR engines.
- remove the Fixes: tag, as this is not a fix.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Instead of duplicating the node hierarchy, reference the nodes by label,
adding labels where necessary.
Drop some trailing or inconsistent white lines while at it.
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
[Thomas: drop Fixes tag as it is not a bug fix.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Because debug dsaf port was separated from service dsaf port, this patch
updates the related configurations of hns dts, changes it to match with
the new binding files. This also removes enet nodes which don't exist in
d02 board.
Signed-off-by: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
updates to the fsl-mc node for full functionality:
-msi-parent is needed for interrupt support
-ranges is needed to enable the bus driver to translate bus addresses
-dpmac nodes provide a basis for relating dpmac objects to PHYs
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
clk_get() on a disabled clock node will return -EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their devices' clocks properties.
Update the disabled external scif clock node so that it
is not disabled to prevent this.
Reported-by: Jürg Billeter <j@bitron.ch>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: fix for v4.6 extracted from a larger patch targeted at v4.7]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Include the development base board, which is equipped with some
devices such as EEPROM.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Anup enables a bunch of standard peripherals in the Northstar 2 DTS: PL330
DMA, GIC maintenance interrupt, PL022 SPI controller
- Anup also re-orgnanizes the clock Device Tree fragments into a separate file
for consistency with how other Broadcom SoCs are doing this
- Luke switches the SMP enable-method and reboot from a spin-table + syscon to
the standard PSCI 1.0 firmware interface
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Merge tag 'arm-soc/for-4.7/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64
Pull "Broadcom ARM64-based SoC Device Tree changes" from Florian Fainelli:
- Anup enables a bunch of standard peripherals in the Northstar 2 DTS: PL330
DMA, GIC maintenance interrupt, PL022 SPI controller
- Anup also re-orgnanizes the clock Device Tree fragments into a separate file
for consistency with how other Broadcom SoCs are doing this
- Luke switches the SMP enable-method and reboot from a spin-table + syscon to
the standard PSCI 1.0 firmware interface
* tag 'arm-soc/for-4.7/devicetree-arm64' of http://github.com/Broadcom/stblinux:
arm64: dts: NS2 secondary core enablement via PSCI
arm64: dts: Add ARM PL022 SPI DT nodes for NS2
arm64: dts: Move NS2 clock DT nodes to separate DT file
arm64: dts: Add maintenance interrupt for GIC in NS2 DT
arm64: dts: Add ARM PL330 DMA DT node for NS2
This patch set only includes a single change to
fix the compatible string for SATA controllers on
X-Gene v2 SOC platforms.
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Merge tag 'xgene-dts-for-v4.7-part1' of https://github.com/AppliedMicro/xgene-next into next/dt64
Merge "First part of X-Gene DTS changes queued for v4.7" from Duc Dang:
This patch set only includes a single change to
fix the compatible string for SATA controllers on
X-Gene v2 SOC platforms.
* tag 'xgene-dts-for-v4.7-part1' of https://github.com/AppliedMicro/xgene-next:
arm64: dts: apm: Fix compatible string for X-Gene 2 SATA controller DTS node
- Reserve memory regions for Hi6220
- Add sp804 timer node for Hi6220
- Add cpu and cluster level's low power state for Hi6220
- Add gpio configuration nodes for Hi6220
- Add pinctrl configuration nodes for Hi6220
- Add spi related nodes for Hi6220
- Add i2c nodes for Hi6220
- Add i2c nodes to work with mezzanine boards
- Add usb nodes for Hi6220
- Add mailobx node for Hi6220
- Add SRAM node and stub clock node for Hi6220
- Add pinctrl nodes for uarts and enable them
- Add LED nodes for hi6220-hikey board
- Add hi655x pmic node for Hi6220
- Add dwmmc nodes for Hi6220
- Add wifi nodes support for Hi6220-Hikey board
- Register thermal sensor for Hi6220
- Register Hi6220's thermal zone for power allocator
- Add L2 cache topology for Hi6220
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Merge tag 'hi6220-dt-for-4.7' of git://github.com/hisilicon/linux-hisi into next/dt64
Pull "ARM64: DT: Hisilicon Hi6220 soc and hikey board updates for 4.7" from Wei Xu
- Reserve memory regions for Hi6220
- Add sp804 timer node for Hi6220
- Add cpu and cluster level's low power state for Hi6220
- Add gpio configuration nodes for Hi6220
- Add pinctrl configuration nodes for Hi6220
- Add spi related nodes for Hi6220
- Add i2c nodes for Hi6220
- Add i2c nodes to work with mezzanine boards
- Add usb nodes for Hi6220
- Add mailobx node for Hi6220
- Add SRAM node and stub clock node for Hi6220
- Add pinctrl nodes for uarts and enable them
- Add LED nodes for hi6220-hikey board
- Add hi655x pmic node for Hi6220
- Add dwmmc nodes for Hi6220
- Add wifi nodes support for Hi6220-Hikey board
- Register thermal sensor for Hi6220
- Register Hi6220's thermal zone for power allocator
- Add L2 cache topology for Hi6220
* tag 'hi6220-dt-for-4.7' of git://github.com/hisilicon/linux-hisi:
arm64: dts: Add L2 cache topology to Hi6220
arm64: dts: register Hi6220's thermal zone for power allocator
arm64: dts: register Hi6220's thermal sensor
arm64: dts: add wifi nodes support for hi6220-hikey
arm64: dts: add dwmmc nodes for hi6220
arm64: dts: hikey: Add hi655x pmic dts node
arm64: dts: add LED nodes for hi6220-hikey
arm64: dts: hi6220: add pinctrl for uarts and enable them
arm64: dts: add Hi6220's stub clock node
arm64: dts: add mailbox node for Hi6220
arm64: dts: Add hi6220 usb node
arm64: dts: hikey: enable i2c0 and i2c1 for working with mezzanine boards
arm64: dts: add all hi6220 i2c nodes
arm64: dts: add Hi6220 spi configuration nodes
arm64: dts: add Hi6220 pinctrl configuration nodes
arm64: dts: Add Hi6220 gpio configuration nodes
arm64: dts: enable idle states for Hi6220
arm64: dts: add sp804 timer node for Hi6220
arm64: dts: Reserve memory regions for hi6220
Just one update: Support for external expansion bus useful for
additional hardware e.g.LogicTile Express daughterboards (Brian Starkey)
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Merge tag 'juno-for-v4.7/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64
Pull "ARMv8 Juno DT updates for v4.7" from Sudeep Holla:
Just one update: Support for external expansion bus useful for
additional hardware e.g.LogicTile Express daughterboards (Brian Starkey)
* tag 'juno-for-v4.7/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: Add external expansion bus to DT
A couple of cleanups and fixes to various device trees, enable power and
volume keys on Jetson TX1, use stdout-path to define the serial port (so
it doesn't have to be specified on the kernel command-line) and add
Google Pixel C (a.k.a. Smaug) support.
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Merge tag 'tegra-for-4.7-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64
Merge "arm64: tegra: Changes for v4.7-rc1" from Thierry Reding
A couple of cleanups and fixes to various device trees, enable power and
volume keys on Jetson TX1, use stdout-path to define the serial port (so
it doesn't have to be specified on the kernel command-line) and add
Google Pixel C (a.k.a. Smaug) support.
* tag 'tegra-for-4.7-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Enable cros-ec and charger on Smaug
arm64: tegra: Add pinmux for Smaug board
arm64: tegra: Add stdout-path for various boards
arm64: tegra: Remove unused #power-domain-cells property
arm64: tegra: Add gpio-keys nodes for Smaug
arm64: tegra: Enable power and volume keys on Jetson TX1
arm64: tegra: Add support for Google Pixel C
arm64: tegra: Replace legacy *,wakeup property with wakeup-source
arm64: tegra: Fix copy/paste typo in several DTS includes
arm64: tegra: Remove 0, prefix from unit-addresses
1. Add PL330 DMA controller and Thermal Management Unit to Exynos 7.
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Merge tag 'samsung-dt64-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64
Merge "Samsung Device Tree ARM64 updates and improvements for v4.7" from Krzysztof Kozlowski:
1. Add PL330 DMA controller and Thermal Management Unit to Exynos 7.
* tag 'samsung-dt64-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: Add nodes for pdma0 and pdma1 for exynos7
arm64: dts: exynos: Add TMU node for exynos7
In order to be standard to manage for rockchip SoCs, move the thermal
data into rk3368 dtsi, we needn't to add a new file for thermal.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Declare PSCI-1.0 node and enable CPU_ON method via PSCI. Spin-table
memreserve has been removed as well as syscon based reset, as PSCI-1.0
expects reset implementation in firmware.
Signed-off-by: Luke Starrett <luke.starrett@broadcom.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This adds the thermal controller and auxadc nodes to the Mediatek MT8173
dtsi file.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This patch adds the L2 cache topology on Hi6220. Hi6220 has two
clusters, every cluster has 512KiB L2 cache (32KiB x 16 ways).
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
With profiling Hi6220's power modeling so get dynamic coefficient and
sustainable power. So pass these parameters from DT.
Now enable power allocator with only one actor for CPU part, so directly
use cluster0's thermal sensor for monitoring temperature.
Reviewed-by: Javi Merino <javi.merino@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add all three dwmmc nodes description for hi6220
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add the mfd hi655x dts node and regulator support on hi6220 platform.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Fei Wang <w.f@huawei.com>
Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Reviewed-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add LED nodes for hi6220-hikey. There are total 6 LEDs on HiKey.
Four general purposed, one for WiFi activity, and one for Bluetooth
activity.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Enable SRAM node and stub clock node for Hi6220, which uses mailbox
channel 1 for CPU's frequency change.
Furthermore, add the CPU clock phandle in CPU's node and using
operating-points-v2 to register operating points. So can be used by
cpufreq-dt driver.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This patch add device mailbox node for Hi6220 in DT.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
In HiKey board dts file, enable i2c0 and i2c1 for working with 96boards' LS
mezzanine.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This patch adds all I2C nodes for the Hi6220 SoC. This hi6220 Soc
use this I2C IP of Synopsys Designware for HiKey board.
Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add Hi6220 spi configuration nodes. Disable by default in hi6220.dtsi
and enable it in board dts for usage of 96boards LS mezzanine board.
Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add cpu and cluster level's low power state for Hi6220.
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add sp804 timer for hi6220, so it can be used as broadcast timer.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
On Hi6220, below memory regions in DDR have specific purpose:
0x05e0,0000 - 0x05ef,ffff: For MCU firmware using at runtime;
0x06df,f000 - 0x06df,ffff: For mailbox message data;
0x0740,f000 - 0x0740,ffff: For MCU firmware's section;
0x3e00,0000 - 0x3fff,ffff: For OP-TEE.
This patch reserves these memory regions in DT.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add nodes for the ChromeOS Embedded Controller and for the gas gauge
connected to the I2C bus that it controls.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Juno development platform has an external expansion bus which can
be used for additional hardware (e.g. LogicTile Express daughterboards).
Add this bus to the Juno base device-tree.
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Brian Starkey <brian.starkey@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
nodes for the core rk3368 and some cleanups for gpio-keys,
mmc and tsadc.
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Merge tag 'v4.7-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
This contains the rk3368-geekbox as new board, mailbox device
nodes for the core rk3368 and some cleanups for gpio-keys,
mmc and tsadc.
* tag 'v4.7-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
Documentation: devicetree: rockchip: Document rk3368-GeekBox
arm64: dts: rockchip: Add rk3368 GeekBox dts
arm64: dts: rockchip: Clean up gpio-keys nodes
dt-bindings: Add vendor prefix for GeekBuying.com
arm64: dts: rockchip: Add rk3368 mailbox device nodes
arm64: dts: rockchip: remove broken-cd from emmc and sdio
arm64: dts: rockchip: fix the incorrect otp-out pin on rk3368
Signed-off-by: Olof Johansson <olof@lixom.net>
Add initial dtsi file to support lg1312 SoC which based on
Cortex-A53. Also add dts file to support lg1312 reference board
which based on lg1312 SoC.
Signed-off-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
* Use generic pinctrl properties in DT for salvator-x board
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Merge tag 'renesas-arm64-cleanup-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64
Renesas ARM64 Based SoC Cleanup for v4.7
* Use generic pinctrl properties in DT for salvator-x board
* tag 'renesas-arm64-cleanup-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: salvator-x: use generic pinctrl properties
Signed-off-by: Olof Johansson <olof@lixom.net>
We have two ARM PL022 SPI instances in NS2 SoC. On NS2 SVK,
one of the ARM PL022 SPI host has Silabs si3226x slic connected
to chip-select #0 whereas second ARM PL022 SPI host has Atmel
AT25 EEPROM connected to chip-select #0.
This patch adds ARM PL022, Silabs si3226x, and Atmel AT25
DT nodes in NS2 DT and NS2 SVK DT respectively.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
For more readabilty and consistency with other Broadcom SoCs, we move
all NS2 clock DT nodes from main SoC DT file to a separate DT file.
We also update the license header in ns2.dtsi as-per new Broadcom
convention.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The KVM ARM64 requires GIC maintenance interrupt for VGIC emulation
so this patch adds the missing "interrupts" attribute to GIC node in
NS2 DT.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
We have one ARM PL330 DMA instance with 8 channels in
NS2 SoC. Let's enable it for NS2 in NS2 DT.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Pramod KUMAR <pramodku@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This patch adds device tree nodes for pdma0 and pdma1 controllers
found on exynos7 SoCs.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
The compatible "fsl,qoriq-gpio" is used by gpio driver:
drivers/gpio/gpio-mpc8xxx.c to implement general gpio
functionalities.
The chip-specific compatible "fsl,ls2080a-gpio" may be
used to fix potential gpio IP block errata or other
chip-specific gpio issues.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The compatible "fsl,qoriq-gpio" is used by gpio driver:
drivers/gpio/gpio-mpc8xxx.c to implement general gpio
functionalities.
The chip-specific compatible "fsl,ls1043a-gpio" may be
used to fix potential gpio IP block errata or other
chip-specific gpio issues.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch adds dts nodes for DSPI on LS1043A-RDB.
Signed-off-by: Yunhui Cui <B56489@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
For Tegra boards, the device-tree alias serial0 is used for the console
and so add the stdout-path information so that the console no longer
needs to be passed via the kernel boot parameters.
For tegra132-norrin the alias serial0 is not defined and so add this.
This has been tested on tegra132-norrin and tegra210-p2371-0000.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Remove the "#power-domain-cells" property which was incorrectly
included by commit e53095857166 ("arm64: tegra: Add Tegra210
support").
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add gpio-keys nodes for the volumn controls, lid switch, tablet mode and
power button.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
[treding@nvidia.com: use symbolic names for input types and codes]
[treding@nvidia.com: use wakeup-source instead of gpio-key,wakeup]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a gpio-keys device tree node to represent the Power, Volume Up and
Volume Down keys found on Jetson TX1.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add initial device-tree support for Google Pixel C (a.k.a. Smaug) based
upon Tegra210 SoC with 3 GiB of LPDDR4 RAM.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Though the keyboard and other driver will continue to support the legacy
"gpio-key,wakeup", "nvidia,wakeup-source" boolean property to enable the
wakeup source, "wakeup-source" is the new standard binding.
This patch replaces all the legacy wakeup properties with the unified
"wakeup-source" property in order to avoid any further copy-paste
duplication.
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The comment about the 8250 vs. APB DMA-enabled UART devices that was
added for Tegra20 and Tegra30 in commit b6551bb933 ("ARM: tegra: dts:
add aliases and DMA requestor for serial controller") introduced a typo
that has since spread to various other DTS include files. Fix all
occurrences of this typo.
Suggested-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses with
more than one cell.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The GeekBox contains an MXM3 module with a Rockchip RK3368 SoC.
Some connectors are available directly on the module.
This adds initial support, namely serial, USB, GMAC, eMMC, IR and TSADC.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add minimal DT files for the Amlogic P20x development boards, based on
the Amlogic S905/GXBB SoC.
Cc: Andreas Färber <afaerber@suse.de>
Cc: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Add minimal DT files for the Hardkernel ODROID-C2 board based on the
Amlogic S905/GXBB SoC.
Used the other gxbb boards from Andreas Färber as a starting point.
Cc: Andreas Färber <afaerber@suse.de>
Cc: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Apparently, it's not valid to have an alias point to a disabled device.
Fix this by moving the aliases that are used (serial0) into the files
that use them, and remove aliases to disabled devices (serial1).
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Resolve the following warnings from new dtc by adding the unit address:
DTC arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dtb
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
DTC arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dtb
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
DTC arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dtb
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
Fixes: cc733bc906 ("ARM64: dts: amlogic: Add Tronsmart Vega S95 configs")
Signed-off-by: Andreas Färber <afaerber@suse.de>
The LS1043a-QDS board is a high-performance computing, evaluation,
development, and test platform supporting the LS1043a SoC.
shawn.guo: sort the entries in Makefile alphabetcially
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The PCI memory windows available in vulcan.dtsi are limited to 128MB
for 32-bit BARs, and 4GB for 64-bit BARs. Given the memory mapped IO
space available in arm64, these windows can be increased substantially
to support more use cases.
The change increases the 32-bit window to 256MB and the 64-bit window
to 128 GB. The firmware on vulcan boards will use these ranges as well.
PCI IO windows are not supported on Vulcan, so remove them instead of
keeping an unused value.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Drop superfluous #address-cells and #size-cells.
Use KEY_POWER define for 116.
Rename sub-nodes to avoid new dtc warnings.
Reported-by: Julien Chauveau <chauveau.julien@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Julien Chauveau <chauveau.julien@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds mailbox device nodes in dts.
Mailbox is used by the Rockchip CPU cores to communicate
requests to MCU processor.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch adds TMU node, related temprature sensor and triping
point data for Atlas cpu core found on exynos7 SoC.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
