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arm64: dts: r8a7795: Add SYSC PM Domains
Add a device node for the System Controller. Hook up the Cortex-A57 CPU cores and the Cortex-A57 and Cortex A53 L2 caches/SCUs to their respective PM Domains. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -10,6 +10,7 @@
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#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7795-sysc.h>
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/ {
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compatible = "renesas,r8a7795";
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@ -39,6 +40,7 @@ a57_0: cpu@0 {
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x0>;
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device_type = "cpu";
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power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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};
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@ -47,6 +49,7 @@ a57_1: cpu@1 {
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x1>;
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device_type = "cpu";
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power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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};
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@ -54,6 +57,7 @@ a57_2: cpu@2 {
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x2>;
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device_type = "cpu";
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power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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};
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@ -61,6 +65,7 @@ a57_3: cpu@3 {
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x3>;
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device_type = "cpu";
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power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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};
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@ -68,12 +73,14 @@ a57_3: cpu@3 {
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L2_CA57: cache-controller@0 {
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compatible = "cache";
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power-domains = <&sysc R8A7795_PD_CA57_SCU>;
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cache-unified;
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cache-level = <2>;
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};
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L2_CA53: cache-controller@1 {
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compatible = "cache";
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power-domains = <&sysc R8A7795_PD_CA53_SCU>;
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cache-unified;
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cache-level = <2>;
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};
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@ -302,6 +309,12 @@ cpg: clock-controller@e6150000 {
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#power-domain-cells = <0>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7795-sysc";
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reg = <0 0xe6180000 0 0x0400>;
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#power-domain-cells = <1>;
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};
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audma0: dma-controller@ec700000 {
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compatible = "renesas,rcar-dmac";
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reg = <0 0xec700000 0 0x10000>;
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