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arm64: dts: r8a7795: Increase the size of GIC-400 mapped registers

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There are some requirements about the GIC-400 memory layout and its
mapping if using 64k aligned base addresses like on r8a7795.

See e.g.

http://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=21550029f709072aacf3b9

Map the whole memory range instead of only 0x2000. This will fix
the issue that some hypervisors, e.g. Xen, fail to handle the
interrupts correctly.

Signed-off-by: Pooya Keshavarzi <Pooya.Keshavarzi@de.bosch.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Pooya Keshavarzi 2016-04-19 08:29:55 +02:00 committed by Simon Horman
parent 3cac478cce
commit 457f47b765
1 changed files with 2 additions and 2 deletions
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4
arch/arm64/boot/dts/renesas/r8a7795.dtsi
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@ -157,9 +157,9 @@ gic: interrupt-controller@0xf1010000 {
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x2000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x2000>;
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};