Commit Graph

8353 Commits

Author SHA1 Message Date
Wen Yang
35fb722074 drm/amd/display: fix a compile warning
Fix comile warning like,
  CC [M]  drivers/gpu/drm/i915/gvt/execlist.o
  CC [M]  drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.o
  CC [M]  drivers/gpu/drm/radeon/btc_dpm.o
  CC [M]  drivers/isdn/hisax/avm_a1p.o
  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.o
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In function ‘dcn10_update_mpcc’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1903:9: warning: missing braces around initializer [-Wmissing-braces]
  struct mpcc_blnd_cfg blnd_cfg = {0};
         ^
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1903:9: warning: (near initialization for ‘blnd_cfg.black_color’) [-Wmissing-braces]

Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Wen Yang <wen.yang99@zte.com.cn>
Reviewed-by: Jiang Biao <jiang.biao2@zte.com.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:13 -05:00
Emily Deng
fc0faf0440 drm/amdgpu/sriov: Only sriov runtime support use kiq
For sriov, don't use kiq in exclusive mode, as don't know how long time
it will take, some times it will occur exclusive timeout.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:12 -05:00
Evan Quan
52de2ea74f drm/amdgpu: fix sdma doorbell range setting
Use the old doorbell range setting until the driver is
able to support more sdma queues.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:12 -05:00
Rex Zhu
a00ead2b39 drm/amdgpu: Fix compile warning
In function ‘gfx_v9_0_check_fw_write_wait’:
warning: enumeration value ‘CHIP_TAHITI’ not handled in switch [-Wswitch]

Always add default case in case there is no match

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:11 -05:00
Christian König
1b1f2fecb6 drm/amdgpu: rework ctx entity creation
Use a fixed number of entities for each hardware IP.

The number of compute entities is reduced to four, SDMA keeps it two
entities and all other engines just expose one entity.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:11 -05:00
Christian König
a245daf3d7 drm/amdgpu: cleanup HW_IP query
Move the code into a separate function.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:10 -05:00
Yintian Tao
9c70d10ae7 drm/amdgpu: remove fulll access for suspend phase1
There is no need for gpu full access for suspend phase1
because under virtualization there is no hw register access
for dce block.

Signed-off-by: Yintian Tao <yttao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:09 -05:00
Emily Deng
3890d11153 drm/amdgpu: use kiq to do invalidate tlb
To avoid the tlb flush not interrupted by world switch, use kiq and one
command to do tlb invalidate.

v2:
Refine the invalidate lock position.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-and-Tested-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:08 -05:00
Emily Deng
39b62541aa drm/amdgpu: Remove the sriov checking and add firmware checking
Unify bare metal and sriov, and add firmware checking for
reg write and reg wait unify command.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-and-Tested-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:08 -05:00
Jun Lei
dd73043534 drm/amd/display: implement DPMS DTN test v2
[why]
Existing DTN infrastructure in driver is hacky.  It uses implicit log
names, and also incorrect escape ID.

[how]
- Implement using generic DTN escape ID.
- Move file logging functionality from driver to to script; driver now outputs to string/buffer
- Move HWSS debug functionality to separate c file
- Add debug functionalty for per-block logging as CSV
- Add pretty print in python

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:07 -05:00
Anthony Koo
d82f99422b drm/amd/display: move edp fast boot optimization flag to stream
[Why]
During S4/S3 stress test it is possible to resume from S4 without
calling mode set on eDP, meaning high level optimization flag is not
reset. If this is followed by an S3 resume call, driver will see
optimization flag is set and consume it and think backend is powered
on when in fact it is not.

This results in PHY being off in sequence where
S4->Resume->S3->Resume->ApplyOpt->black screen.

[How]
Move optimization flag to stream instead of a DC flag.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:07 -05:00
David Francis
728098352e drm/amd/display: Combine dce80 and dce100 i2c hw functions
[Why]
There are two versions of the hw function pointers: one for dce80
and one for all other versions.  These paired functions are
nearly identical.  dce80 and dce100 should not require
different i2c access functions.

[How]
Combine each pair of functions into a single function.  Mostly
the new functions are based on the dce100 versions as those
versions are newer, support more features, and
were more maintained.

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:06 -05:00
Nikola Cornij
d75de8ac94 drm/amd/display: Define registers for dcn10
Define register for dcn10 for future changes

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:06 -05:00
SivapiriyanKumarasamy
eb385204b2 drm/amd/display: Program csc matrix as part of stream update
Add csc_transform struct to dc_stream_update, and program if set when
updating streams

Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:05 -05:00
David Francis
c85e6e546e drm/amd/display: Create new i2c resource
[Why]
I2C code did not match dc resource model and was generally
unpleasant

[How]
Move code into new svelte dce_i2c files, replacing various i2c
objects with two structs: dce_i2c_sw and dce_i2c_hw.  Fully split
sw and hw code paths.  Remove all redundant declarations.  Use
address lists to distinguish between versions.  Change dce80 code
to newer register access macros.

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:05 -05:00
Paul Menzel
2c1e9bca44 drm/amdgpu: Do not evict VRAM on APUs with disabled HIBERNATE
Improve commit d796d844 (drm/radeon/kms: make hibernate work on IGPs) to
only migrate VRAM objects if the Linux kernel is actually built with
support for hibernation (suspend to disk).

The better solution is to get the information, if this is suspend or
hibernate, from `amdgpu_device_suspend()`, but that’s more involved, so
apply the simple solution first.

Link: https://bugs.freedesktop.org/show_bug.cgi?id=107277
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:03 -05:00
Huang Rui
28a160277a drm/amdgpu: add status checking after fw is loaded
The status field must be 0 after FW is loaded.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:03 -05:00
Christian König
09b6f25b55 drm/amdgpu: fix VM size reporting on Raven
Raven doesn't have an VCE block and so also no buggy VCE firmware.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:02 -05:00
Rex Zhu
fdd34271a3 drm/amdgpu: Set clock ungate state when suspend/fini
After set power ungate state, set clock ungate state
before when suspend or fini.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:01 -05:00
Rex Zhu
05df1f01b2 drm/amdgpu: Set power ungate state when suspend/fini
Unify to set power ungate state at the begin of suspend/fini.
Remove the workaround code for gfx off feature in
amdgpu_device.c.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:01 -05:00
Rex Zhu
1112a46b48 drm/amdgpu: Refine function name and function args
There are no any logical changes here.

1. change function names:
   amdgpu_device_ip_late_set_pg/cg_state to
   amdgpu_device_set_pg/cg_state.
2. add a function argument cg/pg_state, so
   we can enable/disable cg/pg through those functions

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:00 -05:00
SivapiriyanKumarasamy
8ab5617279 drm/amd/display: Program gamut remap as part of stream update
Add gamut remap to dc_stream_update struct, and program if set when updating
streams.

Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:11:00 -05:00
Krunoslav Kovac
72ac71a7e6 drm/amd/display: HDR dynamic meta should be treated as stream update
[Why]
Recently we fixed HDR static meta using AFMT registers to be treated as
fast stream update.
Dynamic meta is still being treated as (full) surface update because it
touches HUBP and it travels with pipe data.
Here we change it to be (fast) stream update.
Note, originally we also wanted to redesign here a bit, but without OS
level support for true dynamic meta, it's left the same. We are simply
using HW that can do dynamic meta to send HDR static meta, I still prefer
keeping it in one static meta type then defining dynamic meta types to
hold the same info. Once we know how OS interfaces look like, we can
do proper design.

[How]
Move dyn meta update from update_hubp_dpp to commit_planes_do_stream_update

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:59 -05:00
Krunoslav Kovac
e71f8ca1a7 drm/amd/display: Handle HDR meta update as fast update
[Why]
Vesa DPMS tool sends different HDR meta in OS flips without changing output
parameters. We don't properly update HDR info frame:
- we label HDR meta update as fast update
- when updating HW info frame, we only do it if full update

[How]
It should still be fast update, so when doing HW infoframe update,
do it always no matter the update type.
Also, don't request passive flip for HDR meta update only without output
transfer function or color space changed.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:59 -05:00
Alvin lee
0e4af5f367 drm/amd/display: Program vsc_infopacket in commit_planes_for_stream
Signed-off-by: Alvin lee <alvin.lee3@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:58 -05:00
Alvin lee
1336926f43 drm/amd/display: Enable Stereo in Dal3
- program infoframe for Stereo
- program stereo flip control registers properly

v2: Add missing license headers

Signed-off-by: Alvin lee <alvin.lee3@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:57 -05:00
SivapiriyanKumarasamy
27e2e20774 drm/amd/display: Program vline interrupt on FAST update
Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:57 -05:00
Samson Tam
1e7e86c43f drm/amd/display: decouple front and backend pgm using dpms_off as backend enable flag
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:56 -05:00
Anthony Koo
69ff884526 drm/amd/display: add config for sending VSIF
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:56 -05:00
Harry Wentland
4c1fa3630b drm/amd/display: Don't force UPDATE_TYPE_FULL if stream_update has hdr_static_metadata
This was missed when pushing public patch for 3e3a40b03847 (drm/amd/display:
Updated HDR Static Metadata to directly take info packet raw)

This is currently no problem yet since we're not doing HDR on Linux yet.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:55 -05:00
Anthony Koo
bf2af91cb3 drm/amd/display: Correct rounding calcs in mod_freesync_is_valid_range
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:55 -05:00
Anthony Koo
953c2901c8 drm/amd/display: refactor vupdate interrupt registration
We only need to register once OS calls the interrupt control.
Also, if we are entering static screen mode, disable after ramping is done.
Disable shall be done via timer of 2 seconds regardless of ramping
complete or not, just to simplify.

Also, ramp to mid instead of min, due to better flicker performance...

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:54 -05:00
Anthony Koo
9410a3776b drm/amd/display: fix LFC tearing at top of screen
Tearing occurred because new VTOTAL MIN/MAX was being programmed
too early.
The flip can happen within the VUPDATE high region, and the new min/max
would take effect immediately. But this means that frame is not variable
anymore, and tearing would occur when the flip actually happens.

The fixed insert duration should be programmed on the first VUPDATE
interrupt instead.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:54 -05:00
Anthony Koo
be922ff750 drm/amd/display: Add back code to allow for rounding error
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:53 -05:00
Anthony Koo
050790cc59 drm/amd/display: Fix bug that causes black screen
Ignore MSA bit on DP display is usually set during SetTimings, but
there was a case where the module thought refresh rate was not valid
and ignore MSA bit was not set.

Later, a valid refresh rate range was requested but since ignore MSA bit
not set, it caused black screen.

Issue if with how the module checked for VRR support. Fix up that logic.
DM should call new valid_range function to determine if timing is supported.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:53 -05:00
Anthony Koo
ff6014d63a drm/amd/display: Fix bug where refresh rate becomes fixed
This issue occurs if refresh rate range is very small and lfc is not used.
When frame spikes occur, refresh rate becomes fixed and will not restore properly

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:52 -05:00
Anthony Koo
e80e944608 drm/amd/display: add method to check for supported range
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:51 -05:00
Anthony Koo
98e6436d3a drm/amd/display: Refactor FreeSync module
Remove dependency on internal sink map and instead
use existing stream and plane state

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:51 -05:00
Harry Wentland
8c3db1284a drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module
Add code to tear down freesync modules when disabled.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:50 -05:00
Feifei Xu
bfcea52042 drm/amdgpu:change VEGA booting with firmware loaded by PSP
With PSP firmware loading, TMR mc address is supposed to be used.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:50 -05:00
Evan Quan
d4e838431d drm/amdgpu: added support 2nd UVD instance
Added psp fw loading support for vega20 2nd UVD instance.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:49 -05:00
Christian König
0d346a14c6 drm/amdgpu: use entity instead of ring for CS
Further demangle ring from entity handling.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:48 -05:00
Christian König
8290268f31 drm/amdgpu: move context related stuff to amdgpu_ctx.h
Further unmangle amdgpu.h.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:48 -05:00
Christian König
86275d090f drm/amdgpu: remove ring lru handling
Not needed any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:47 -05:00
Christian König
869a53d4d7 drm/amdgpu: remove the queue manager
Not needed any more since that is now done by the scheduler.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:47 -05:00
Christian König
72a4c072ca drm/amdgpu: use scheduler load balancing for compute CS
Start to use the scheduler load balancing for userspace compute
command submissions.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:46 -05:00
Christian König
845e6fdf3b drm/amdgpu: use scheduler load balancing for SDMA CS
Start to use the scheduler load balancing for userspace SDMA
command submissions.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:45 -05:00
Christian König
3798e9a6e6 drm/amdgpu: use new scheduler load balancing for VMs
Instead of the fixed round robin use let the scheduler balance the load
of page table updates.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:45 -05:00
James Zhu
aa5873dca4 drm/amdgpu: Change VCE booting with firmware loaded by PSP
With PSP firmware loading, TMR mc address is supposed to be used.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:44 -05:00
Dan Carpenter
ff30e9e850 drm/amdgpu: fix integer overflow test in amdgpu_bo_list_create()
We accidentally left out the size of the amdgpu_bo_list struct.  It
could lead to memory corruption on 32 bit systems.  You'd have to
pick the absolute maximum and set "num_entries == 59652323" then size
would wrap to 16 bytes.

Fixes: 920990cb08 ("drm/amdgpu: allocate the bo_list array after the list")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Bas Nieuwenhuizen <basni@chromium.org>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:42 -05:00
Rex Zhu
e51ee68ff2 drm/amd/pp: OverDrive gfx domain voltage on Tonga
Also ajust the gfx domain voltage on Tonga when user overdriver
the voltage.

For Tonga, Driver do not update user's setting to voltage table
in smu, we only pick up a minimum value from voltage table that
not less than the user's setting.

v2: fix a typo

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:41 -05:00
Rex Zhu
a54594752a drm/amdgpu: Cancel the delay work when suspend
Cancel the delay work to avoid the corner case that
ib test was not running when suspend

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:41 -05:00
Alex Deucher
6dddaeef4f drm/amdgpu: remove experimental flag for vega20
Now that PSP and SMU support is in place.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:40 -05:00
Feifei Xu
3082be1aea drm/amdgpu/psp: Enlarge PSP TMR SIZE from 3M to 4M.
Enlarge the PSP TMR SIZE to 4M for dual UVD fw front-door loading.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:39 -05:00
Evan Quan
218a9fbc8a drm/amdgpu: update vega20 sdma golden settings
Updated vega20 SDMA0 and SDMA1 golden settings.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:39 -05:00
Feifei Xu
54d682d9a5 drm/amdgpu/gfx9: Update gfx9 golden settings.
Update the goldensettings for vega20.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:38 -05:00
Evan Quan
ff50e15b00 drm/amd/powerplay: added voltage boot time calibration
Run AFLL BTC after upload pptable and before enabling
all smu features.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:38 -05:00
Evan Quan
efa7ac67a8 drm/amd/powerplay: remove max DCEFCLK limitation
The latest SMU fw removes the limitation that required
UCLK >= DCEFCLK.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:37 -05:00
Evan Quan
16ed0ff275 drm/amd/powerplay: allow slow switch only if NBPState enabled
Otherwise there may be potential SMU performance issues.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:37 -05:00
Evan Quan
5d923a6928 drm/amd/powerplay: correct the argument for PPSMC_MSG_SetUclkFastSwitch
The argument was set wrongly. Fast/slow switch was asked when there is
actually a slow/fast switch needed.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:36 -05:00
Evan Quan
d940def9ab drm/amd/powerplay: avoid enabling/disabling uvd/vce dpm twice
For vega20, there are two UVD rings which share one powerplay instance.
Under some case(two rings used parallel), the uvd dpm is disabled twice
which causes the SMC hang.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:36 -05:00
Evan Quan
be6a55a11a drm/amd/powerplay: remove setting soc floor voltage before sending pptable
SOC voltage is not able to switch and forced to low 0.8V when running HEVC.
Thus the test failed.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:35 -05:00
Evan Quan
3490738f9b drm/amd/powerplay: enable fclk ss by default
Set fclk ss as enabled on default.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:35 -05:00
Likun Gao
0df5295c99 drm/amdgpu/vg20: Change the load type of vega20 to psp (v2)
Modified the vega20 load type to psp now that psp
support is implemented.

v2: squash in fixes history (Alex)

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:34 -05:00
Feifei Xu
654f761cfa drm/amdgpu: Add psp 11.0 support for vega20. (v2)
Add psp 11.0 code for vega20 and enable it.  PSP is the
security processor for the GPU.  It handles firmware
loading and GPU resets among other things.

v2: whitespace fix, enable support, adjust reg includes (Alex)

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:34 -05:00
Evan Quan
a6637313c7 drm/amdgpu: enable vega20 powerplay support
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:33 -05:00
Evan Quan
8c191fe3d5 drm/amd/powerplay: update vega20 clocks threshold settings on power state adjust
UVD, VCE and SOC clocks need to be taken into consideration. Also, the
thresholds need be updated correspondingly when stable power state is selected.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:32 -05:00
Evan Quan
acd116243a drm/amd/powerplay: revise vega20 PPSMC_MSG_SetSoftMin/[Max]ByFreq settings
UVD, VCE and Socclk also need to be taken into consideration when
setting PPSMC_MSG_SetSoftMinByFreq and PPSMC_MSG_SetSoftMaxByFreq.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:32 -05:00
Evan Quan
d617d4d730 drm/amd/powerplay: new interfaces for overdrive vega20 sclk and mclk
Add support for the new SMU firmware interface for clock adjustment.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:31 -05:00
Evan Quan
7dd67c0d42 drm/amd/powerplay: initialize vega20 overdrive settings
The initialized overdrive settings are taken from vbios and SMU(
by PPSMC_MSG_TransferTableSmu2Dram).

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:31 -05:00
Evan Quan
bc9b8c45b8 drm/amd/powerplay: conv the vega20 pstate sclk/mclk into necessary 10KHz unit
Powerplay uses 10KHz units.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:30 -05:00
Evan Quan
8dd97d6bc2 drm/amd/powerplay: add vega20 pre_display_config_changed callback
fix possible handshake hang and video playback crash

Corner cases:
 - Handshake between SMU and DCE causes hangs when CRTC is not
   enabled
 - System crash occurs when starting 4K playback with Movies and TV
   in an SLS configuration

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:30 -05:00
Evan Quan
b8497699ef drm/amd/powerplay: export vega20 stable pstate clocks
Needed for querying the stable pstate clocks.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:29 -05:00
Evan Quan
fff7e3e049 drm/amd/powerplay: correct force clock level related settings for vega20 (v2)
1. The min/max level is determined by soft_min_level/soft_max_level.
2. Vega20 comes with pptable v3 which has no vdd related
table(vdd_dep_on_socclk, vdd_dep_on_mclk) support.
3. Vega20 does not support separate fan feature control(enable or
disable).

v2: squash in fixes:
- bug fix for force dpm level settings
- fix wrong data type

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:29 -05:00
Evan Quan
7c2912a26d drm/amd/powerplay: init vega20 uvd/vce powergate status on dpm setup
This is essentially necessary when uvd/vce dpm is not enabled yet.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:28 -05:00
Evan Quan
982b903194 drm/amd/powerplay: support workload profile query and setup for vega20
Support the power profile API.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:28 -05:00
Evan Quan
da958630d5 drm/amd/powerplay: add the hw manager for vega20 (v3)
hwmgr is the interface for the driver to setup state
structures which are used by the smu for managing the
power state.

v2: squash in fixes:
- update set_watermarks_for_clocks_ranges to use common code
- drop unsupported apis
- correct MAX_REGULAR_DPM_NUMBER value
- multimonitor fixes
- add check for vbios pptable version
- revise dpm table setup
- init fclk dpm state
- Remove unused definition in vega20_hwmgr
- support power limit setup
- enable vega20 to honour DAL clock limits
- comment out dump_table debugging
v3: switch to SOC15 register access macros

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:27 -05:00
Evan Quan
f0e7e5e2a8 drm/amd/powerplay: new interfaces for ActivityMonitor table with SMU
Vega20 has a new activity monitor table that is stored in memory.  Add
API to get and set the new table.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:27 -05:00
Evan Quan
f4eac80add drm/amd/powerplay: add the smu manager for vega20 (v2)
The SMU manager handles the driver interaction with the SMU
which handles clock and voltage controls.

v2: switch to SOC15 register access macros
    reserve space for ActivityMonitor table
    enable SMU fw loading
    Drop dead code from bringup

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:26 -05:00
Evan Quan
b9443b572c drm/amd/powerplay: add vega20_pptable.h (v2)
v2: squash in table size fixes

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:25 -05:00
Evan Quan
79df9413f7 drm/amd/powerplay: add vega20_ppsmc.h (v2)
v2: update to latest.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:25 -05:00
Evan Quan
5fef5b1e7d drm/amd/powerplay: add smu11_driver_if.h (v4)
v2: cleanup
v3: fit the latest 40.6 smc fw
v4: update to latest.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:24 -05:00
Evan Quan
5f51ab41e7 drm/amd/powerplay: add vega20_inc.h (v2)
v2: use thm 11.0.2 headers

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:24 -05:00
Evan Quan
7a0d7089c7 drm/amdgpu: update atomfirmware.h
Add struct atom_smc_dpm_info_v4_3

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:23 -05:00
Feifei Xu
fe3c948918 drm/amdgpu: Add nbio 7.4 support for vega20 (v3)
Some register offset in nbio v7.4 are different with v7.0.
We need a seperate nbio_v7_4.c for vega20.

v2: fix doorbell range for sdma (Alex)
v3: squash in static fix (kbuild test robot)

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:23 -05:00
Alex Deucher
25eaa565c4 Revert "drm/amdgpu: Add nbio support for vega20 (v2)"
Revert this to add proper nbio 7.4 support.

This reverts commit f5b2e1fa321eff20a9418ebd497d8a466f024a85.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:22 -05:00
Feifei Xu
e9126d09ee drm/amdgpu/include: Add mp 11.0 header files. (v2)
Add the system management controller v11.0 header files.

v2: cleanup

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:22 -05:00
Evan Quan
e6af616a78 drm/amdgpu/include: add thm 11.0.2 headers
Headers for thermal controller.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:21 -05:00
Feifei Xu
c62d3cd0dd drm/amdgpu/include: Add sdma0/1 4.2 register headerfiles. (v3)
These are the System DMA register headers for vega20.

v2: cleanups (Alex)
v3: add missing licenses (Alex)

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:21 -05:00
Feifei Xu
1f902edecb drm/amdgpu/include: Add nbio 7.4 header files (v4)
v2: Cleanups (Alex)
v3: More updates (Alex)
v4: more cleanups (Alex)

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:20 -05:00
Mauro Rossi
00ecc6e6d4 drm/amdgpu: enable ABGR and XBGR formats (v2)
Add support for DRM_FORMAT_{A,X}BGR8888 in amdgpu with amd dc disabled

(v2) Crossbar registers are defined and used to swap red and blue channels,
     keeping the existing coding style in each of the dce modules.
     After setting crossbar bits in fb_swap, use bitwise OR for big endian
     where required in DCE6 and DCE8 which do not rely on REG_SET_FIELD()

Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:19 -05:00
Mauro Rossi
bcd47f60ab drm/amd/display: enable ABGR and XBGR formats (v4)
SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 is supported in amd/display/dc/dc_hw_types.h
and the necessary crossbars register controls to swap red and blue channels
are already implemented in drm/amd/display/dc/dce/dce_mem_input.c

(v4) Logic to handle new formats is added only in amdgpu_dm module.

Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:18 -05:00
Alex Deucher
a19c3bea8e drm/amdgpu/powerplay/vega10: enable AVFS control via ppfeaturemask
Allow the user to disable AFVS via ppfeaturemask for debugging.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:18 -05:00
Alex Deucher
b4abff4bb2 drm/amdgpu/powerplay/smu7: enable AVFS control via ppfeaturemask
Allow the user to disable AFVS via ppfeaturemask for debugging.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:17 -05:00
Alex Deucher
a4ead3e5d6 drm/amdgpu: add AVFS control to PP_FEATURE_MASK
Add a ppfeaturemask flag to disable AVFS control.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:17 -05:00
Tony Cheng
5d0e7e5caa drm/amd/display: dc 3.1.62
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Steven Chiu <Steven.Chiu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:16 -05:00
Leo (Sunpeng) Li
5678094038 drm/amd/display: Remove redundant non-zero and overflow check
[Why]
Unsigned int is guaranteed to be >= 0, and read_channel_reply checks for
overflows. read_channel_reply also returns -1 on error, which is what
dc_link_aux_transfer is expected to return on error.

[How]
Remove the if-statement. Return result of read_channel_reply directly.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:16 -05:00
Charlene Liu
2f14bc8968 drm/amd/display: add retimer log for HWQ tuning use.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:15 -05:00
Dmytro Laktyushkin
f137586b2b drm/amd/display: fix dml handling of mono8/16 pixel formats
mono formats are treated exactly the same as equivallent bpp
444 formats. Dml validation however lacks 444 8 bit format
while dml perf param calculation lacks mono format support

This change makes them equivallent as far as the enum is concerned
to avoid having to update dml

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:15 -05:00
Dmytro Laktyushkin
c4621988d4 drm/amd/display: Add dprefclk value to dce_dccg
This allows us to avoid any vbios bugs when initializing clocks

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:14 -05:00
Gloria Li
94a4ffd1d4 drm/amd/display: fix PIP bugs on Dal3
[Why]
There are outstanding bugs for PIP in Dal3:
-Crash when toggling PIP visibility
-Global Alpha is not working, Adjusting global alpha
 doesn’t have an effect
-Cursor is not working with pip plane and pipe splits
-One flash occurs when cursor enters PIP plane from
 top/bottom
-Crash when moving PIP plane off the screen

[How]
Resolve divide by 0 error
Implement global alpha
Program cursor on all pipes
Add dst rects' x and y offests into cursor position
Disable cursor when it is beyond bottom/top edge

Signed-off-by: Gloria Li <geling.li@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:14 -05:00
Tony Cheng
f1220c876d drm/amd/display: dc 3.1.61
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Steven Chiu <Steven.Chiu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:13 -05:00
Rex Zhu
6c1fd99bc6 drm/amdgpu: Cancel gfx off delay work when driver fini/suspend
there may be gfx off delay work pending when suspend/driver
unload, need to cancel them first.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:12 -05:00
Alex Deucher
ec2e082a79 drm/amdgpu/powerplay: check vrefresh when when changing displays
Compare the current vrefresh in addition to the number of displays
when determining whether or not the smu needs updates when changing
modes. The SMU needs to be updated if the vbi timeout changes due
to a different refresh rate.  Fixes flickering around mode changes
in some cases on polaris parts.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:12 -05:00
Boyuan Zhang
7ea34ea3e8 drm/amdgpu: fix emit frame size and comments for jpeg
Fix vcn jpeg ring emit fence size in dword, and fix the naming in comments.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:11 -05:00
Boyuan Zhang
36a12bd0b4 drm/amdgpu: add emit trap for vcn jpeg
Add emit trap command in jpeg emit fence call.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:11 -05:00
Boyuan Zhang
7f31077cad drm/amdgpu: enable system interrupt for jrbc
Enable system interrupt for jrbc during engine starting time.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:10 -05:00
Boyuan Zhang
44287b7190 drm/amdgpu: add system interrupt mask for jrbc
Add new mask for enabling system interrupt for jrbc.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:10 -05:00
Boyuan Zhang
8709890892 drm/amdgpu: add system interrupt register offset header
Add new register offset for enabling system interrupt.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:09 -05:00
Boyuan Zhang
eb4f699920 drm/amdgpu: add emit reg write reg wait for vcn jpeg
The emit_reg_write_reg_wait function was not assigned for vcn jpeg.
This patch adds it back.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:09 -05:00
Alex Deucher
54f16ebfde drm/amdgpu/pp: endian fixes for processpptables.c
Properly swap when reading from the vbios.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:08 -05:00
Alex Deucher
2cf0109951 drm/amdgpu/pp: endian fixes for process_pptables_v1_0.c
Properly swap when reading from the vbios.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:08 -05:00
Huang Rui
c2d358d724 drm/amdgpu: move missed gfxoff entry into amdgpu_gfx header
Move missed gfxoff entry to amdgpu_gfx.h.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:05 -05:00
Huang Rui
4473e1db31 drm/amdgpu: move vm definitions into amdgpu_vm header
Demangle amdgpu.h.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:05 -05:00
Huang Rui
c082b99878 drm/amdgpu: move gmc macros into amdgpu_gmc header
Demangle amdgpu.h.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:04 -05:00
Huang Rui
5df585258f drm/amdgpu: move display definitions into amdgpu_display header
Demangle amdgpu.h.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:04 -05:00
Huang Rui
9e21fc56fe drm/amdgpu: remove useless gds switch macro
Demangle amdgpu.h.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:03 -05:00
Huang Rui
0a7845db93 drm/amdgpu: move ring macros into amdgpu_ring header
Demangle amdgpu.h.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:03 -05:00
Christian König
7febe4bfd5 drm/scheduler: fix setting the priorty for entities (v2)
Since we now deal with multiple rq we need to update all of them, not
just the current one.

v2: Trivial: Removed unused variable (Alex)

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:00 -05:00
Rex Zhu
bf9b1d9dc7 drm/amdgpu: Delay 100ms to enable gfx off feature
Original 500ms delay seems a bit large.
Change to 100 ms suggested by Christian.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:10:00 -05:00
Vitaly Prosyak
1fdf7a4b1f drm/amd/display: Add check for num of entries in gamma
This check avoids potential bugs related to gamma.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:59 -05:00
Vitaly Prosyak
dc6c981d20 drm/amd/display: Use DGAM ROM or RAM
[Why]
Optimize gamma programming

[How]
Use ROM for optimization when it is possible.
Use RAM only when it is necessary.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:58 -05:00
Nikola Cornij
d02e07948f drm/amd/display: Print DPP DTN log info only for enabled pipes
[why]
There is currently a dependency on the order in which tests are executed.
This is because the non-relevant state info is being printed, which results
in the output based on the state from the previous test.

[how]
Print DPP DTN log only if the pipe is enabled.
In addition to the affected per-submission DTN golden logs, included in this
change is also DTN golden log update for pre-submission tests.
The other DTN golden logs affected by this change will be updated upon
nightly test run (which will generate the updated DTN logs).

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:58 -05:00
Martin Tsai
9b5349f74a drm/amd/display: correct image viewport calculation
[why]
We didn't transfer the camera/video viewport coordinate
when doing rotation and mirror.

[how]
To correct the viewport coordinate in calculate_viewport().

Signed-off-by: Martin Tsai <Martin.Tsai@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:57 -05:00
Mikita Lipski
1b369d3c0d drm/amd/display: pass the right num of modes added
[why]
In case if edid is null or corrupted we need to manually add
a single failsafe mode (640x480). If zero modes returned
DRM adds a different failsafe mode that is not accepted by
DP 1.2 compliance test

[how]
Return the number of modes manually added

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:57 -05:00
Huang Rui
2cddc50e98 drm/amdgpu: move gem definitions into amdgpu_gem header
Demangle amdgpu.h.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:56 -05:00
Huang Rui
6462c0071b drm/amdgpu: move psp macro into amdgpu_psp header
Demangle amdgpu.h.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:56 -05:00
Huang Rui
55560046d5 drm/amdgpu: move firmware definitions into amdgpu_ucode header
Demangle amdgpu.h.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:55 -05:00
Huang Rui
bb7743bc20 drm/amdgpu: move sdma definitions into amdgpu_sdma header
Demangle amdgpu.h.
Furthermore, SDMA is used for moving and clearing the data buffer, so the header
also need be included in ttm.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:55 -05:00
Huang Rui
aa47d11728 drm/amdgpu: move ih definitions into amdgpu_ih header
Demangle amdgpu.h

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:54 -05:00
Huang Rui
448fe1928c drm/amdgpu: move gfx definitions into amdgpu_gfx header
Demangle amdgpu.h

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:54 -05:00
Rex Zhu
fd28705388 drm/amd/pp: Delete duplicated interface in hwmgr_func
gfx off support in smu can be via powergate_gfx interface.
so remove the gfx_off_control interface.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:53 -05:00
Rex Zhu
3fded222f4 drm/amdgpu: Disable gfx off if VCN is busy
this patch is a workaround for the gpu hang
at video begin/end time if gfx off is enabled.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:53 -05:00
Rex Zhu
408acede87 drm/amdgpu: Ctrl gfx off via amdgpu_gfx_off_ctrl
use amdgpu_gfx_off_ctrl function so driver can arbitrate
whether the gfx ip can be power off or power on.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:52 -05:00
Rex Zhu
1e317b99f0 drm/amdgpu: Put enable gfx off feature to a delay thread
delay to enable gfx off feature to avoid gfx on/off frequently
suggested by Alex and Evan.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:52 -05:00
Rex Zhu
d23ee13fba drm/amdgpu: Add amdgpu_gfx_off_ctrl function
v2:
   1. drop the special handling for the hw IP
      suggested by hawking and Christian.
   2. refine the variable name suggested by Flora.

This funciton as the entry of gfx off feature.
we arbitrat gfx off feature enable/disable in this
function.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:51 -05:00
Nicholas Kazlauskas
5a83c93249 drm/amd/display: Add support for toggling DFS bypass
[Why]

If the hardware supports DFS bypass it will always be enabled after
creation of the DCCG. DFS bypass should only be enabled when
the current stream consists of a single embedded panel and the
minimum display clock is below the DFS bypass threshold.

[How]

Add a function to the DCCG table that updates the DFS bypass state
when setting the bandwidth. If the DFS bypass state is changed, the
clock needs to be reprogrammed to reflect this before the DPREFCLK
is updated for audio endpoints. The existing display clock value
is used as the target display clock value when reprogramming since the
resulting change will be equal or larger to the current value.

These changes only specifically target dce110 but do offer a framework
for support on other applicable targets.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <David.Francis@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:50 -05:00
Nicholas Kazlauskas
1c8faa9aa0 drm/amd/display: Enable DFS bypass support in DC config
[Why]

We explicitly disable DFS bypass support when creating DC. Support
for this feature should now be in place so it can be left implicitly
enabled.

[How]

Remove the line that disables DFS bypass support.

Note: This option was actually reset to false anyway for most of
the hardware I've tested on making this particular line misleading
in the first place. This patch also fixes this issue.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:50 -05:00
Nicholas Kazlauskas
4e60536d09 drm/amd/display: Set DFS bypass flags for dce110
[Why]

While there is support for using and quering DFS bypass clocks the
hardware is never notified to enter DFS bypass mode for dce110.

[How]

Add a flag that can be set when programming the display engine PLL
to enable DFS bypass mode. If this flag is set then the hardware is
notified to enter DFS bypass mode and the correct display engine clock
frequency can be acquired.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:49 -05:00
Tony Cheng
2cb3bcdb33 drm/amd/display: dal 3.1.60
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:49 -05:00
Jun Lei
265f5ba6c2 drm/amd/display: Move PME to function pointer call semantics
[why]
Legacy IRI style is not linux friendly.

[how]
New function pointer call
semantics will be used for all future PPLIB/DAL interfaces, and also
some existing will be refactored.  This change defines how the
new function pointer structures will look, as well as implements

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:48 -05:00
Charlene Liu
a465feae60 drm/amd/display: pass compat_level to hubp
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:48 -05:00
Rex Zhu
f688b614b6 drm/amd/pp: Implement get_performance_level for legacy dgpu
display can get clock info through this function.
implement this function for vega10 and old asics.
from vega12, there is no power state management,
so need to add new interface to notify display
the clock info

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:47 -05:00
Andrey Grodzovsky
65f7260b13 drm/amdgpu: Add job pipe sync dependecy trace
It's useful to trace any dependency a job has on prevoius
jobs.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:47 -05:00
Rex Zhu
c36628d898 drm/amgpu/acp: Implement set_powergating_state for acp
so driver can powergate acp block after asic initialized
to save power.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:44 -05:00
Rex Zhu
3a54d2c895 drm/amdgpu/acp: Powrgate acp via smu
Call smu to power gate/ungate acp instand of only
powr down acp tiles in acp block.
when smu power gate acp:
smu will turn off clock, power down acp tiles,check and
enter in ULV state.
when smu  ungate acp:
smu will exit ulv, turn on clocks, power on acp tiles.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:43 -05:00
Vijendar Mukunda
1062ddb6d5 drm/amd/amdgpu: Enabling Power Gating for Stoney platform
Removed condition checks to skip the power gating feature for
stoney platform.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Vijendar Mukunda <vijendar.mukunda@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:43 -05:00
Rex Zhu
be2d6aa51e drm/amdgpu: Power down acp if board uses AZ (v2)
if board uses AZ rather than ACP, we power down acp
through smu to save power.

v2: handle S3/S4 and hw_fini (Alex)

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:42 -05:00
Rex Zhu
982976d92f drm/amd/pp: Add ACP PG support in SMU
when ACP block not enabled, we power off
acp block to save power.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:41 -05:00
Rex Zhu
9650205a32 drm/amd/display: Fix bug use wrong pp interface
Used wrong pp interface, the original interface is
exposed by dpm on SI and paritial CI.

Pointed out by Francis David <david.francis@amd.com>

v2: dal only need to set min_dcefclk and min_fclk to smu.
    so use display_clock_voltage_request interface,
    instand of update all display configuration.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:41 -05:00
Andrey Grodzovsky
a3d9103ebf drm/amdgpu: Fix page fault and kasan warning on pci device remove.
Problem:
When executing echo 1 > /sys/class/drm/card0/device/remove kasan warning
as bellow and page fault happen because adev->gart.pages already freed by the
time amdgpu_gart_unbind is called.

BUG: KASAN: user-memory-access in amdgpu_gart_unbind+0x98/0x180 [amdgpu]
Write of size 8 at addr 0000000000003648 by task bash/1828
CPU: 2 PID: 1828 Comm: bash Tainted: G        W  O      4.18.0-rc1-dev+ #29
Hardware name: Gigabyte Technology Co., Ltd. AX370-Gaming/AX370-Gaming-CF, BIOS F3 06/19/2017
Call Trace:
dump_stack+0x71/0xab
kasan_report+0x109/0x390
amdgpu_gart_unbind+0x98/0x180 [amdgpu]
ttm_tt_unbind+0x43/0x60 [ttm]
ttm_bo_move_ttm+0x83/0x1c0 [ttm]
ttm_bo_handle_move_mem+0xb97/0xd00 [ttm]
ttm_bo_evict+0x273/0x530 [ttm]
ttm_mem_evict_first+0x29c/0x360 [ttm]
ttm_bo_force_list_clean+0xfc/0x210 [ttm]
ttm_bo_clean_mm+0xe7/0x160 [ttm]
amdgpu_ttm_fini+0xda/0x1d0 [amdgpu]
amdgpu_bo_fini+0xf/0x60 [amdgpu]
gmc_v8_0_sw_fini+0x36/0x70 [amdgpu]
amdgpu_device_fini+0x2d0/0x7d0 [amdgpu]
amdgpu_driver_unload_kms+0x6a/0xd0 [amdgpu]
drm_dev_unregister+0x79/0x180 [drm]
amdgpu_pci_remove+0x2a/0x60 [amdgpu]
pci_device_remove+0x5b/0x100
device_release_driver_internal+0x236/0x360
pci_stop_bus_device+0xbf/0xf0
pci_stop_and_remove_bus_device_locked+0x16/0x30
remove_store+0xda/0xf0
kernfs_fop_write+0x186/0x220
__vfs_write+0xcc/0x330
vfs_write+0xe6/0x250
ksys_write+0xb1/0x140
do_syscall_64+0x77/0x1e0
entry_SYSCALL_64_after_hwframe+0x44/0xa9
RIP: 0033:0x7f66ebbb32c0

Fix:
Split gmc_v{6,7,8,9}_0_gart_fini to postpone amdgpu_gart_fini to after
memory managers are shut down since gart unbind happens
as part of this procedure

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:40 -05:00
Emily Deng
4f0ecd36f2 amdgpu: fix multi-process hang issue
SWDEV-146499: hang during multi vulkan process testing

cause:
the second frame's PREAMBLE_IB have clear-state
and LOAD actions, those actions ruin the pipeline
that is still doing process in the previous frame's
work-load IB.

fix:
need insert pipeline sync if have context switch for
SRIOV (because only SRIOV will report PREEMPTION flag
to UMD)

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:40 -05:00
Christian König
9296435729 drm/amdgpu: fix preamble handling
At this point the command submission can still be interrupted.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:39 -05:00
Christian König
1cadf2b368 drm/amdgpu: fix VM clearing for the root PD
We need to figure out the address after validating the BO, not before.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27 11:09:39 -05:00
Linus Torvalds
5e8704ac1c amdgpu and panel/misc fixes.
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Merge tag 'drm-next-2018-08-24' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "Just a couple of fixes"

  One MAINTAINERS address change, two panels fixes, and set of amdgpu
  fixes (build fixes, display fixes and some others)"

* tag 'drm-next-2018-08-24' of git://anongit.freedesktop.org/drm/drm:
  drm/edid: Add 6 bpc quirk for SDC panel in Lenovo B50-80
  drm/amd/display: Don't build DCN1 when kcov is enabled
  Revert "drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86"
  drm/amdgpu/display: disable eDP fast boot optimization on DCE8
  drm/amdgpu: fix amdgpu_amdkfd_remove_eviction_fence v3
  drm/amdgpu: fix incorrect use of drm_file->pid
  drm/amdgpu: fix incorrect use of fcheck
  drm/powerplay: enable dpm under pass-through
  drm/amdgpu: access register without KIQ
  drm/amdgpu: set correct base for THM/NBIF/MP1 IP
  drm/amd/display: fix dentist did ranges
  drm/amd/display: make dp_ss_off optional
  drm/amd/display: fix dp_ss_control vbios flag parsing
  drm/amd/display: Do not retain link settings
  MAINTAINERS: drm-misc: Change seanpaul's email address
  drm/panel: simple: tv123wam: Add unprepare delay
2018-08-24 09:22:54 -07:00
Michal Hocko
93065ac753 mm, oom: distinguish blockable mode for mmu notifiers
There are several blockable mmu notifiers which might sleep in
mmu_notifier_invalidate_range_start and that is a problem for the
oom_reaper because it needs to guarantee a forward progress so it cannot
depend on any sleepable locks.

Currently we simply back off and mark an oom victim with blockable mmu
notifiers as done after a short sleep.  That can result in selecting a new
oom victim prematurely because the previous one still hasn't torn its
memory down yet.

We can do much better though.  Even if mmu notifiers use sleepable locks
there is no reason to automatically assume those locks are held.  Moreover
majority of notifiers only care about a portion of the address space and
there is absolutely zero reason to fail when we are unmapping an unrelated
range.  Many notifiers do really block and wait for HW which is harder to
handle and we have to bail out though.

This patch handles the low hanging fruit.
__mmu_notifier_invalidate_range_start gets a blockable flag and callbacks
are not allowed to sleep if the flag is set to false.  This is achieved by
using trylock instead of the sleepable lock for most callbacks and
continue as long as we do not block down the call chain.

I think we can improve that even further because there is a common pattern
to do a range lookup first and then do something about that.  The first
part can be done without a sleeping lock in most cases AFAICS.

The oom_reaper end then simply retries if there is at least one notifier
which couldn't make any progress in !blockable mode.  A retry loop is
already implemented to wait for the mmap_sem and this is basically the
same thing.

The simplest way for driver developers to test this code path is to wrap
userspace code which uses these notifiers into a memcg and set the hard
limit to hit the oom.  This can be done e.g.  after the test faults in all
the mmu notifier managed memory and set the hard limit to something really
small.  Then we are looking for a proper process tear down.

[akpm@linux-foundation.org: coding style fixes]
[akpm@linux-foundation.org: minor code simplification]
Link: http://lkml.kernel.org/r/20180716115058.5559-1-mhocko@kernel.org
Signed-off-by: Michal Hocko <mhocko@suse.com>
Acked-by: Christian König <christian.koenig@amd.com> # AMD notifiers
Acked-by: Leon Romanovsky <leonro@mellanox.com> # mlx and umem_odp
Reported-by: David Rientjes <rientjes@google.com>
Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Doug Ledford <dledford@redhat.com>
Cc: Jason Gunthorpe <jgg@ziepe.ca>
Cc: Mike Marciniszyn <mike.marciniszyn@intel.com>
Cc: Dennis Dalessandro <dennis.dalessandro@intel.com>
Cc: Sudeep Dutt <sudeep.dutt@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Dimitri Sivanich <sivanich@sgi.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: "Jérôme Glisse" <jglisse@redhat.com>
Cc: Andrea Arcangeli <aarcange@redhat.com>
Cc: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2018-08-22 10:52:44 -07:00
Leo (Sunpeng) Li
9d1d02ff36 drm/amd/display: Don't build DCN1 when kcov is enabled
DCN1 contains code that utilizes fp math. When
CONFIG_KCOV_INSTRUMENT_ALL and CONFIG_KCOV_ENABLE_COMPARISONS are
enabled, build errors are found. See this earlier patch for details:

https://lists.freedesktop.org/archives/dri-devel/2018-August/186131.html

As a short term solution, disable CONFIG_DRM_AMD_DC_DCN1_0 when
KCOV_INSTRUMENT_ALL and KCOV_ENABLE_COMPARISONS are enabled. In
addition, make it a fully derived config, taking into account
CONFIG_X86.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-21 14:33:59 -05:00
Leo (Sunpeng) Li
dc37a9a08d Revert "drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86"
This reverts commit 8624c3c4dbfe24fc6740687236a2e196f5f4bfb0.

We need CONFIG_DRM_AMD_DC_DCN1_0 to guard code that is using fp math.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-21 14:32:28 -05:00
Alex Deucher
95f05a3a2e drm/amdgpu/display: disable eDP fast boot optimization on DCE8
Seems to cause blank screens.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106940
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-21 14:23:17 -05:00
Christian König
e6f8d26ebb drm/amdgpu: fix amdgpu_amdkfd_remove_eviction_fence v3
Fix quite a number of bugs here. Unfortunately only compile tested.

v2: fix copy&paste error
v3: fix 80 chars issue in comment

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-21 14:19:26 -05:00
Christian König
c4aed87630 drm/amdgpu: fix incorrect use of drm_file->pid
That's the PID of the creator of the file (usually the X server) and not
the end user of the file.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
CC: stable@vger.kernel.org
2018-08-21 14:19:18 -05:00
Christian König
bce31d4c1a drm/amdgpu: fix incorrect use of fcheck
The usage isn't RCU protected.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
CC: stable@vger.kernel.org
2018-08-21 14:19:10 -05:00
Yintian Tao
11a88c2e92 drm/powerplay: enable dpm under pass-through
Repeat enable dpm under pass-through because there is no actually
hardware-fini and real power-off when guest vm shutdown or reboot.
Otherwise, under pass-through it will be failed to populate populate
and upload SCLK MCLK DPM levels due to zero of pcie_speed_table.count.

Signed-off-by: Yintian Tao <yttao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-21 14:18:21 -05:00
Yintian Tao
fa1d04e9a8 drm/amdgpu: access register without KIQ
there is no need to access register such as mmSMC_IND_INDEX_11
and mmSMC_IND_DATA_11 through KIQ because they are VF-copy.

Signed-off-by: Yintian Tao <yttao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-21 14:17:36 -05:00
Evan Quan
bde0781561 drm/amdgpu: set correct base for THM/NBIF/MP1 IP
Set correct address base for vega20.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-21 14:16:50 -05:00
Dmytro Laktyushkin
39a3cd6783 drm/amd/display: fix dentist did ranges
Dentist did ranges were incomplete as max setting has an unusual
divider step up of 66.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-21 14:16:43 -05:00
Dmytro Laktyushkin
66b198ffc9 drm/amd/display: make dp_ss_off optional
dp_ss_off flag doesn't need to be set, so we create a link_init
function if it is needed by an asic

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-21 14:16:35 -05:00
Dmytro Laktyushkin
16747b2109 drm/amd/display: fix dp_ss_control vbios flag parsing
dp_ss_control = 0 means ss is off, we had a typo where
we would double not dp_ss_control while setting dp_ss_off
flag

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-21 14:16:28 -05:00
Samson Tam
8f7040b8f2 drm/amd/display: Do not retain link settings
Do not retrain link settings if lane count and link rate are both
unknown.  Causes driver to be stuck reading VBIOS register after
removing emulated connection.

Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-21 14:16:20 -05:00
Michel Dänzer
c9533d1bca drm/amdgpu: Use kvmalloc for allocating UVD/VCE/VCN BO backup memory
The allocated size can be (at least?) as large as megabytes, and
there's no need for it to be physically contiguous.

May avoid spurious failures to initialize / suspend the corresponding
block while there's memory pressure.

Bugzilla: https://bugs.freedesktop.org/107432
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-16 12:59:11 -05:00
Nicholas Kazlauskas
dddc0557e3 drm/amd/display: Guard against null crtc in CRC IRQ
[Why]

A null pointer deference can occur if crtc is null in
amdgpu_dm_crtc_handle_crc_irq. This can happen if get_crtc_by_otg_inst
returns NULL during dm_crtc_high_irq, leading to a hang in some IGT
test cases.

[How]

Check that CRTC is non-null before accessing its fields.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-13 17:29:44 -05:00
Mikita Lipski
433149130c drm/amd/display: Pass connector id when executing VBIOS CT
[why]
Older ASICs require both phys_id and connector_id
to execute bios command table. If we are not passing the
right connector_id - it can lead to a black screen.

[how]
Set connector_obj_id when executing vbios command table

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-08-13 17:29:37 -05:00
Mikita Lipski
ad8960a6cb drm/amd/display: Check if clock source in use before disabling
[why]
We are disabling clock source while other pipes are still using
it, because we don't verify the number of pipes that share it.

[how]
- Adding a function in resources to return the number of pipes
sharing the clock source.
- Checking that no one is sharing the clock source before disabling

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-08-13 17:29:11 -05:00
Mikita Lipski
fc69009e35 drm/amd/display: Allow clock sharing b/w HDMI and DVI
[why]
HDMI and DVI share the same PHY clock and single link
DVI and HDMI both use 4 lanes, so they should be allowed
to be sharing the same clock source if all other parameters
are satisfied.

[how]
Change a check for general DVI to Dual DVI.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-13 17:24:21 -05:00
Jerry (Fangzhi) Zuo
7cb5285507 drm/amd/display: Fix warning observed in mode change on Vega
[Why]
DOUBLE_BUFFER_EN bit is getting cleared before enable blanking.
That leads to CRTC_BLANK_DATA_EN is getting updated immediately.

[How]
Get DOUBLE_BUFFER_EN bit set, the same as DCE110.

Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-13 17:22:08 -05:00
Charlene Liu
321f65a623 drm/amd/display: fix single link DVI has no display
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-13 17:21:49 -05:00
Emily Deng
20acbed47d drm/amdgpu/vce: VCE entity initialization relies on ring initializtion
Entity init should after ring init, as the entity's sched_rq's initialization
is in ring init.

SWDEV-161495

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-13 17:21:29 -05:00
Emily Deng
33d5bd0705 drm/amdgpu/uvd: UVD entity initialization relys on ring initialization
Entity init should after ring init, as the entity's sched_rq's initialization
is in ring init.

SWDEV-161495

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-13 17:20:10 -05:00
Likun Gao
4d77c0f676 drm/amdgpu:add VCN booting with firmware loaded by PSP
Setup psp firmware loading for VCN, and make VCN block
booting from tmr mac address.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-08-13 17:19:46 -05:00
Likun Gao
235ac9de62 drm/amdgpu:add VCN support in PSP driver
Add VCN support in PSP driver

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-08-13 17:19:27 -05:00
Likun Gao
c9ca989696 drm/amdgpu:add new firmware id for VCN
Add the new firmware id for VCN into the enum

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-08-13 17:19:10 -05:00
James Zhu
435198f33b drm/amdgpu: update tmr mc address
Update tmr mc address with firmware loading address
which is returned from PSP firmware

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-08-13 17:18:54 -05:00
James Zhu
abf412b3ef drm/amdgpu:add tmr mc address into amdgpu_firmware_info
amdgpu IP blocks booting need Trust Memory Region(tmr) mc address
of its firmware which is loaded by PSP

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Likun Gao <likun.gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-08-13 17:18:39 -05:00
Dave Airlie
557ce95051 Merge branch 'drm-next-4.19' of git://people.freedesktop.org/~agd5f/linux into drm-next
More fixes for 4.19:
- Fixes for scheduler
- Fix for SR-IOV
- Fixes for display

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180809200052.2777-1-alexander.deucher@amd.com
2018-08-10 11:43:02 +10:00
Emily Deng
b045d3af7d drm/amdgpu/sriov: give 8s for recover vram under RUNTIME
Extend the timeout for recovering vram bos from shadows on sr-iov
to cover the worst case scenario for timeslices and VFs

Under runtime, the wait fence time could be quite long when
other VFs are in exclusive mode. For example, for 4 VF, every
VF's exclusive timeout time is set to 3s, then the worst case is
9s. If the VF number is more than 4,then the worst case time will
be longer.
The 8s is the test data, with setting to 8s, it will pass the TDR
test for 1000 times.

SWDEV-161490

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-09 11:59:17 -05:00
Dave Airlie
940fbcb73f Merge branch 'drm-next-4.19' of git://people.freedesktop.org/~agd5f/linux into drm-next
Fixes for 4.19:
- Fix UVD 7.2 instance handling
- Fix UVD 7.2 harvesting
- GPU scheduler fix for when a process is killed
- TTM cleanups
- amdgpu CS bo_list fixes
- Powerplay fixes for polaris12 and CZ/ST
- DC fixes for link training certain HMDs
- DC fix for vega10 blank screen in certain cases

From: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180801222906.1016-1-alexander.deucher@amd.com
2018-08-08 06:22:23 +10:00
Hersen Wu
1e1dbd6fd1 drm/amd/display: display connected to dp-1 does not light up
[why]
for vega, dp set_panel_mode is
handled by psp firmware. dal should not program the
register again.

[how]
dal does not program panel mode.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-06 15:57:51 -05:00
Mikita Lipski
81aca8e75c drm/amd/display: update clk for various HDMI color depths
[why]
When programming tonga's connector's backend we didn't take
in account that HDMI's colour depth might be more than 8bpc
therefore we need to add a switch statement that would adjust
the pixel clock accordingly.

[how]
Add a switch statement updating clock by its appropriate
coefficient.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-08-06 15:57:29 -05:00
Dmytro Laktyushkin
99326ee362 drm/amd/display: program display clock on cache match
[Why]
We seem to have an issue where high enough display clock
will not get set properly during S3 resume if we only
call vbios once

[How]
Expand condition of display clock programming to happen
even when cached display clock matches requested display
clock

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-06 15:57:12 -05:00
Nicholas Kazlauskas
fb7b11e163 drm/amd/display: Add NULL check for enabling dp ss
[Why]

The pointer for integrated_info can be NULL which causes the system to
do a null pointer deference and hang on boot.

[How]

Add a check to ensure that integrated_info is not null before enabling
DP ss.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-06 15:57:02 -05:00
Dmytro Laktyushkin
ad830e7ab1 drm/amd/display: add vbios table check for enabling dp ss
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-06 15:56:54 -05:00
Mikita Lipski
3e27e10e2e drm/amd/display: Don't share clk source between DP and HDMI
[why]
Prevent clock source sharing between HDMI and DP connectors.
DP shouldn't be sharing its ref clock with phy clock,
which caused an issue of older ASICS booting up with multiple
diplays plugged in.

[how]
Add an extra check that would prevent HDMI and DP sharing clk.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-08-06 14:35:43 -05:00
Hersen Wu
9315e2399a drm/amd/display: Fix DP HBR2 Eye Diagram Pattern on Carrizo
[why] dp hbr2 eye diagram pattern for raven asic is not stabled.
workaround is to use tp4 pattern. But this should not be
applied to asic before raven.

[how] add new bool varilable in asic caps. for raven asic,
use the workaround. for carrizo, vega, do not use workaround.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-06 14:35:25 -05:00
Nicholas Kazlauskas
5ae6fe5729 drm/amd/display: Use calculated disp_clk_khz value for dce110
[Why]

The calculated values for actual disp_clk_khz were ignored when
notifying pplib of the new display requirements. In order to honor DFS
bypass clocks from the hardware, the calculated value should be used.

[How]

The return value for set_dispclk is now assigned back into new_clocks
and correctly carried through into dccg->clks.phyclk_khz. When notifying
pplib of new display requirements dccg->clks.phyclk_khz is used
instead of dce.dispclk_khz. The value of dce.dispclk_khz was never
explicitly set to anything before.

A 15% higher display clock value than calculated is no longer requested
for dce110 since it now makes use of the calculated value.

Since dce112 makes use of dce110's set_bandwidth but not its
update_clocks it needs to have the value correctly carried through.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-06 14:35:25 -05:00
David Francis
78e4405cec drm/amd/display: Implement custom degamma lut on dcn
[Why]
Custom degamma lut functions are a feature we would
like to support on compatible hardware

[How]
In atomic check, convert from array of drm_color_lut to
dc_transfer_func.  On hardware commit, allow for possibility
of custom degamma.  Both are based on the equivalent
regamma pipeline.

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-06 14:35:25 -05:00
David Francis
d90e9a3bf5 drm/amd/display: Destroy aux_engines only once
[Why]
In the dce112 function to destroy the resource pool, engines
(the aux engines) is destroyed twice.  This has no ill effects
but is a tad redundant.

[How]
Remove the redundant call

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-06 14:35:24 -05:00
David Francis
53a53f8687 drm/amd/display: Read back max backlight value at boot
[Why]
If there is no program explicitly setting the backlight
brightness (for example, during a minimal install of linux), the
hardware defaults to maximum brightness but the backlight_device
defaults to 0 value.  Thus, settings displays the wrong brightness
value.

[How]
When creating the backlight device, set brightness to max

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-06 14:35:24 -05:00
David Francis
620a0d27b2 drm/amd/display: Implement backlight_ops.get_brightness
[Why]
This hook that is supposed to read the actual backlight value
is used in a few places throughout the kernel to setup or force
update on backlight

[How]
Create a dc function that calls the existing abm function, and
call that function from amdgpu

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-06 14:35:24 -05:00
abdoulaye berthe
0301ccbaf6 drm/amd/display: DP Compliance 400.1.1 failure
[Why]
400.1.1 is failing because we are not performing link training when
we get an HPD pulse for the same display. This is breaking DP
compliance

[How]
Always perform link training after HPD pulse if the detection
reason is not  DETECT_REASON_HPDRX.

Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-06 14:35:23 -05:00
Leo (Sunpeng) Li
e11d41472a drm/amd/display: Use requested HDMI aspect ratio
[Why]
The DRM mode's HDMI picture aspect ratio field was never saved in
dc_stream's timing struct. This causes us to mistake a new stream to
have the same timings as the old, even though the user has requested a
different aspect ratio.

[How]
Save DRM's aspect ratio field within dc_stream's timing struct.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=107153
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-08-06 14:33:31 -05:00
Harry Wentland
1619677618 drm/amd/display: Only require EDID read for HDMI and DVI
[Why]
VGA sometimes has trouble retrieving the EDID on very long cables, KVM
switches, or old displays.

[How]
Only require EDID read for HDMI and DVI and exempt other types (DP,
VGA). We currently don't support VGA but if anyone adds support in the
future this might get overlooked.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Suggested-by: Michel Dänzer <michel@daenzer.net>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-03 10:14:10 -05:00
Harry Wentland
01dc285d5c drm/amd/display: Report non-DP display as disconnected without EDID
[Why]
Some boards seem to have a problem where HPD is high on HDMI even though
no display is connected. We don't want to report these as connected. DP
spec still requires us to report DP displays as connected when HPD is
high but we can't read the EDID in order to go to fail-safe mode.

[How]
If connector_signal is not DP abort detection if we can't retrieve the
EDID.

v2: Add Bugzilla and stable

Bugzilla: https://bugs.freedesktop.org/107390
Bugzilla: https://bugs.freedesktop.org/106846
Cc: stable@vger.kernel.org
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-03 10:14:09 -05:00
Gustavo A. R. Silva
ddf74e79a5 drm/amdgpu/pm: Fix potential Spectre v1
idx can be indirectly controlled by user-space, hence leading to a
potential exploitation of the Spectre variant 1 vulnerability.

This issue was detected with the help of Smatch:

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:408 amdgpu_set_pp_force_state()
warn: potential spectre issue 'data.states'

Fix this by sanitizing idx before using it to index data.states

Notice that given that speculation windows are large, the policy is
to kill the speculation on the first load and not worry if it can be
completed with a dependent load/store [1].

[1] https://marc.info/?l=linux-kernel&m=152449131114778&w=2

Cc: stable@vger.kernel.org
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:23 -05:00
Colin Ian King
7ac7aebe85 drm/amd/display: add missing void parameter to dc_create_transfer_func
Add a missing void parameter to function dc_create_transfer_func, fixes
sparse warning:

warning: non-ANSI function declaration of function 'dc_create_transfer_func'

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:22 -05:00
Thomas Zimmermann
fea872b279 drm/amdgpu: Replace ttm_bo_unref with ttm_bo_put
The function ttm_bo_put releases a reference to a TTM buffer object. The
function's name is more aligned to the Linux kernel convention of naming
ref-counting function _get and _put.

A call to ttm_bo_unref takes the address of the TTM BO object's pointer and
clears the pointer's value to NULL. This is not necessary in most cases and
sometimes even worked around by the calling code. A call to ttm_bo_put only
releases the reference without clearing the pointer.

The current behaviour of cleaning the pointer is kept in the calling code,
but should be removed if not required in a later patch.

v2:
 * set prefix to drm/amdgpu

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:21 -05:00
Thomas Zimmermann
71d5ef1127 drm/amdgpu: Replace ttm_bo_reference with ttm_bo_get
The function ttm_bo_get acquires a reference on a TTM buffer object. The
function's name is more aligned to the Linux kernel convention of naming
ref-counting function _get and _put.

v2:
 * changed prefix to drm/amdgpu

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:21 -05:00
Christian König
4a102ad4ba drm/amdgpu: create an empty bo_list if no handle is provided
Instead of having extra handling just create an empty bo_list when no
handle is provided.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:19 -05:00
Christian König
920990cb08 drm/amdgpu: allocate the bo_list array after the list
This avoids multiple allocations for the head and the array.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:19 -05:00
Christian König
39f7f69a60 drm/amdgpu: add bo_list iterators
Add helpers to iterate over all entries in a bo_list.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:19 -05:00
Christian König
a0f208453b drm/amdgpu: nuke amdgpu_bo_list_free
The RCU grace period is harmless and avoiding it is not worth the effort
of doubling the implementation.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:18 -05:00
Christian König
81c6dabcc9 drm/amdgpu: always recreate bo_list
The bo_list handle is allocated by OP_CREATE, so in OP_UPDATE here we just
re-create the bo_list object and replace the handle. This way we don't
need locking to protect the bo_list because it's always re-created when
changed.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:18 -05:00
Christian König
4a8c21a1e9 drm/amdgpu: move bo_list defines to amdgpu_bo_list.h
Further demangle amdgpu.h

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:18 -05:00
Christian König
8ab19ea619 drm/amdgpu: add new amdgpu_vm_bo_trace_cs() function v2
This allows us to trace all VM ranges which should be valid inside a CS.

v2: dump mappings without BO as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Reviewed-and-tested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> (v1)
Reviewed-by: Huang Rui <ray.huang@amd.com> (v1)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:17 -05:00
Christian König
0cb7c1f03b drm/amdgpu: return error if both BOs and bo_list handle is given
Return -EINVAL when both the BOs as well as a list handle is provided in
the IOCTL.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:17 -05:00
Christian König
275105ce7b drm/amdgpu: fix total size calculation
long might only be 32bit in size and we can easily use more than 4GB
here.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming  Zhou <david1.zhou@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:16 -05:00
Christian König
52c054caf8 drm/amdgpu: add proper error handling to amdgpu_bo_list_get
Otherwise we silently don't use a BO list when the handle is invalid.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:16 -05:00
Rex Zhu
ccf9ef0b0d drm/amdgpu: fix a reversed condition
This test was reversed so it would end up leading to vddnb value
can't be read via hwmon on APU.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-07-31 16:58:12 -05:00
Rex Zhu
8a50bb47a8 drm/amd/pp: Convert voltage unit in mV*4 to mV on CZ/ST
the voltage showed in debugfs and hwmon should be in mV

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-07-31 16:58:06 -05:00
Rex Zhu
90983631a6 drm/amd/pp: Delete unused temp variables
Only delete the dead temp variables in Polaris.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-31 16:58:06 -05:00
Rex Zhu
2d227ec2c1 drm/amd/pp/Polaris12: Fix a chunk of registers missed to program
DIDTConfig_Polaris12[] table missed a big chunk of data.

Pointed by aidan.fabius <aidan.fabius@coreavi.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-07-31 16:58:02 -05:00
Dave Airlie
3fce461827 BackMerge v4.18-rc7 into drm-next
rmk requested this for armada and I think we've had a few
conflicts build up.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-07-30 10:39:22 +10:00
Huang Rui
2e603d0429 drm/amdgpu: clean up the superfluous space and align the comment text for amdgpu_ttm
This patch cleans up spaces and align the text to refine the comment for
amdgpu_ttm.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 15:00:38 -05:00
Junwei Zhang
204029e197 drm/amdgpu: correct evict flag for bo move
pass the evict flag instead of hard code

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 15:00:29 -05:00
Alex Deucher
f1e582ebfd drm/amdgpu: implement harvesting support for UVD 7.2 (v3)
Properly handle cases where one or more instance of the IP
block may be harvested.

v2: make sure ip_num_rings is initialized amdgpu_queue_mgr.c
v3: rebase on Christian's UVD changes, drop unused var

Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:44 -05:00
Harry Wentland
d04cc604a6 drm/amd: Add missing fields in atom_integrated_system_info_v1_11
This structure needs to align with structure in atomfirmware table.
Update it.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:43 -05:00
Harry Wentland
116f451c90 drm/amd/display: DC 3.1.59
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:43 -05:00
Anthony Koo
9907704174 drm/amd/display: Prevent PSR from being enabled if initialization fails
[Why]
PSR_SET command is sent to the microcontroller in order to initialize
parameters needed for PSR feature, such as telling the microcontroller
which pipe is driving the PSR supported panel. When this command is
skipped or fails, the microcontroller may program the wrong thing if
driver tries to enable PSR.

[How]
If PSR_SET fails, do not set psr_enable flag to indicate the feature is
not yet initialized.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:43 -05:00
Jerry (Fangzhi) Zuo
f358b39d18 drm/amd/display: Fix Vega10 black screen after mode change
[Why]
The sequence is slightly changed when bring .set_bandwidth out
from the end of programming backend to the end of programming
surface. Vega10 doesn't like to get clocks updated if
stream_count is zero in the current context (Atomic Reset).

[How]
Do not update clocks if no stream is showing up in the context.

Fixes 1b2b130192 "dc: Remove 300Mhz minimum disp clk limit."

Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:42 -05:00
Bhawanpreet Lakha
65c78961b3 drm/amd/display: flatten aux_engine and engine
[Why]
engine and aux_engine are unnecessary layers we want to remove this
layer.

[How]
flatten engine and aux engine structs into one struct called
aux_engine and remove all references to the engine struct.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:42 -05:00
Bhawanpreet Lakha
824474ba38 drm/amd/display: Retry link training again
[Why]
Some receivers seem to fail the first link training but are good on
subsequent tries. We want to retry link training again. This fixes
HTC vive pro not lighting up after being disabled.

[How]
Check if the link training passed without fall back if this is not
the case then we retry link training.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:42 -05:00
Christian König
66c28d6df2 drm/amdgpu: patch the IBs for the second UVD instance v2
Patch the IBs for the second UVD instance so that userspace don't need
to care about the instance they submit to.

v2: use direct IB patching

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-and-tested-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:41 -05:00
Christian König
9d248517d4 drm/amdgpu: add support for inplace IB patching for MM engines v2
We are going to need that for the second UVD instance on Vega20.

v2: rename to patch_cs_in_place

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-and-tested-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-27 09:07:41 -05:00
Jia-Ju Bai
586092ab4b gpu: drm: amdgpu: Replace mdelay with msleep in cik_pcie_gen3_enable()
cik_pcie_gen3_enable() is only called by cik_common_hw_init(), which is
never called in atomic context.
cik_pcie_gen3_enable() calls mdelay() to busily wait, which is not
necessary.
mdelay() can be replaced with msleep().

This is found by a static analysis tool named DCNS written by myself.

Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:06:40 -05:00
Alex Deucher
6cdf4e87b4 drm/amdgpu/gmc9: clarify GPUVM fault error message
The address printed is the actual address, not the page.

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:06:40 -05:00
Nayan Deshmukh
068c330419 drm/scheduler: remove sched field from the entity
The scheduler of the entity is decided by the run queue on which
it is queued. This patch avoids us the effort required to maintain
a sync between rq and sched field when we start shifting entites
among different rqs.

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:06:26 -05:00
Nayan Deshmukh
cdc5017659 drm/scheduler: modify API to avoid redundancy
entity has a scheduler field and we don't need the sched argument
in any of the functions where entity is provided.

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:06:19 -05:00
Christian König
bf314ca3f1 drm/amdgpu: reduce the number of placements for a BO
Make struct amdgpu_bo a bit smaller.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:06:13 -05:00
Christian König
c704ab18e0 drm/amdgpu: consistenly name amdgpu_bo_ functions
Just rename functions, no functional change.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:06:06 -05:00
Christian König
4d4831a3da drm/amdgpu: expose only the first UVD instance for now
Going to completely rework the context to ring mapping with Nayan's GSoC
work, but for now just stopping to expose the second UVD instance should
do it.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:05:32 -05:00
Christian König
f8a91d4555 drm/amdgpu: clean up coding style a bit
No need to bitcast a boolean and even if we should use "!!" instead.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-25 15:05:08 -05:00
Harry Wentland
bb805f2b20 drm/amd/display: DC 3.1.58
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:16:07 -05:00
Jun Lei
cfd84fd365 drm/amd/display: separate dc_debug into dc_debug_options and dc_debug data
[why]
confusing as to which part of debug is informational, and which part causes behavioral change

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:15:59 -05:00
Bhawanpreet Lakha
5c6ac7112f drm/amd/display: Decouple aux from i2c
[Why]
Aux engine is created from i2caux layer. We want to remove this layer
and use the engine directly.

[How]
Decouple aux engine from i2caux. Move aux engine related code to dce folder and use
dc resource pool to manage the engine. And use the engine functions directly

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:15:50 -05:00
vikrant mhaske
3fc9fc4cf5 drm/amd/display: DPP CM ICSC AYCRCB8888 format support
[why]
Diags has POR to run the video workload using AYCRCB8888 through DCN;
capture it through DWB and send it to VCN hardware to encode

[how]
added the code to support this format so that DPP ICSC will be able to
convert it from YUV444 to internal RGB and DWB OCSC will be able to
convert from internal RGB to YUV420

Signed-off-by: vikrant mhaske <vikrant.mhaske@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:15:41 -05:00
David Francis
278ca8d677 drm/amd/display: On dce100, set clocks to 0 on suspend
[Why]
When a dce100 asic was suspended, the clocks were not set to 0.
Upon resume, the new clock was compared to the existing clock,
they were found to be the same, and so the clock was not set.
This resulted in a pernicious blackscreen.

[How]
In atomic commit, check to see if there are any active pipes.
If no, set clocks to 0

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:15:30 -05:00
Tony Cheng
aafded8885 drm/amd/display: allow diags to skip initial link training
[why]
diag specify what the full config and is only concerned about pass/fail at the end

having inter-op code like verifiying we can actually train at reported link rate
slows down diag test and add complexity we don't need

[how]
add dc_debug option to skip capability link trianing

also  remove hbr in function name as verify is not specific to hbr

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Ken Chalmers <ken.chalmers@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:15:14 -05:00
Mikita Lipski
85344e75d0 drm/amd/display: Remove unnecessary warning
[why]
The warning message floods the dmesg log on Tonga even
though it is expected to have a pix_clk set to zero,
when the pipe is not active.
[how]
remove the assert

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:15:02 -05:00
Shirish S
5f8181733f drm/amdgpu: move the amdgpu_fbdev_set_suspend() further up
This patch moves amdgpu_fbdev_set_suspend() to the beginning
of suspend sequence.

This is to ensure fbcon does not to write to the VRAM
after GPU is powerd down.

Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:14:54 -05:00
Michel Dänzer
456607d816 drm/amdgpu: Don't warn on destroying a pinned BO
The warning turned out to be not so useful, as BO destruction tends to
be deferred to a workqueue.

Also, we should be preventing any damage from this now, so not really
important anymore to fix code doing this.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:14:45 -05:00
Evan Quan
92859e0d5c drm/amd/powerplay: allow slow switch only if NBPState enabled v2
Otherwise there may be potential SMU performance issues.

v2: fix commit description and coding style

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <rex.zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:14:35 -05:00