drm/amd/display: pass compat_level to hubp

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu 2018-07-16 14:05:11 -04:00 committed by Alex Deucher
parent f688b614b6
commit a465feae60
4 changed files with 9 additions and 4 deletions

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@ -485,7 +485,8 @@ void hubp1_program_surface_config(
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror)
bool horizontal_mirror,
unsigned int compat_level)
{
hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
hubp1_program_tiling(hubp, tiling_info, format);

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@ -664,7 +664,8 @@ void hubp1_program_surface_config(
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror);
bool horizontal_mirror,
unsigned int compat_level);
void hubp1_program_deadline(
struct hubp *hubp,

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@ -2004,6 +2004,7 @@ static void update_dchubp_dpp(
struct dpp *dpp = pipe_ctx->plane_res.dpp;
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
union plane_size size = plane_state->plane_size;
unsigned int compat_level = 0;
/* depends on DML calculation, DPP clock value may change dynamically */
/* If request max dpp clk is lower than current dispclk, no need to
@ -2095,7 +2096,8 @@ static void update_dchubp_dpp(
&size,
plane_state->rotation,
&plane_state->dcc,
plane_state->horizontal_mirror);
plane_state->horizontal_mirror,
compat_level);
}
hubp->power_gated = false;

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@ -96,7 +96,8 @@ struct hubp_funcs {
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror);
bool horizontal_mirror,
unsigned int compa_level);
bool (*hubp_is_flip_pending)(struct hubp *hubp);