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drm/amd/display: pass compat_level to hubp
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -485,7 +485,8 @@ void hubp1_program_surface_config(
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union plane_size *plane_size,
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enum dc_rotation_angle rotation,
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struct dc_plane_dcc_param *dcc,
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bool horizontal_mirror)
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bool horizontal_mirror,
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unsigned int compat_level)
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{
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hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
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hubp1_program_tiling(hubp, tiling_info, format);
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@ -664,7 +664,8 @@ void hubp1_program_surface_config(
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union plane_size *plane_size,
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enum dc_rotation_angle rotation,
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struct dc_plane_dcc_param *dcc,
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bool horizontal_mirror);
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bool horizontal_mirror,
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unsigned int compat_level);
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void hubp1_program_deadline(
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struct hubp *hubp,
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@ -2004,6 +2004,7 @@ static void update_dchubp_dpp(
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struct dpp *dpp = pipe_ctx->plane_res.dpp;
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struct dc_plane_state *plane_state = pipe_ctx->plane_state;
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union plane_size size = plane_state->plane_size;
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unsigned int compat_level = 0;
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/* depends on DML calculation, DPP clock value may change dynamically */
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/* If request max dpp clk is lower than current dispclk, no need to
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@ -2095,7 +2096,8 @@ static void update_dchubp_dpp(
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&size,
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plane_state->rotation,
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&plane_state->dcc,
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plane_state->horizontal_mirror);
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plane_state->horizontal_mirror,
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compat_level);
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}
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hubp->power_gated = false;
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@ -96,7 +96,8 @@ struct hubp_funcs {
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union plane_size *plane_size,
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enum dc_rotation_angle rotation,
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struct dc_plane_dcc_param *dcc,
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bool horizontal_mirror);
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bool horizontal_mirror,
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unsigned int compa_level);
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bool (*hubp_is_flip_pending)(struct hubp *hubp);
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