mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/amd/powerplay: add the smu manager for vega20 (v2)
The SMU manager handles the driver interaction with the SMU
which handles clock and voltage controls.
v2: switch to SOC15 register access macros
reserve space for ActivityMonitor table
enable SMU fw loading
Drop dead code from bringup
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan
Alex Deucher
parent
b9443b572c
commit
f4eac80add
@ -26,7 +26,7 @@
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SMU_MGR = smumgr.o smu8_smumgr.o tonga_smumgr.o fiji_smumgr.o \
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polaris10_smumgr.o iceland_smumgr.o \
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smu7_smumgr.o vega10_smumgr.o smu10_smumgr.o ci_smumgr.o \
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vega12_smumgr.o vegam_smumgr.o smu9_smumgr.o
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vega12_smumgr.o vegam_smumgr.o smu9_smumgr.o vega20_smumgr.o
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AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
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530
drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
Normal file
530
drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
Normal file
@ -0,0 +1,530 @@
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "smumgr.h"
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#include "vega20_inc.h"
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#include "soc15_common.h"
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#include "vega20_smumgr.h"
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#include "vega20_ppsmc.h"
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#include "smu11_driver_if.h"
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#include "ppatomctrl.h"
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#include "pp_debug.h"
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#include "smu_ucode_xfer_vi.h"
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#include "smu7_smumgr.h"
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#include "vega20_hwmgr.h"
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/* MP Apertures */
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#define MP0_Public 0x03800000
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#define MP0_SRAM 0x03900000
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#define MP1_Public 0x03b00000
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#define MP1_SRAM 0x03c00004
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/* address block */
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#define smnMP1_FIRMWARE_FLAGS 0x3010024
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#define smnMP0_FW_INTF 0x30101c0
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#define smnMP1_PUB_CTRL 0x3010b14
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static bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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uint32_t mp1_fw_flags;
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WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2,
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(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
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mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2);
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if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
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return true;
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return false;
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}
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/*
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* Check if SMC has responded to previous message.
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*
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* @param smumgr the address of the powerplay hardware manager.
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* @return TRUE SMC has responded, FALSE otherwise.
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*/
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static uint32_t vega20_wait_for_response(struct pp_hwmgr *hwmgr)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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uint32_t reg;
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reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
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phm_wait_for_register_unequal(hwmgr, reg,
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0, MP1_C2PMSG_90__CONTENT_MASK);
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return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
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}
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/*
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* Send a message to the SMC, and do not wait for its response.
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* @param smumgr the address of the powerplay hardware manager.
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* @param msg the message to send.
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* @return Always return 0.
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*/
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static int vega20_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
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uint16_t msg)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
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return 0;
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}
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/*
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* Send a message to the SMC, and wait for its response.
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* @param hwmgr the address of the powerplay hardware manager.
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* @param msg the message to send.
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* @return Always return 0.
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*/
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static int vega20_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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int ret = 0;
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vega20_wait_for_response(hwmgr);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
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vega20_send_msg_to_smc_without_waiting(hwmgr, msg);
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ret = vega20_wait_for_response(hwmgr);
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if (ret != PPSMC_Result_OK)
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pr_err("Failed to send message 0x%x, response 0x%x\n", msg, ret);
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return (ret == PPSMC_Result_OK) ? 0 : -EIO;
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}
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/*
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* Send a message to the SMC with parameter
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* @param hwmgr: the address of the powerplay hardware manager.
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* @param msg: the message to send.
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* @param parameter: the parameter to send
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* @return Always return 0.
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*/
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static int vega20_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
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uint16_t msg, uint32_t parameter)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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int ret = 0;
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vega20_wait_for_response(hwmgr);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
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vega20_send_msg_to_smc_without_waiting(hwmgr, msg);
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ret = vega20_wait_for_response(hwmgr);
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if (ret != PPSMC_Result_OK)
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pr_err("Failed to send message 0x%x, response 0x%x\n", msg, ret);
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return (ret == PPSMC_Result_OK) ? 0 : -EIO;
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}
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/*
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* Retrieve an argument from SMC.
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* @param hwmgr the address of the powerplay hardware manager.
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* @param arg pointer to store the argument from SMC.
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* @return Always return 0.
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*/
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int vega20_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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*arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
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return 0;
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}
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/*
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* Copy table from SMC into driver FB
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* @param hwmgr the address of the HW manager
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* @param table_id the driver's table ID to copy from
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*/
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int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id)
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{
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struct vega20_smumgr *priv =
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(struct vega20_smumgr *)(hwmgr->smu_backend);
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int ret = 0;
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PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
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"Invalid SMU Table ID!", return -EINVAL);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
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"Invalid SMU Table version!", return -EINVAL);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
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"Invalid SMU Table Length!", return -EINVAL);
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PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrHigh,
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upper_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
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"[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!",
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return ret);
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PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrLow,
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lower_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
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"[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
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return ret);
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PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_TransferTableSmu2Dram, table_id)) == 0,
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"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
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return ret);
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memcpy(table, priv->smu_tables.entry[table_id].table,
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priv->smu_tables.entry[table_id].size);
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return 0;
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}
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/*
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* Copy table from Driver FB into SMC
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* @param hwmgr the address of the HW manager
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* @param table_id the table to copy from
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*/
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int vega20_copy_table_to_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id)
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{
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struct vega20_smumgr *priv =
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(struct vega20_smumgr *)(hwmgr->smu_backend);
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int ret = 0;
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PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
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"Invalid SMU Table ID!", return -EINVAL);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
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"Invalid SMU Table version!", return -EINVAL);
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PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
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"Invalid SMU Table Length!", return -EINVAL);
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memcpy(priv->smu_tables.entry[table_id].table, table,
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priv->smu_tables.entry[table_id].size);
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PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrHigh,
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upper_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
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"[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
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return ret);
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PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetDriverDramAddrLow,
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lower_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,
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"[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
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return ret);
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PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_TransferTableDram2Smu, table_id)) == 0,
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"[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
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return ret);
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return 0;
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}
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int vega20_enable_smc_features(struct pp_hwmgr *hwmgr,
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bool enable, uint64_t feature_mask)
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{
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uint32_t smu_features_low, smu_features_high;
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int ret = 0;
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smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
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smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
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if (enable) {
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PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_EnableSmuFeaturesLow, smu_features_low)) == 0,
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"[EnableDisableSMCFeatures] Attemp to enable SMU features Low failed!",
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return ret);
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PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_EnableSmuFeaturesHigh, smu_features_high)) == 0,
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"[EnableDisableSMCFeatures] Attemp to enable SMU features High failed!",
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return ret);
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} else {
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PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_DisableSmuFeaturesLow, smu_features_low)) == 0,
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"[EnableDisableSMCFeatures] Attemp to disable SMU features Low failed!",
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return ret);
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PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_DisableSmuFeaturesHigh, smu_features_high)) == 0,
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"[EnableDisableSMCFeatures] Attemp to disable SMU features High failed!",
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return ret);
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}
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return 0;
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}
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int vega20_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
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uint64_t *features_enabled)
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{
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uint32_t smc_features_low, smc_features_high;
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int ret = 0;
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if (features_enabled == NULL)
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return -EINVAL;
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PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc(hwmgr,
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PPSMC_MSG_GetEnabledSmuFeaturesLow)) == 0,
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"[GetEnabledSMCFeatures] Attemp to get SMU features Low failed!",
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return ret);
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PP_ASSERT_WITH_CODE((ret = vega20_read_arg_from_smc(hwmgr,
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&smc_features_low)) == 0,
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"[GetEnabledSMCFeatures] Attemp to read SMU features Low argument failed!",
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return ret);
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PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc(hwmgr,
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PPSMC_MSG_GetEnabledSmuFeaturesHigh)) == 0,
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"[GetEnabledSMCFeatures] Attemp to get SMU features High failed!",
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return ret);
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PP_ASSERT_WITH_CODE((ret = vega20_read_arg_from_smc(hwmgr,
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&smc_features_high)) == 0,
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"[GetEnabledSMCFeatures] Attemp to read SMU features High argument failed!",
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return ret);
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*features_enabled = ((((uint64_t)smc_features_low << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
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(((uint64_t)smc_features_high << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
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return 0;
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}
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static int vega20_set_tools_address(struct pp_hwmgr *hwmgr)
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{
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struct vega20_smumgr *priv =
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(struct vega20_smumgr *)(hwmgr->smu_backend);
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int ret = 0;
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if (priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr) {
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ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetToolsDramAddrHigh,
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upper_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr));
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if (!ret)
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ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetToolsDramAddrLow,
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lower_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr));
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}
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return ret;
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}
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static int vega20_smu_init(struct pp_hwmgr *hwmgr)
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{
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struct vega20_smumgr *priv;
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unsigned long tools_size = 0x19000;
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int ret = 0;
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struct cgs_firmware_info info = {0};
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ret = cgs_get_firmware_info(hwmgr->device,
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smu7_convert_fw_type_to_cgs(UCODE_ID_SMU),
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&info);
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if (ret || !info.kptr)
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return -EINVAL;
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priv = kzalloc(sizeof(struct vega20_smumgr), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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hwmgr->smu_backend = priv;
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/* allocate space for pptable */
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ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
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sizeof(PPTable_t),
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PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&priv->smu_tables.entry[TABLE_PPTABLE].handle,
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&priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,
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&priv->smu_tables.entry[TABLE_PPTABLE].table);
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if (ret)
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goto free_backend;
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priv->smu_tables.entry[TABLE_PPTABLE].version = 0x01;
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priv->smu_tables.entry[TABLE_PPTABLE].size = sizeof(PPTable_t);
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/* allocate space for watermarks table */
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ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
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sizeof(Watermarks_t),
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PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&priv->smu_tables.entry[TABLE_WATERMARKS].handle,
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&priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,
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&priv->smu_tables.entry[TABLE_WATERMARKS].table);
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if (ret)
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goto err0;
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priv->smu_tables.entry[TABLE_WATERMARKS].version = 0x01;
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priv->smu_tables.entry[TABLE_WATERMARKS].size = sizeof(Watermarks_t);
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/* allocate space for pmstatuslog table */
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ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
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tools_size,
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PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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||||
&priv->smu_tables.entry[TABLE_PMSTATUSLOG].handle,
|
||||
&priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);
|
||||
if (ret)
|
||||
goto err1;
|
||||
|
||||
priv->smu_tables.entry[TABLE_PMSTATUSLOG].version = 0x01;
|
||||
priv->smu_tables.entry[TABLE_PMSTATUSLOG].size = tools_size;
|
||||
|
||||
/* allocate space for OverDrive table */
|
||||
ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
|
||||
sizeof(OverDriveTable_t),
|
||||
PAGE_SIZE,
|
||||
AMDGPU_GEM_DOMAIN_VRAM,
|
||||
&priv->smu_tables.entry[TABLE_OVERDRIVE].handle,
|
||||
&priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_OVERDRIVE].table);
|
||||
if (ret)
|
||||
goto err2;
|
||||
|
||||
priv->smu_tables.entry[TABLE_OVERDRIVE].version = 0x01;
|
||||
priv->smu_tables.entry[TABLE_OVERDRIVE].size = sizeof(OverDriveTable_t);
|
||||
|
||||
/* allocate space for SmuMetrics table */
|
||||
ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
|
||||
sizeof(SmuMetrics_t),
|
||||
PAGE_SIZE,
|
||||
AMDGPU_GEM_DOMAIN_VRAM,
|
||||
&priv->smu_tables.entry[TABLE_SMU_METRICS].handle,
|
||||
&priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_SMU_METRICS].table);
|
||||
if (ret)
|
||||
goto err3;
|
||||
|
||||
priv->smu_tables.entry[TABLE_SMU_METRICS].version = 0x01;
|
||||
priv->smu_tables.entry[TABLE_SMU_METRICS].size = sizeof(SmuMetrics_t);
|
||||
|
||||
/* allocate space for ActivityMonitor table */
|
||||
ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
|
||||
sizeof(DpmActivityMonitorCoeffInt_t),
|
||||
PAGE_SIZE,
|
||||
AMDGPU_GEM_DOMAIN_VRAM,
|
||||
&priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].handle,
|
||||
&priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table);
|
||||
if (ret)
|
||||
goto err4;
|
||||
|
||||
priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].version = 0x01;
|
||||
priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size = sizeof(DpmActivityMonitorCoeffInt_t);
|
||||
|
||||
return 0;
|
||||
|
||||
err4:
|
||||
amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_SMU_METRICS].handle,
|
||||
&priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_SMU_METRICS].table);
|
||||
err3:
|
||||
amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_OVERDRIVE].handle,
|
||||
&priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_OVERDRIVE].table);
|
||||
err2:
|
||||
amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PMSTATUSLOG].handle,
|
||||
&priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);
|
||||
err1:
|
||||
amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_WATERMARKS].handle,
|
||||
&priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_WATERMARKS].table);
|
||||
err0:
|
||||
amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PPTABLE].handle,
|
||||
&priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_PPTABLE].table);
|
||||
free_backend:
|
||||
kfree(hwmgr->smu_backend);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int vega20_smu_fini(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct vega20_smumgr *priv =
|
||||
(struct vega20_smumgr *)(hwmgr->smu_backend);
|
||||
|
||||
if (priv) {
|
||||
amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PPTABLE].handle,
|
||||
&priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_PPTABLE].table);
|
||||
amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_WATERMARKS].handle,
|
||||
&priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_WATERMARKS].table);
|
||||
amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PMSTATUSLOG].handle,
|
||||
&priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);
|
||||
amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_OVERDRIVE].handle,
|
||||
&priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_OVERDRIVE].table);
|
||||
amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_SMU_METRICS].handle,
|
||||
&priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_SMU_METRICS].table);
|
||||
amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].handle,
|
||||
&priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr,
|
||||
&priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table);
|
||||
kfree(hwmgr->smu_backend);
|
||||
hwmgr->smu_backend = NULL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vega20_start_smu(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = vega20_is_smc_ram_running(hwmgr);
|
||||
PP_ASSERT_WITH_CODE(ret,
|
||||
"[Vega20StartSmu] SMC is not running!",
|
||||
return -EINVAL);
|
||||
|
||||
ret = vega20_set_tools_address(hwmgr);
|
||||
PP_ASSERT_WITH_CODE(!ret,
|
||||
"[Vega20StartSmu] Failed to set tools address!",
|
||||
return ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool vega20_is_dpm_running(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
uint64_t features_enabled = 0;
|
||||
|
||||
vega20_get_enabled_smc_features(hwmgr, &features_enabled);
|
||||
|
||||
if (features_enabled & SMC_DPM_FEATURES)
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
|
||||
const struct pp_smumgr_func vega20_smu_funcs = {
|
||||
.smu_init = &vega20_smu_init,
|
||||
.smu_fini = &vega20_smu_fini,
|
||||
.start_smu = &vega20_start_smu,
|
||||
.request_smu_load_specific_fw = NULL,
|
||||
.send_msg_to_smc = &vega20_send_msg_to_smc,
|
||||
.send_msg_to_smc_with_parameter = &vega20_send_msg_to_smc_with_parameter,
|
||||
.download_pptable_settings = NULL,
|
||||
.upload_pptable_settings = NULL,
|
||||
.is_dpm_running = vega20_is_dpm_running,
|
||||
};
|
||||
61
drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h
Normal file
61
drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h
Normal file
@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright 2018 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef _VEGA20_SMUMANAGER_H_
|
||||
#define _VEGA20_SMUMANAGER_H_
|
||||
|
||||
#include "hwmgr.h"
|
||||
#include "smu11_driver_if.h"
|
||||
|
||||
struct smu_table_entry {
|
||||
uint32_t version;
|
||||
uint32_t size;
|
||||
uint64_t mc_addr;
|
||||
void *table;
|
||||
struct amdgpu_bo *handle;
|
||||
};
|
||||
|
||||
struct smu_table_array {
|
||||
struct smu_table_entry entry[TABLE_COUNT];
|
||||
};
|
||||
|
||||
struct vega20_smumgr {
|
||||
struct smu_table_array smu_tables;
|
||||
};
|
||||
|
||||
#define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF
|
||||
#define SMU_FEATURES_LOW_SHIFT 0
|
||||
#define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
|
||||
#define SMU_FEATURES_HIGH_SHIFT 32
|
||||
|
||||
int vega20_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
|
||||
int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
|
||||
uint8_t *table, int16_t table_id);
|
||||
int vega20_copy_table_to_smc(struct pp_hwmgr *hwmgr,
|
||||
uint8_t *table, int16_t table_id);
|
||||
int vega20_enable_smc_features(struct pp_hwmgr *hwmgr,
|
||||
bool enable, uint64_t feature_mask);
|
||||
int vega20_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
|
||||
uint64_t *features_enabled);
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user