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drm/amd/display: Add dprefclk value to dce_dccg

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This allows us to avoid any vbios bugs when initializing clocks

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2018-07-30 14:41:01 -04:00 committed by Alex Deucher
parent 94a4ffd1d4
commit c4621988d4
2 changed files with 4 additions and 1 deletions
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4
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
View File

@ -202,7 +202,7 @@ static int dce12_get_dp_ref_freq_khz(struct dccg *clk)
{
struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
return dccg_adjust_dp_ref_freq_for_ss(clk_dce, 600000);
return dccg_adjust_dp_ref_freq_for_ss(clk_dce, clk_dce->dprefclk_khz);
}
static enum dm_pp_clocks_state dce_get_required_clocks_state(
@ -882,6 +882,7 @@ struct dccg *dce120_dccg_create(struct dc_context *ctx)
dce_dccg_construct(
clk_dce, ctx, NULL, NULL, NULL);
clk_dce->dprefclk_khz = 600000;
clk_dce->base.funcs = &dce120_funcs;
return &clk_dce->base;
@ -909,6 +910,7 @@ struct dccg *dcn1_dccg_create(struct dc_context *ctx)
clk_dce->dprefclk_ss_divider = 1000;
clk_dce->ss_on_dprefclk = false;
clk_dce->dprefclk_khz = 600000;
if (bp->integrated_info)
clk_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
if (clk_dce->dentist_vco_freq_khz == 0) {

1
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
View File

@ -90,6 +90,7 @@ struct dce_dccg {
int dprefclk_ss_percentage;
/* DPREFCLK SS percentage Divider (100 or 1000) */
int dprefclk_ss_divider;
int dprefclk_khz;
};