Add pinctrl support for Bitmain BM1880 SoC. This SoC only supports
pinmuxing and the pinctrl registers are part of the sctrl block.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Add GPIO line names for Sophon Edge board based on BM1880 SoC from
Bitmain. Line names are based on the board schematics as well as the
96Boards Consumer Edition specification v1.0.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Add GPIO support for Bitmain BM1880 SoC based on Designware APB GPIO
controller IP. IP exposes 3 GPIO controllers with a total of 72 pins.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
- Pinctrl related fixes for the A33 NAND controller
- Fix the refcounting of DT nodes in our core code
- Fix for a typo'd DT property
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXLmrygAKCRDj7w1vZxhR
xWPzAPsG8IOfePeDDq5QtpXuO/ksMCb1H/+1dsHwe6yW2CFrQwD/W3p/n5i/ervO
tUtfb4a4uz0WthUrApkWlCUS30IGdwU=
=/Hf9
-----END PGP SIGNATURE-----
Merge tag 'sunxi-fixes-for-5.1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into fixes
Allwinner fixes for 5.1
- Pinctrl related fixes for the A33 NAND controller
- Fix the refcounting of DT nodes in our core code
- Fix for a typo'd DT property
* tag 'sunxi-fixes-for-5.1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sun8i: a33: Reintroduce default pinctrl muxing
arm64: dts: allwinner: a64: Rename hpvcc-supply to cpvdd-supply
ARM: sunxi: fix a leaked reference by adding missing of_node_put
ARM: sunxi: fix a leaked reference by adding missing of_node_put
Signed-off-by: Olof Johansson <olof@lixom.net>
* Add ADC temp for temp alarm node on PM8998
* Add ref clks for DSI PHYs on SDM845 and MSM8916
* Add CPU capacity and topology on SDM845
* Add display and gpu related nodes on MSM8996
* Add sound and hdmi display support on DB820C
* Fixup thermal nodes on MSM8998 platform
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJcwoc2AAoJEFKiBbHx2RXV79sP/1l5EzWuFvypYASL+GTO7p2V
VUdsg6LQIniM1+A3WbYfHHX6gaydbd/M1fzt4gbK7bMcCfMkIkC5awvORjYF723n
LohxsAv0VVSEYZQBO6cPyP0TYPrUaIvtyjuazXHVJ+sdoapkuX6n8/nlsiBtqrAs
3gsH3CHYLkDH2OZdUqwiMmksXjg15sXCiCrGgygNYISyV43tujPDBCy5632RF14j
AHqL0WdyqJE5CxTJ70I9jZis4x0Ramj56fdhjue6zOZ8uGEcXgBezOyao8T8CpxK
cbl9KhYDQBHK+DC991lzEJsqYrup+xeZ1P+PI7HVILYogcyjRa8ZvnKQ3DXimhSW
6bUWKjsDmONMiKFXZDsDFnZYrOIH2gdd2q+Ve4J++zeGahqn3MbL1JxFBCgKnQ+S
dAWgk/iSazbwrqxRcpkn4SsRsrdFxBVMWMWU3OVTgcDV/6wHATcCMqW114djlYMJ
jNU9JiqHFntDX/WRu8ZIVGxv7qPhD0DL1w0NK+5gPofnfGasDjMppaH058xHJqPO
9F8+zaKljzoIzXiEyk2j/VimFuL6caLI7kv0Qi1WC0hAA1oJ8ZzPMe8eWCnFuG22
Ldn/Dr3iKIzv8L3x03EIA1raNB6sMhSZgb7IEFb7CC8QJ3BjeDR2izTnDk5kIKWO
14/sVe2utNiUOBZr9u2r
=99VN
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/dt
Qualcomm ARM64 Updates for v5.2 - Part 2
* Add ADC temp for temp alarm node on PM8998
* Add ref clks for DSI PHYs on SDM845 and MSM8916
* Add CPU capacity and topology on SDM845
* Add display and gpu related nodes on MSM8996
* Add sound and hdmi display support on DB820C
* Fixup thermal nodes on MSM8998 platform
* tag 'qcom-arm64-for-5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: dts: msm8998: thermal: Restrict thermal zone name length to under 20
arm64: dts: msm8998: thermal: Fix number of supported sensors
arm64: dts: msm8998-mtp: thermal: Remove skin and battery thermal zones
arm64: dts: db820c: Add sound card support
arm64: dts: apq8096-db820c: Add HDMI display support
arm64: dts: Add Adreno GPU definitions
arm64: qcom: msm8996.dtsi: Add Display nodes
arm64: dts: msm8996: Add display smmu node
arm64: dts: msm8996: Add graphics smmu node
arm64: dts: sdm845: Add CPU capacity values
arm64: dts: sdm845: Add CPU topology
arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs
arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY
arm64: dts: qcom: pm8998: Use ADC temperature to temp-alarm node
Signed-off-by: Olof Johansson <olof@lixom.net>
for the rk3328-roc-cc and some minor fixes for rk3399 and rockpro64.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAly/g+YQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgX5oB/0Sub17eWc+RSKRLTKoBZooMK+aS4iEqzl9
T3Um1m0c/zR5XY+cMnmlvBUp9ryu/XEjiX9pi2EiE/Oio2Ty6t4q/4td+9BvH+gb
TbCmNI+ZVWvqrMyRAPjrXT3lJc2dOIWbf9Ej02MdZC/WSG5JfWMKfI8PxZRV4IlW
TSJbQLVVjrVcFk0J2Ov/iDyIuDNBOhN4zUNm3YbBGLJ0Wa0KmoaHa0qtTK5SRcEm
ZUztuzscla5nWo2kXI2Aw2UMiparGaqGT+uAODGdhIbgIsa+o2D9WzAfW4xalvlJ
NSzXvJIHGIDdWmBEku8JNitWh3S85Y4DYfXv/kGqWU6CYGaTqr5z
=Sd0J
-----END PGP SIGNATURE-----
Merge tag 'v5.2-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
Bulk conversion of remaining gpios to the helper constants, new peripherals
for the rk3328-roc-cc and some minor fixes for rk3399 and rockpro64.
* tag 'v5.2-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: fix IO domain voltage setting of APIO5 on rockpro64
arm64: dts: rockchip: fix cts, rts pin assign of UART3 for rk3399
arm64: dts: rockchip: bulk convert gpios to their constant counterparts
arm64: dts: rockchip: enable display nodes on rk3328-roc-cc
arm64: dts: rockchip: eMMC additions for rk3328-roc-cc
Signed-off-by: Olof Johansson <olof@lixom.net>
The old "cooling-{min,max}-state" properties for thermal bindings were
ratified to "cooling-{min,max}-level" by commit eb168b70de ("of:
thermal: Fix inconsitency between cooling-*-state and cooling-*-level"),
which were later removed entirely by commit e04907dbc2 ("dt-bindings:
thermal: Remove "cooling-{min|max}-level" properties").
The pwm-fan binding, however, was apparently in-flight in parallel with
that ratification, and so managed to introduce an example of the old
properties which escaped the scope of the later cleanup and has thus
continued to be dutifully copied for new boards despite being useless.
Clean up these remaining undocumented anachronisms to minimise any
further confusion.
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add wlan_disable signal hog for rfkill signal on clearfog-gt-8k
(Armada 8040 based board)
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCXL7EYQAKCRALBhiOFHI7
1f2CAJ4nM5kwS3ogb4dRIixdHzTVxZZabwCdE2uvCR2nncS4NC05L07TKISs/pk=
=v9Z0
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-5.2-1' of git://git.infradead.org/linux-mvebu into arm/dt
mvebu dt64 for 5.2 (part 1)
Add wlan_disable signal hog for rfkill signal on clearfog-gt-8k
(Armada 8040 based board)
* tag 'mvebu-dt64-5.2-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: clearfog-gt-8k: add wlan_disable signal hog
Signed-off-by: Olof Johansson <olof@lixom.net>
Our usual bunch of changes shared between arm and arm64, the most notable
one being:
- Fix of improper usage of DT bindings, thanks to the DT validation
- Add the SID for the H3 and H5
- New board: RerVision H3-DVK
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXLm2aQAKCRDj7w1vZxhR
xQJYAQDs7mcoEHwBqw+1iZGmHZuvj4jJXdAd/FkmoujMawaGoQD/a4zddy8AL7s9
WA9I42cSuBwfZjftLX/br4Ycssd1sgQ=
=90I8
-----END PGP SIGNATURE-----
Merge tag 'sunxi-h3-h5-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Allwinner H3/H5 changes for 5.2
Our usual bunch of changes shared between arm and arm64, the most notable
one being:
- Fix of improper usage of DT bindings, thanks to the DT validation
- Add the SID for the H3 and H5
- New board: RerVision H3-DVK
* tag 'sunxi-h3-h5-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sun8i: mapleboard: Remove cd-inverted
ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI
ARM: dts: sun8i: h3: bluetooth for Banana Pi M2 Zero board
ARM: dts: sun8i: h3: Add default dr_mode
ARM: dts: sun8i: h3: Refactor the pinctrl node names
ARM: dts: sunxi: h3/h5: Remove stale pinctrl-names entry
ARM: dts: sunxi: h3/h5: Add device node for SID
ARM: dts: sun8i-h3: Add support for the RerVision H3-DVK board
Signed-off-by: Olof Johansson <olof@lixom.net>
This PR is pretty significant, but it been mostly about:
- Fixing the DTC warnings in most of our DT. We're now down to 2
warnings, from several thousands.
- Fixing a good number of minor issues, typos, and so on thanks to the DT
validation tools
- Describe the MBUS controller and the special DMA RAM mapping on the A13
- Add support for the LRADC on the A83t
- Add support for the I2C bus used for the PMIC on the A33
- Start using the DT annotation /omit-if-no-ref/ on our pinctrl nodes
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXLmxsgAKCRDj7w1vZxhR
xQs0APwIUuCrLfRD0av6xeCI4bon+G6drCxNVqkgf/cm3sAd5AEAzd6Ok74CEJar
xlSPxgqpBxCVyt2bxQxfN5mch2OPKgA=
=HH/F
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Allwinner DT changes for 5.2
This PR is pretty significant, but it been mostly about:
- Fixing the DTC warnings in most of our DT. We're now down to 2
warnings, from several thousands.
- Fixing a good number of minor issues, typos, and so on thanks to the DT
validation tools
- Describe the MBUS controller and the special DMA RAM mapping on the A13
- Add support for the LRADC on the A83t
- Add support for the I2C bus used for the PMIC on the A33
- Start using the DT annotation /omit-if-no-ref/ on our pinctrl nodes
* tag 'sunxi-dt-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (65 commits)
ARM: dts: sun8i: a83t: Enable USB OTG controller on some boards
ARM: dtsi: axp81x: add USB power supply node
ARM: dts: sun5i: Reorder pinctrl nodes
ARM: dts: sun6i: i7: Remove useless property
ARM: dts: sun4i: lime: Fix the USB PHY ID detect GPIO properties
ARM: dts: sun4i: protab2: Remove stale pinctrl-names entry
ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI
ARM: dts: sun8i: v40: bananapi-m2-berry: Sort device node dereferences.
ARM: dts: sun5i: Add the MBUS controller
dt-bindings: sunxi: Add compatible for OrangePi 3 board
ARM: dts: sun8i: a83t: Add I2C2 pinmux setting for PE pins
dt-bindings: arm: sunxi: Add Beelink GS1 board
ARM: dts: sun8i: tbs-a711: Add support for volume keys input
ARM: dts: sunxi: Add R_LRADC support for A83T
ARM: dts: sunxi: Improve A33 NAND transfers by using DMA
ARM: dts: sun8i: tbs-a711: Enable UART2 (for NEO-6M GPS module)
ARM: dts: sunxi: Remove useless pinctrl nodes
ARM: dts: sunxi: Remove pinctrl groups setting bias
ARM: dts: sunxi: Remove useless address and size cells
ARM: dts: sunxi: Conform to DT spec for NAND controller
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This contains a bunch of changes all across the board. Perhaps the most
notable introduction here is support for the Jetson Nano Developer Kit.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAly4jscTHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoTevD/9jwO9JSPox9Cuy/d1V+R4XXk5xbf3i
c+oMpWqWMmkQMkEi6VA8w76WpRej5WyClCvxbY9cdoY5xpNYpnLN6sw2c6kMCwC1
EYM7BVuJh1DLTfUWbj8N7TTxZP5+PtKDWRAVfgnq9i4W52WjfwlUdJt8OmPd4KFf
zHiSmf4oJiz5aiIX/fqQf852HE9lpijnWrHcsdDqRzBh64O83jO52JF3bBEnwg23
x1i1aMzlYrOoNmAJHZxUxfFG+/qF6BcKY7ba7DQOIHXGBwUKGDMbELNLg4yuS0So
NcEVsZZEjTtOYmzMWKqm3wSQISYSguU43QtyRBkBZLOrHvEQRjgNRKs3Bmvug7L3
jCwA/qyA7kkYeBr9gn9CfE42ih8Az5dki38rzo5vfXqF6fALIf+J7MIur+p08kBk
VOzMvDPT2FWXlykSfOaCq6ppdo0Fh88qDFxTCx97nYm6s7NDw1ZUI1IDZ0JgoA7n
YqH0bC9WDAyA17gsyUH+mynvLiQvJ4kpAIaYa2JxlITXt05L5mTHEpsnelcSOrOx
K96/M3r+z6/1OP68IqPWC0oh3adwJ9tuVZv2iO//cWeEXwO48wH6KERYJqG6cYLk
x+tFhNPBy8U4x0FIEbpXW7s9bKWD07TpDijRDa4NriegkpTPmEm644QRPsBEgQuX
qtzaoIrFFGOJIg==
=V3kv
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.2-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.2-rc1
This contains a bunch of changes all across the board. Perhaps the most
notable introduction here is support for the Jetson Nano Developer Kit.
* tag 'tegra-for-5.2-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Remove regulator hacks on Jetson TX2
arm64: tegra: Enable XUSB on P2771
arm64: tegra: Add XUSB and pad controller on Tegra186
arm64: tegra: Add NVIDIA Jetson Nano Developer Kit support
arm64: tegra: smaug: Move PLL power supplies to XUSB pad controller
arm64: tegra: jetson-tx1: Move PLL power supplies to XUSB pad controller
arm64: tegra: Enable command queue for Tegra186 SDMMC4
arm64: tegra: Fix default tap and trim values
arm64: tegra: Add supply for temperature sensor on P2888
arm64: tegra: Enable aconnect, ADMA and AGIC on Jetson TX1
arm64: tegra: Add L2 cache topology to Tegra210
arm64: tegra: Enable CPU idle support for Shield
arm64: tegra: Enable CPU idle support for Smaug
arm64: tegra: Enable CPU idle support for Jetson TX1
arm64: tegra: Add CPU idle states properties for Tegra210
arm64: tegra: Fix timer node for Tegra210
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add base support for Agilex platform
- Add 'cap-mmc-highspeed' Stratix10 and 32-bit SoCFPGA platform
- Increase Stratix10 QSPI support to 100 MHz
-----BEGIN PGP SIGNATURE-----
iQJIBAABCgAyFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAly1Mv8UHGRpbmd1eWVu
QGtlcm5lbC5vcmcACgkQGZQEC4GjKPS7mg//d56np59wWQ1k4wP7FFo3ewnNcqdu
Zr3e2T586KCRFpCAH2zsY32jzPLPgzgX0ssiXg4FDr8Q0tptDfYFtkzUfM+9J8LH
91VhGCUoq3YfKudnovl4vOo9QLTXyXxm9qSv4MN+8z+np/uLOc05qWFrPS6Ylh0O
cYcC/1hif8svnxziH9d7QwF3Eely8aYAETY4waQVG5SDkzVMG9JuecC8rfxfOyCv
uMy4jBTeOY7xDAJwl0yILPcI3qLZX97AoBUD64b7TmgGkrraSm9xijDmQKRFgFlz
r42Ze4o1kjY+iKYefyXJiE+k4TQUoark8V0tBLst8KujiveH6gPQ8T8s75d0djFj
r9koVafOege64KsY3Gdrkkv7e9vI8oCqcy/dvoApb9RBA3X+4V/gXJCZxv5KPOcn
t3/swEsHKYnmJ1GumkmCnO+2aGKkDcJewJkQrnU4DNC8AVyGOyehPu9kqYfrMC3g
eODzoHWC+4ZKltglfxP0mihqXHXcdYrSHfxAKtWAZyTect20w5w3dCsvvvpoxaA2
gYr008kqrGVIxumpCZlbaEVnr/0PnHdiMstIWMVsIOsvs8EuvQrbmJJS2TSqhhI0
gUFyADgnh4RCV/cD3EeYC9dokM6Ms2SDB/r7QdnQG1aELkVi51hSJf201w6fYemI
Uq1EBLmMGaF8zow=
=PxBZ
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_updates_for_v5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA DTS updates for v5.2
- Add base support for Agilex platform
- Add 'cap-mmc-highspeed' Stratix10 and 32-bit SoCFPGA platform
- Increase Stratix10 QSPI support to 100 MHz
* tag 'socfpga_dts_updates_for_v5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: agilex: Add initial support for Intel's Agilex SoCFPGA
arm64: dts: stratix10: increase QSPI max frequency to 100MHz
arm64: dts: stratix10: enable MMC highspeed support
ARM: dts: socfpga: enable MMC highspeed support
Signed-off-by: Olof Johansson <olof@lixom.net>
* Hi3660 SoC and related boards:
- Added DMA support for the uart nodes
- Added the asp DMA controller node
- Replaced dma-min-chan with dma-channel-mask to follow the binding
* Hi3670 SoC and related boards:
- Reused Hi3660 reset to support Hi3670, updated the binding
document and added dts node
- Reused Hi3660 MMC controller to support Hi3670, updated the
binding document and added related nodes to support SD and WiFi
for the SoC and hikey970 board
- Added UFS controller node
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJctKRtAAoJEAvIV27ZiWZcHWUP/2adwR95p9SDb4WUZsmxWAPm
W3vveeLqack6K70ySStBmNCgrTyW5txJcJOFU4ceoERBOkpEfWJV6SEuWMma0ssW
Vz4Zs15T+d6Pz2UbIi7owhj1ooyxVuJpPwZRFMs0esD8d92ZuptTWAnnbyA5WCKB
Obvucl04QUHpzmCQAPKXW2icQFmGPCA+UOviSR/0Kj00XDhmxVkpUl54fe16r6e+
keVT5ElVuI4SZax5BPIHiUryKbujL6A+n7y3goV57MGkKhklJ78BRb3czxLUpgSq
xyqfYYnpTGszZ/gNIIYohHvp1N09dMXXhmIt22zfUCpG+1ClquK8oDtZzDBAl0wV
ZtXn1Khb+D96nzZobYIEhKX0ki76OeRIJAj1gxLkpMJkhp8amGLmeVJP6ER88zuN
ypVSpXfPnOAeGGcrVUIXhYIGqBWinM7iCasX9lctkD+Mui0bBjaF5NFWuNAIo74w
N57yNRQRdK0CMxuyU57lrxPzlmWibnSx3gVz8BXTSBBXDkTefmwKITDjyJ8swo8m
voeBOAYOdbdCKWaU5Nh1DAfBorvP3MPXi33KkdTUaMzkd5pqbNq02IqG7DlFE3L1
CMw4PnCgLoVVN8s7ud8l1wiXkeXJSgskE2P/c57/4t4cGargC8xyz8ALXobCJFGq
N795O6Za9LYzTQyLpyzn
=9+Sr
-----END PGP SIGNATURE-----
Merge tag 'hisi-arm64-dt-for-5.2' of git://github.com/hisilicon/linux-hisi into arm/dt
ARM64: DT: Hisilicon SoCs DT updates for 5.2
* Hi3660 SoC and related boards:
- Added DMA support for the uart nodes
- Added the asp DMA controller node
- Replaced dma-min-chan with dma-channel-mask to follow the binding
* Hi3670 SoC and related boards:
- Reused Hi3660 reset to support Hi3670, updated the binding
document and added dts node
- Reused Hi3660 MMC controller to support Hi3670, updated the
binding document and added related nodes to support SD and WiFi
for the SoC and hikey970 board
- Added UFS controller node
* tag 'hisi-arm64-dt-for-5.2' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hisilicon: hi3670: Add UFS controller support
arm64: dts: hi3660: Fixup unofficial dma-min-chan to dma-channel-mask
arm64: dts: hi3660: Add hisi asp dma device
arm64: dts: hi3660: Add dma to uart nodes
arm64: dts: hisilicon: hikey970: Add SD and WiFi support
arm64: dts: hisilicon: hi3670: Add MMC controller support
dt-bindings: mmc: Add HI3670 MMC controller binding
arm64: dts: hisilicon: hi3670: Add reset controller support
dt-bindings: reset: Add HI3670 reset controller binding
Signed-off-by: Olof Johansson <olof@lixom.net>
- Align xlnx-zynqmp-clk.h file name and separate
binding for clock driver
- Add TI quirks to zynqmp boards
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAly0Q7IACgkQykllyylKDCHtLACfZGBpUNq5coHf3tQohyNyROnh
q9cAn11bsVu3/BDOYhAO9TzKuYtzCACh
=n0Wu
-----END PGP SIGNATURE-----
Merge tag 'zynqmp-dt-for-v5.2' of https://github.com/Xilinx/linux-xlnx into arm/dt
arm64: dts: zynqmp: DT changes for v5.2
- Align xlnx-zynqmp-clk.h file name and separate
binding for clock driver
- Add TI quirks to zynqmp boards
* tag 'zynqmp-dt-for-v5.2' of https://github.com/Xilinx/linux-xlnx:
arm64: zynqmp: dt: Add TI PHY quirk
dt-bindings: xilinx: Separate clock binding from firmware doc
include: dt-binding: clock: Rename zynqmp header file
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Use proper clock rates for GSCALER module on TM2 boards.
2. Add clocks for local paths on DECON and GSCALER modules of
Exynos5433.
3. Add Slim SecuritySubSystem to Exynos5433.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAlyzVIgQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD11HFD/9uiXfydqVDwnC6OgJg0usKHXbfA8qhtgdK
IGYTv99Cxk3uR2MHkCDI1xDeMUcgAL7Dd9DI8HI0rGlCJ0zWVS/UtMD2oG3nd2p0
A0g8kbp7jxKU2UjfjKrcnd62aXbqgvz+T8/Phvjhv+UIOOEChqjeWj6rqCVVCOLk
jSDXi3zu1buO1Z+XuvIIn9/YmPOXevrAy8qs69NNIMbKYAx8aA5tsg2zmwenJxKp
43EXVjgfTFyCVjezflkezj+osxAiUHKD8xkbW5byPWnhop/4uuvEv6G6AwEA8zcm
sXMmWSqvo3nuCcqDe8MiE18ZvcSl5FpM9KNAhN8WD1mS3o++uBgntpMOsIHmq2Py
591MWBt0FsmYD0wS4uWCqISN/rQPJiXxuCzk4k1Wv92/TKSOarTZBuqi2R5u2pP+
lposx27g2XxYjv6VPkOU0+4802R3Mliyo3qyT9EysoxJBy//U2DAVXc7gQARqAJJ
0UW95PafFI/UbLyeSOBQriVAeBFXcVPqSL80jdf7qk7G7VS8JRbx1gwKA0VLh4+o
IE4QLIKNltW3QgdKsvx7Dx1T0VPG5ztSYCZQRs13WD+I7SosVWOlZ1ti+ecFJp68
GCytNRibpsSTHNcU8LviguHjvWjstBk3QmBnVGBDLH8GXNgOIhnEoq3hxyeNGVLe
FDThtgkr1Q==
=hXn6
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM64 changes for v5.2
1. Use proper clock rates for GSCALER module on TM2 boards.
2. Add clocks for local paths on DECON and GSCALER modules of
Exynos5433.
3. Add Slim SecuritySubSystem to Exynos5433.
* tag 'samsung-dt64-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add SlimSSS to Exynos5433
arm64: dts: exynos: add DSD/GSD clocks to DECONs and GSCALERs of Exynos5433
arm64: dts: exynos: configure GSCALER related clocks on TM2
Signed-off-by: Olof Johansson <olof@lixom.net>
and emmc cleanups for rk3399. New boards are the OrangePi (rk3399) and
NanoPi NEO4. Both the OrangePi as well as the NanoPC/Pie family also
directly got some additional features added after the boards itself.
The Rock960 family (rock960+ficus) got their power-tree cleaned to match
the schematics and also got hdmi-audio and their gpu enabled.
Mali support also got enabled on the RockPi4 and finally both
rk3328-rock64 and rk3328-roc-cc got some additional features.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlyjIrAQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgTCuB/9wEiNDr5DvIYHdQM0/TrAWzMepdaO2YAHI
5v2NaZ3l0LDB1yXEJUJn/f7PRbGW9IETaldXLWKca8g8zJq6tM60p4gWx0XHw2hq
szajRwBhbvo16u3vSNOJ1LlK8SdfI+ENx9129qWVtXToODK/0TIo+ubOpPT3uBxt
P2Og+2F0zoj1WSWTXPEaGexF0YnwRp1v5NODF9XV6jpB9wAL+CYsllse7GFLxc52
sdp2Lfp/r/3VzHOCDOJ8e9YPXmLIYrjBQNw12/XkGdbnMKucCnI8GYxdkU7gSUh8
9ryBAAjOWREopY8GwdBfX+C+l1AKUFi8YFvC6PCxqFoseglzvAK0
=/JXo
-----END PGP SIGNATURE-----
Merge tag 'v5.2-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
Core new soc features are hdmi-cec for rk3328, scheduler capacity-values
and emmc cleanups for rk3399. New boards are the OrangePi (rk3399) and
NanoPi NEO4. Both the OrangePi as well as the NanoPC/Pie family also
directly got some additional features added after the boards itself.
The Rock960 family (rock960+ficus) got their power-tree cleaned to match
the schematics and also got hdmi-audio and their gpu enabled.
Mali support also got enabled on the RockPi4 and finally both
rk3328-rock64 and rk3328-roc-cc got some additional features.
* tag 'v5.2-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (23 commits)
arm64: dts: rockchip: Decrease emmc-phy's drive impedance on rk3399-puma
arm64: dts: rockchip: Define drive-impedance-ohm for RK3399's emmc-phy.
arm64: dts: rockchip: Disable DCMDs on RK3399's eMMC controller.
arm64: dts: rockchip: Add nanopi4 ethernet phy
arm64: dts: rockchip: Add PWM fan for NanoPC-T4
arm64: dts: rockchip: Add the fusb typec manager to rk3399-orangepi
arm64: dts: rockchip: Specify vid supply for the rk3399-orangepi compass (AK09911)
arm64: dts: rockchip: Fix clock names and add missing supplies for bluetooth on rk3399-orangepi
arm64: dts: rockchip: Add 12V DCIN regulator to rk3399-ficus
arm64: dts: rockchip: Rename vcc_sys into vcc5v0_sys on rk3399-rock960
arm64: dts: rockchip: Add Nanopi NEO4 initial support
arm64: dts: rockchip: enable hdmi audio out for rk3399-rockpro64
arm64: dts: rockchip: Add support for the Orange Pi RK3399 board.
arm64: dts: rockchip: enable mali on rock960 boards
arm64: dts: rockchip: enable mali on Rock Pi 4
arm64: dts: rockchip: add rk3328-roc-cc cpu-supply entries for all cpu nodes
arm64: dts: rockchip: give some life to the rk3328-roc-cc leds
arm64: dts: rockchip: add #sound-dai-cells to HDMI of rk3328
arm64: dts: rockchip: add ir-receiver node on rk3328-rock64
arm64: dts: rockchip: add leds node on rk3328-rock64
...
Signed-off-by: Olof Johansson <olof@lixom.net>
The thermal core restricts names of thermal zones to under 20
characters. Fix the names for a couple of msm8998 thermal zones.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Tested-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Andy Gross <agross@kernel.org>
msm8998 has 22 sensors connected in total, 14 on the 1st controller, 8
on the 2nd controller. Increase the number to allow sensors with ID 12
and 13 to be registered.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Tested-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Andy Gross <agross@kernel.org>
The msm8998-mtp doesn't have TSENS-based sensors wired up for skin and
battery thermal zones. TSENS sensors should be common across all boards
using the SoC and shouldn't be board-specific as these entries.
They also show the following error when trying to read the temperature
cat: read error: Invalid argument
Remove these board-specific erroneous thermal zones.
Fixes: 4449b6f248 ("arm64: dts: qcom: msm8998: Add tsens and thermal-zones")
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Tested-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Andy Gross <agross@kernel.org>
The XXTI fixed-clock is the input to the SoC therefore it should not be
inside the soc node. This also fixes DTC W=1 warning:
arch/arm64/boot/dts/exynos/exynos7.dtsi:90.17-94.5:
Warning (simple_bus_reg): /soc/xxti: missing or empty reg/ranges property
While moving, change the name of the xxti node to match the generic type
of device (following DeviceTree specification).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
The ARM PMU and ARM architected timer nodes are part of ARM CPU design
therefore they should not be inside the soc node. This also fixes DTC
W=1 warnings like:
arch/arm64/boot/dts/exynos/exynos7.dtsi:472.11-480.5:
Warning (simple_bus_reg): /soc/arm-pmu: missing or empty reg/ranges property
arch/arm64/boot/dts/exynos/exynos7.dtsi:482.9-492.5:
Warning (simple_bus_reg): /soc/timer: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This patch fixes IO domain voltage setting that is related to
audio_gpio3d4a_ms (bit 1) of GRF_IO_VSEL.
This is because RockPro64 schematics P.16 says that regulator
supplies 3.0V power to APIO5_VDD. So audio_gpio3d4a_ms bit should
be clear (means 3.0V). Power domain map is saying different thing
(supplies 1.8V) but I believe P.16 is actual connectings.
Fixes: e4f3fb4909 ("arm64: dts: rockchip: add initial dts support for Rockpro64")
Cc: stable@vger.kernel.org
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch adds support both digital and analog audio on DB820c.
This board has HDMI port and 3.5mm audio jack to support both digital
and analog audio respectively.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
The APQ8096 DB820c platform provides HDMI output. The MDSS block on
8x96 supports a direct HDMI out. Populate the MDSS, MDP and HDMI DT
nodes. Also, add the HDMI HPD and DDC pinctrl nodes with the bias
and driver strength specified for this platform.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Add an initial node for the Adreno GPU.
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Specify the relative CPU capacity of all SDM845 AP cores.
The values were provided by Qualcomm engineers.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Andy Gross <agross@kernel.org>
The 8 CPU cores of the SDM845 are organized in two clusters of 4 big
("gold") and 4 little ("silver") cores. Add a cpu-map node to the DT
that describes this topology.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 10nm PHY.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Add 'xo_board' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 28nm PHY.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Andy Gross <agross@kernel.org>
The temperature information from the temp-alarm block itself is very
coarse ("temperature is above/below trip points"). Provide the driver
with the die temperature channel of the ADC on the PMIC for more precise
readings.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Add the Audio DSP (ADSP) and Compute DSP (CDSP) nodes for TrustZone
based remoteproc, supporting booting these cores on e.g. the MTP, and
enable the same for the MTP.
Tested-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Define the rmtfs memory node. As the memory region specified in version
10 of the memory map is only 1MB a chunk of unallocated memory is
chosen.
Tested-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Update existing and add missing regions to the reserved memory map, as
described in version 10.
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Wire up the reset controller in the Qcom UFS controller for the PHY.
This will be used to toggle PHY reset during initialization of the PHY.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
lx2160a supports pw20 which could help save more power during cpu is
dile. It needs system firmware support via PSCI.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
v2 of "clk: imx: Refactor entire sccg pll clk" dropped the implicit
reparenting of the PLL output from the bypass clock to the real
PLL. The commit introducing the GPU node had only been tested against
v1 of this patch. Without an explicit reparent to the real PLL the
GPU is stuck at the bypass clock rate of 25MHz, serverly hampering
performance.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Link the SW1AB regulator to the GPU domain, so that it gets enabled
when needed.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This is very similar to imx8mq cpufreq-dt support.
Operating points are from datasheet:
https://www.nxp.com/docs/en/data-sheet/IMX8MMCEC.pdf
Higher opps were omitted (just like imx8mq) because it requires checking
speed grade from OCOTP fuses.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add an initial description of the i2c1 bus with a pca9646 i2c switch and
various gpio expanders and sensors behind that. Only add the sensors
which already have upstream drivers.
According to the datasheet the pca9646 is software compatible with
pca9546 so no driver changes should be required.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On i.MX8QXP, SCU uses MU1 general interrupt channel #3 to notify
user for IRQs of RTC alarm, thermal alarm and WDOG etc., mailbox
RX doorbell mode is used for this function, this patch adds
support for it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This enables the Vivante GC7000L GPU on the i.MX8MQ SoC.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Zii Ultra design, also known as RDU3, is the i.MX8M based successor
to the the i.MX6 based RDU2. This adds the basic board support for all
components which are supported by the upstream kernel at this time.
The board comes in 2 different versions, called RMB3 and Zest, which
are derived from the same design, but have different layouts and a
few small differences in the populated components.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
There is currently no DT binding for GPIO rfkill signals. To make
mini-PCIe attached WiFi devices work, use gpio-hog to hold the
wlan_disable signal de-asserted.
Signed-off-by: Thomas Schreiber <tschreibe@gmail.com>
[baruch: add pinctrl node; rename tag]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
blsp1_i2c1 is at 0x0c175000
blsp2_i2c5 is at 0x0c1ba000 (the label is correct)
Fixes: 1e71d0c273 ("arm64: dts: qcom: msm8998: Enumerate i2c controllers")
Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Andy Gross <agross@kernel.org>
The compatible flag should be different for each board to match
with the dtb and to let the bootloader pick the appropriate dtb.
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
This adds the gpio-ranges property so that the GPIO pins are initialized
by the GPIO framework and not pinctrl. This fixes a circular dependency
between these two frameworks so GPIO hogging can be used on this board.
This was not tested on this particular hardware, however this same
change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Andy Gross <agross@kernel.org>
This adds the gpio-ranges property so that the GPIO pins are initialized
by the GPIO framework and not pinctrl. This fixes a circular dependency
between these two frameworks so GPIO hogging can be used on this board.
This was not tested on this particular hardware, however this same
change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Andy Gross <agross@kernel.org>
This adds the gpio-ranges property so that the GPIO pins are initialized
by the GPIO framework and not pinctrl. This fixes a circular dependency
between these two frameworks so GPIO hogging can be used on this board.
This was not tested on this particular hardware, however this same
change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Andy Gross <agross@kernel.org>
This adds the gpio-ranges property so that the GPIO pins are initialized
by the GPIO framework and not pinctrl. This fixes a circular dependency
between these two frameworks so GPIO hogging can be used on this board.
This was not tested on this particular hardware, however this same
change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Amarula A64-Relic board by default bound with OV5640 camera,
so add support for it with below pin information.
- PE13, PE12 via i2c-gpio bitbanging
- CLK_CSI_MCLK as external clock
- PE1 as external clock pin muxing
- ALDO1 as AVDD supply
- DLDO3 as DOVDD supply
- ELDO3 as DVDD supply
- PE14 gpio for reset pin
- PE15 gpio for powerdown pin
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Some camera modules have the SoC feeding a master clock to the sensor
instead of having a standalone crystal. This clock signal is generated
from the clock control unit and output from the CSI MCLK function of
pin PE1.
Add a pinmux setting for it for camera sensors to reference.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
According to the device tree specification, any bus should have a 'bus'
node name.
Since it isn't the case for us on the DE2 bus, fix that.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Various regulators were marked as always-on for Jetson TX2. At this
point, all of the regulators are properly hooked up, so this workaround
is no longer required.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable the relevant pads for XUSB support on P2771-0000 and hook up the
USB supply voltage regulators to the ports.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Jetson Nano Developer Kit is a Tegra X1 based development board. It
is similar to Jetson TX1 but it is not pin compatible. It features 4 GB
of LPDDR4, an SPI NOR flash for early boot firmware and an SD card slot
used for storage.
HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
Ethernet controller provides onboard network connectivity. An M.2 Key-E
slot with PCIe x1 adds additional possibilities.
A 40-pin header on the board can be used to extend the capabilities and
exposed interfaces of the Jetson Nano.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The XUSB pad controller is responsible for supplying power to the PLLs
used to drive the various USB, PCI and SATA pads. Move the PLL power
supplies from the PCIe and XUSB controllers to the XUSB pad controller
to make sure they are available when needed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The XUSB pad controller is responsible for supplying power to the PLLs
used to drive the various USB, PCI and SATA pads. Move the PLL power
supplies from the PCIe and XUSB controllers to the XUSB pad controller
to make sure they are available when needed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Neither the OHCI or EHCI bindings are using the phy-names property, so we
can just drop it.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This patch adds the HDMI, CVBS and CEC attributes and nodes to support
full display on the U200 Reference Design.
AO-CEC-B is used by default and AO-CEC-A is disabled.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This patch adds the HDMI, CVBS and CEC attributes and nodes to support
full display on the SEI510 STB.
AO-CEC-B is used by default and AO-CEC-A is disabled.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This patch adds the HDMI, CVBS and CEC attributes and nodes to support
full display on the X96 Max STB.
AO-CEC-B is used by default and AO-CEC-A is disabled.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Amlogic G12A embeds 2 CEC controllers :
- AO-CEC-A the same controller as in GXBB, GXL & GXM SoCs
- AO-CEC-B is a new controller
Note, the two controller can work simultanously since 2 Pads can
handle CEC, thus this SoC can handle 2 distinct CEC busses.
This patch adds the nodes for the AO-CEC-A and AO-CEC-B controllers.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This patch corrects the SPDX License Identifier style
in the arm64 Hardware Architecture related files.
Suggested-by: Joe Perches <joe@perches.com>
Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This patch adds the device nodes of ARM Performance Monitor Uint
for mt8173.
Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
The cpu type of cpu2 and cpu3 should be cortex-a72, not cortex-a57.
Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Enable the USB2 and USB3 Host ports on the X96 Max Set-Top-Box.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Enable the USB2 OTG and USB3 Host ports on the S905D2 Reference Design.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Enable the USB2 and USB3 Host ports on the SEI520 Set-Top-Box.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add support for the :
- ADC Touch key
- Bluetooth Module on UART A
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add system regulators for the S905D U200 reference design.
Add some regulators. Still missing
* VDD_EE (0.8V - PWM controlled)
* VDD_CPU (PWM controlled)
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This patch adds the nodes for the USB Complex found in the Amlogic
G12A SoC.
It includes the :
- 2 USB2 PHYs
- 1 USB3 + PCIE Combo PHY
- the USB Glue with it's DWC2 and DWC3 sub-nodes
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This patch adds the SAR ADC controller node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Remove the "reg-names" property from the display node of R-Car Gen3 R8A77965
device tree.
No other mainline R-Car Gen3 SoC has that property specified.
Fixes: 2f2c71bfc8 ("arm64: dts: renesas: r8a77965: Populate the DU instance placeholder")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[reworded commit message, sent upstream]
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
MMC1 is used on some H6 boards we want to support. Typical use is 4-bit
SDIO interface with a WiFi chip. Add pin definitions for this use case.
As this is the only possible configration for mmc1, make it the default
one, too.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Using standard CCF interface to set vdec/venc parent clk
and clk rate.
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
Signed-off-by: Qianqian Yan <qianqian.yan@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
The workaround for a hardware bug preventing this from working has been
merged now, so command queue support can be enabled again for Tegra186.
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Default tap and trim values are incorrect for Tegra186 SDMMC4. This
patch fixes them.
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The VCC supply property is not populated for the temperature sensor on
the P2888 board and so the following warning is observed on boot ...
lm90 0-004c: 0-004c supply vcc not found, using dummy regulator
On the P2888 board, the VCC supply for the temperature sensor is
connected to the 'vdd_1v8ls' rail. Add the 'vcc-supply' property for
the temperature sensor to prevent this warning message from occurring.
Fixes: 8b457812f5 ('arm64: tegra: Add temperature sensor on P2888')
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
These are currently mostly unused because we lack a proper audio driver
on Tegra210. However, enabling them makes sure that at least their probe
code paths are tested at runtime.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add L2 cache and make it the next level of cache for each of the CPUs.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable CPU idle support for Smaug platform.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable CPU idle support for Jetson TX1 platform.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
