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arm64: dts: meson-g12a: Add VPU and HDMI related nodes
Add VPU and HDMI display support. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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@ -109,6 +109,37 @@ apb: bus@ff600000 {
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
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hdmi_tx: hdmi-tx@0 {
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compatible = "amlogic,meson-g12a-dw-hdmi";
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reg = <0x0 0x0 0x0 0x10000>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
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resets = <&reset RESET_HDMITX_CAPB3>,
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<&reset RESET_HDMITX_PHY>,
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<&reset RESET_HDMITX>;
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reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
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clocks = <&clkc CLKID_HDMI>,
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<&clkc CLKID_HTX_PCLK>,
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<&clkc CLKID_VPU_INTR>;
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clock-names = "isfr", "iahb", "venci";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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/* VPU VENC Input */
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hdmi_tx_venc_port: port@0 {
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reg = <0>;
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hdmi_tx_in: endpoint {
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remote-endpoint = <&hdmi_tx_out>;
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};
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};
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/* TMDS Output */
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hdmi_tx_tmds_port: port@1 {
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reg = <1>;
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};
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};
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periphs: bus@34400 {
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compatible = "simple-bus";
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reg = <0x0 0x34400 0x0 0x400>;
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@ -138,6 +169,23 @@ gpio: bank@40 {
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gpio-ranges = <&periphs_pinctrl 0 0 86>;
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};
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hdmitx_ddc_pins: hdmitx_ddc {
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mux {
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groups = "hdmitx_sda",
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"hdmitx_sck";
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function = "hdmitx";
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bias-disable;
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};
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};
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hdmitx_hpd_pins: hdmitx_hpd {
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mux {
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groups = "hdmitx_hpd_in";
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function = "hdmitx";
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bias-disable;
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};
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};
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uart_a_pins: uart-a {
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mux {
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groups = "uart_a_tx",
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@ -195,6 +243,19 @@ usb2_phy0: phy@36000 {
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#phy-cells = <0>;
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};
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dmc: bus@38000 {
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compatible = "simple-bus";
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reg = <0x0 0x38000 0x0 0x400>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
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canvas: video-lut@48 {
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compatible = "amlogic,canvas";
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reg = <0x0 0x48 0x0 0x14>;
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};
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};
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usb2_phy1: phy@3a000 {
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compatible = "amlogic,g12a-usb2-phy";
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reg = <0x0 0x3a000 0x0 0x2000>;
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@ -262,6 +323,50 @@ clkc_AO: clock-controller {
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clock-names = "xtal", "mpeg-clk";
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};
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pwrc_vpu: power-controller-vpu {
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compatible = "amlogic,meson-g12a-pwrc-vpu";
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#power-domain-cells = <0>;
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amlogic,hhi-sysctrl = <&hhi>;
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resets = <&reset RESET_VIU>,
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<&reset RESET_VENC>,
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<&reset RESET_VCBUS>,
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<&reset RESET_BT656>,
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<&reset RESET_RDMA>,
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<&reset RESET_VENCI>,
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<&reset RESET_VENCP>,
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<&reset RESET_VDAC>,
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<&reset RESET_VDI6>,
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<&reset RESET_VENCL>,
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<&reset RESET_VID_LOCK>;
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clocks = <&clkc CLKID_VPU>,
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<&clkc CLKID_VAPB>;
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clock-names = "vpu", "vapb";
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/*
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* VPU clocking is provided by two identical clock paths
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* VPU_0 and VPU_1 muxed to a single clock by a glitch
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* free mux to safely change frequency while running.
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* Same for VAPB but with a final gate after the glitch free mux.
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*/
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assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
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<&clkc CLKID_VPU_0>,
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<&clkc CLKID_VPU>, /* Glitch free mux */
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<&clkc CLKID_VAPB_0_SEL>,
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<&clkc CLKID_VAPB_0>,
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<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
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assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
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<0>, /* Do Nothing */
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<&clkc CLKID_VPU_0>,
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<&clkc CLKID_FCLK_DIV4>,
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<0>, /* Do Nothing */
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<&clkc CLKID_VAPB_0>;
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assigned-clock-rates = <0>, /* Do Nothing */
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<666666666>,
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<0>, /* Do Nothing */
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<0>, /* Do Nothing */
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<250000000>,
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<0>; /* Do Nothing */
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};
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ao_pinctrl: pinctrl@14 {
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compatible = "amlogic,meson-g12a-aobus-pinctrl";
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#address-cells = <2>;
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@ -341,6 +446,32 @@ saradc: adc@9000 {
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};
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};
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vpu: vpu@ff900000 {
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compatible = "amlogic,meson-g12a-vpu";
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reg = <0x0 0xff900000 0x0 0x100000>,
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<0x0 0xff63c000 0x0 0x1000>;
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reg-names = "vpu", "hhi";
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interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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amlogic,canvas = <&canvas>;
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power-domains = <&pwrc_vpu>;
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/* CVBS VDAC output port */
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cvbs_vdac_port: port@0 {
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reg = <0>;
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};
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/* HDMI-TX output port */
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hdmi_tx_port: port@1 {
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reg = <1>;
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hdmi_tx_out: endpoint {
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remote-endpoint = <&hdmi_tx_in>;
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};
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};
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};
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gic: interrupt-controller@ffc01000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xffc01000 0 0x1000>,
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