GPIOs 0 through 3 and 81 through 84 are configured to not be accessible
from the application CPUs. Mark them as reserved to allow the MSM8998
MTP to boot after the introduction of 3edfb7bd76 ("gpiolib: Show
correct direction from the beginning").
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
With the introduction of commit 3edfb7bd76 ("gpiolib: Show correct
direction from the beginning") the gpiolib will attempt to read the
direction of all pins, which triggers a read from protected register
regions.
The pins 0 through 3 and 81 through 84 are protected, so mark these as
reserved.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
cbass_wakeup interconnect which is the parent of wakeup_uart node
defines address-cells=1 and size-cells=1, therefore fix up reg property
of wakeup_uart node accordingly. Otherwise, this UART instance fails to
probe if enabled.
Fixes: 4201af2544 ("arm64: dts: ti: am654: Add uart nodes")
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
rsnd driver supports SSIU now, let's use it.
Then, BUSIF DMA settings on rcar_sound,ssi (= rxu, txu) are
no longer needed.
To avoid git merge timing issue / git bisect issue,
this patch doesn't remove it so far, but will be removed in
the future.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The VIN driver bindings dictates fixed numbering for VIN endpoints connected
to CSI-2 endpoints, even when a single endpoint exists.
Without proper endpoint numbering the VIN driver fails to probe.
Based on a patch in BSP from Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Fixes: ec70407ae7 ("arm64: dts: renesas: r8a77990: Add VIN and CSI-2 device nodes")
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds SDHI{0,1,3} device nodes for the r8a77990 SoC
and enables SD card slot connected to SDHI0, micro SD card slot
connected to SDHI1 and eMMC connected to SDHI3 on the Ebisu board
using the R8A77990 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Simon Horman <horms+renesas@verge.net.au>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds pin control for SCIF2 on R8A77990 E3 Ebisu.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Merge tag 'stratix10_dts_fix_for_v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into fixes
ARM: dts: stratix10: fix multicast filtering
On Stratix 10, the EMAC has 256 hash buckets for multicast filtering. This
needs to be specified in DTS, otherwise the stmmac driver defaults to 64
buckets and initializes the filter incorrectly. As a result, e.g. valid
IPv6 multicast traffic ends up being dropped.
* tag 'stratix10_dts_fix_for_v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: stratix10: fix multicast filtering
Signed-off-by: Olof Johansson <olof@lixom.net>
Pine H64 board has HDMI type A connector.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit adds all entries needed for HDMI to function properly.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
[added DE3 bus]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The eMMC card has two supplies, VCC and VCCQ. The VCC supplies the NAND
array and the VCCQ supplies the bus. On Salvator-X and ULCB, the VCC is
connected to 3.3V rail, while the VCCQ is connected to 1.8V rail. Adjust
the pinmux to match the bus, which is always operating in 1.8V mode.
While at it, deduplicate the pinmux entries, which are now the same for
both default and UHS modes. We still need the two pinctrl entries to
match the bindings though.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add ddrc memory controller node in dts. The size mentioned in dts is
0x30000, because we need to access DDR_QOS INTR registers located at
0xFD090208 from this driver.
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Most of the legacy "gpio-key,wakeup" boolean property is already
replaced with "wakeup-source". However few occurrences of old property
has popped up again, probably from the remnants in downstream trees.
This patch replaces the legacy properties with the unified
"wakeup-source" property introduced by:
"Input: gpio_keys - switch to using generic device properties"
(sha1: 700a38b27e)
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Gru-Scarlet is a tablet device using ChomeOS, dual-dsi display
and Wacom touchscreen with stylus.
There exist two variants in the market using different displays
that are differentiated via their sku-id.
The bootloader on them also determines the correct devicetree to
load via the sku-id.
So add a common scarlet dtsi and two minimal board devicetrees
for the two display variants.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Rob Herring <robh@kernel.org>
On Stratix 10, the EMAC has 256 hash buckets for multicast filtering. This
needs to be specified in DTS, otherwise the stmmac driver defaults to 64
buckets and initializes the filter incorrectly. As a result, e.g. valid
IPv6 multicast traffic ends up being dropped.
Fixes: 78cd6a9d8e ("arm64: dts: Add base stratix 10 dtsi")
Cc: stable@vger.kernel.org
Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This patch adds the device nodes for all HSCIF serial ports to
the R8A77990 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
OrangePi Lite2 is Allwinner H6 based open-source SBC,
which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 1GB LPDDR3 RAM
- AXP805 PMIC
- AP6356S Wifi/BT
- USB 2.0, USB 3.0 Host, OTG
- HDMI port
- 5V/2A DC power supply
Signed-off-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Based on the information from hardware schematics and orangepi
vendor orangepi H6 boards, One Plus and Lite2 shares common nodes
like axp805, uart, mmc0 etc. The common differences between them is
- One Plus, has Ethernet
- Lite2, has Wifi, USB3, CSI port.
So, add common orangepi nodes into sun50i-h6-orangepi.dtsi so-that
it case use on respective orangepi h6 board dts files.
Cc: zhaoyifan <zhao_steven@263.net>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Describe TMUs in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch enables Audio for the Ebisu board on R8A77990 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: rebased]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds Audio-DMAC0 device node and Sound device node
for the R8A77990 SoC.
Based on work by Takeshi Kihara and Hai Nguyen Pham.
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
[simon: dropped include update, which is already present]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds/enables USB2.0 peripheral for R-Car [DE]3 boards.
R-Car E3 Ebisu board connects the ID pin to the SoC, so this adds
a group "usb0_id" into usb0_pins node. Also, to use SW15 pin 3 side,
this patch adds vbus0_usb2 node on r8a77990-ebisu.dts.
R-Car D3 Draak board doesn't connect the ID pin, so this adds
"renesas,no-otg-pins" property into usb2_phy0 node.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds a property "companion" with xhci0 phandle to
the usb3_peri0 node in salvator-common.dtsi.
About the detail of this property for renesas_usb3 udc driver, please
refer to the commit 39facfa01c ("usb: gadget: udc: renesas_usb3:
Add register of usb role switch").
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Hook up the R-Car E3 AVB device to IPMMU-DS0 16 as described in
the data sheet.
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Hook up the R-Car V3H AVB device to IPMMU-DS1 33 as described in
the data sheet.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Hook up the R-Car M3-N AVB device to IPMMU-DS0 16 as described in
the data sheet.
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The "official" Condor boards have always been wired to mount NFS via
GEther, not EtherAVB -- the boards resoldered for EtherAVB were local
to Cogent Embedded, so we've been having an unpleasant situation where
a "normal" Condor board still can't mount NFS (unless an EtherAVB PHY
extension board is plugged in). Switch from EtherAVB to GEther at last!
Fixes: 8091788f3d ("arm64: dts: renesas: condor: add EtherAVB support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
hscif2 has 4 dmas, but has only 2 dma-names.
This patch add missing dma-names.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Fixes: e0f0bda793 ("arm64: dts: renesas: r8a7795: sort subnodes
of the soc node")
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds the device nodes for SCIF-{0,1,3,4,5} serial ports to
the R8A77990 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe MSIOF in the R8A779{7|8}0 device trees.
The DMA props are omitted for R8A77980 as the RT-DMAC isn't supported
(yet?)...
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The M3-N (r8a77965) platform has one LVDS encoder connected to the DU.
Add the corresponding DT node and wire it up.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe THS/CIVM in the R8A77980 device trees.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe THS/CIVM in the R8A77970 device tree.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe PWMs in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds a device node for the Interrupt Controller for External
Devices (INTC-EX) on R-Car E3, which serves external IRQ pins IRQ[0-5].
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
commit 2d87dc0e5b ("arm64: dts: renesas: r8a7795: Add address
properties to rcar_sound port nodes") added missing #address-cells
and #size-cells for sound ports.
But, these are based on platform, not on SoC. This patch cleanups it.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device nodes for both RZ/G2M CAN channels.
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Pine H64 board has an Ethernet port, which is connected to a
RTL8211E PHY, then the PHY is connected to the MAC on H6 SoC.
Add support for the Ethernet port.
The PHY needs some time to start up, and the time is modelled as enable
ramp delay of the regulator.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Allwinner H6 SoC has an EMAC like the one in A64.
Add device tree nodes for the H6 DTSI file.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Emlid Neutis N5 is a SoM based on Allwinner H5, has a WiFi & BT
module, DDR3 RAM and eMMC.
- add neutis n5 dtsi file for SoM needs
- add neutis devboard dts file
- add neutis devboard target to dtb makefile
Signed-off-by: Aleksandr Aleksandrov <aleksandr.aleksandrov@emlid.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Backlight power is controlled by PH6 GPIO, so add corresponding
regulator-fixed node for it. Otherwise backlight won't light up
if bootloader doesn't enable it.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The backlight is for the eDP panel and it has the connector on the excavator baseboard.
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
After commit 88ba95bedb ("backlight: pwm_bl: Compute brightness of LED
linearly to human eye") the pwm_bl driver is able to calculate a default
brightness table. The calculated table for this PWM will have more
granularity and will be adjusted to change the brightness linearly to
the human eye. Use that table instead of have a DT-defined table with
less granularity.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
In order to use earlycon, the stdout-path property needs to be set
in the chosen node.
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
eMMC that's sold by Pine64 can do HS200, rk3328 can do it
as well, so update DTS to enable it.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Sapphire board has a 12V fan. So, adding it to the DTS.
There is no power supply directly connected, it needs the baseboard to
work.
If the board is used standalone then a hardware modification is needed.
On the Sapphire board there is an unpopulated resistor to connect it to
VBUS_TYPEC, which is usually 5V (too low) and can range up to 20V
(too high).
I tested it for a week connected to VCC_SYS which is 8.4V and proved to
be more than enough for the required cooling needs. This is the
connection described in the comment.
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add spi dma channels as specified by the rk3399 TRM.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
When the performance governor is set as default, the rock960 hangs
around one minute after booting, whatever the activity is (idle, key
pressed, loaded, ...).
Based on the commit log found at https://patchwork.kernel.org/patch/10092377/
"vdd_log has no consumer and therefore will not be set to a specific
voltage. Still the PWM output pin gets configured and thence the vdd_log
output voltage will changed from it's default. Depending on the idle
state of the PWM this will slightly over or undervoltage the logic supply
of the RK3399 and cause instability with GbE (undervoltage) and PCIe
(overvoltage). Since the default value set by a voltage divider is the
correct supply voltage and we don't need to change it during runtime we
remove the rail from the devicetree completely so the PWM pin will not
be configured."
After removing the vdd-log from the rock960's specific DT, the board
does no longer hang and shows a stable behavior.
Apply the same change for the rock960 by removing the vdd-log from the
DT.
Fixes: 874846f1fc ("arm64: dts: rockchip: add 96boards RK3399 Ficus board")
Cc: stable@vger.kernel.org
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The LX2160A QorIQ Development System (QDS) is a test, evaluation, and
development platform, supporting QorIQ LX2160A processor.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
There are close to 800 indivudal changesets in this branch again, which
feels like a lot. There are particularly many changes for the NVIDIA
Tegra platform this time, in fact more than it has seen in the two years
since the v4.9 merge window. Aside from this, it's been fairly normal,
with lots of changes going into Renesas R-CAR, NXP i.MX, Allwinner Sunxi,
Samsung Exynos, and TI OMAP.
Most of the changes are for adding new features into existing boards,
for brevity I'm only mentioning completely new machines and SoCs here.
For the first time I think we have (slightly) more new 64-bit hardware
than 32-bit:
Two boards get added for TI OMAP: Moxa UC-2101 is an industrial
computer, see https://www.moxa.com/product/UC-2100.htm; GTA04A5
is a minor variation of the motherboards of the GTA04 phone, see
https://shop.goldelico.com/wiki.php?page=GTA04A5
Clearfog is a nice little board for quad-core
Marvell Armada 8040 network processor, see
https://www.solid-run.com/marvell-armada-family/clearfog-gt-8k/
Two additional server boards come with the Aspeed baseboard management
controllers: Stardragon4800 is an arm64 reference platform made by HXT
(based on Qualcomm's server chips), and TiogaPass is an Open Compute
mainboard with x86 CPUs. Both use the ARM11 based AST2500 chips in
the BMC.
NXP i.MX usually sees a lot of new boards each release. This time there
we only add one minor variant: ConnectCore 6UL SBC Pro uses the same
SoM design as the ConnectCore 6UL SBC Express added later. However,
there is a new chip, the i.MX6ULZ, which is an even smaller variant
of the i.MX6ULL, with features removed. There is also support for the
reference board design, the i.MX6ULZ 14x14 EVK.
A new Raspberry Pi variant gets added, this one is the CM3 compute module
based on bcm2837, it was launched in early 2017 but only now added to
the kernel, both as 32-bit and as 64-bit files, as we tend to do for
Raspberry Pi.
On the Allwinner side, everything is again about cheap development
boards, usually of the "Fruit Pi" variety. The new ones this time
are:
Orange Pi Zero Plus2: http://www.orangepi.org/OrangePiZeroPlus2/
Orange Pi One Plus: http://www.orangepi.org/OrangePiOneplus/
Pine64 LTS: https://www.pine64.org/?product=pine-a64-lts
Banana Pi M2+ H5: http://www.banana-pi.org/m2plus.html
The last one of these is now a 64-bit version of the earlier Banana
Pi M2+ H3, with the same board layout.
Similarly, for Rockchips, get get another variant of the 32-bit
Asus Tinker board, the model 'S' based on rk3288, and three now
boards based on the popular RK3399 chip:
ROC-RK3399-PC: https://libre.computer/products/boards/roc-rk3399-pc/
Rock960: https://www.96boards.org/product/rock960/
RockPro64: https://www.pine64.org/?page_id=61454
These are all quite powerful boards with lots of RAM and I/O, and
the RK3399 is the same chip used in several Chromebooks. Finally,
we get support for the PX30 (aka rk3326) chip, which is based on the
low-end 64-bit Cortex-A35 CPU core. So far, only the evaluation board
is supported.
One more Banana Pi is added with a Mediatek chip: Banana Pi R64 is based
on the MT7622 WiFi router platform, and the first product I've seen with
a 64-bit Mediatek chip in that market: http://www.banana-pi.org/r64.html
For HiSilicon, we gain support for the Hi3670 SoC and HiKey 370
development board, which are similar to the Hi3660 and Hikey 360
respectively, but add support for an NPU.
Amlogic gets initial support for the Meson-G12A chip (S905D2),
another quad-core Cortex-A53 SoC, and its evaluation platform.
On the 32-bit side, we gain support for an actual end-user product,
the Endless Computers Endless Mini based on Meson8b (S805), see
https://endlessos.com/computers/
Qualcomm adds support for their MSM8998 SoC and evaluation platform. This
chip is commonly known as the Snapdragon 835, and is used in high-end
phones as well as low-end laptops.
For Renesas, a very bare support for the r8a774a1 (RZ/G2M) is added,
but no boards for this one. However, we do add boards for the previously
added r8a77965 (R-Car M3-N): the M3NULCB Kingfisher and the M3NULCB
Starter Kit Pro.
While we have lots of DT changes for NVIDIA to update the existing files,
the only board that gets added is the Toradex Colibri T20 on Colibri
Evaluation Board for the old Tegra2.
Synaptics add support for their AS370 SoC, which is part of the (formerly
Marvell) Berlin line of set-top-box chips used e.g. in the various Google
Chromecast. Only the .dtsi gets added at this point, no actual machines.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree updates from Arnd Bergmann:
"There are close to 800 indivudal changesets in this branch again,
which feels like a lot. There are particularly many changes for the
NVIDIA Tegra platform this time, in fact more than it has seen in the
two years since the v4.9 merge window. Aside from this, it's been
fairly normal, with lots of changes going into Renesas R-CAR, NXP
i.MX, Allwinner Sunxi, Samsung Exynos, and TI OMAP.
Most of the changes are for adding new features into existing boards,
for brevity I'm only mentioning completely new machines and SoCs here.
For the first time I think we have (slightly) more new 64-bit hardware
than 32-bit:
Two boards get added for TI OMAP: Moxa UC-2101 is an industrial
computer, see https://www.moxa.com/product/UC-2100.htm; GTA04A5 is a
minor variation of the motherboards of the GTA04 phone, see
https://shop.goldelico.com/wiki.php?page=GTA04A5
Clearfog is a nice little board for quad-core Marvell Armada 8040
network processor, see
https://www.solid-run.com/marvell-armada-family/clearfog-gt-8k/
Two additional server boards come with the Aspeed baseboard management
controllers: Stardragon4800 is an arm64 reference platform made by HXT
(based on Qualcomm's server chips), and TiogaPass is an Open Compute
mainboard with x86 CPUs. Both use the ARM11 based AST2500 chips in the
BMC.
NXP i.MX usually sees a lot of new boards each release. This time
there we only add one minor variant: ConnectCore 6UL SBC Pro uses the
same SoM design as the ConnectCore 6UL SBC Express added later.
However, there is a new chip, the i.MX6ULZ, which is an even smaller
variant of the i.MX6ULL, with features removed. There is also support
for the reference board design, the i.MX6ULZ 14x14 EVK.
A new Raspberry Pi variant gets added, this one is the CM3 compute
module based on bcm2837, it was launched in early 2017 but only now
added to the kernel, both as 32-bit and as 64-bit files, as we tend to
do for Raspberry Pi.
On the Allwinner side, everything is again about cheap development
boards, usually of the "Fruit Pi" variety. The new ones this time are:
- Orange Pi Zero Plus2: http://www.orangepi.org/OrangePiZeroPlus2/
- Orange Pi One Plus: http://www.orangepi.org/OrangePiOneplus/
- Pine64 LTS: https://www.pine64.org/?product=pine-a64-lts
- Banana Pi M2+ H5: http://www.banana-pi.org/m2plus.html
The last one of these is now a 64-bit version of the earlier Banana Pi
M2+ H3, with the same board layout.
Similarly, for Rockchips, get get another variant of the 32-bit Asus
Tinker board, the model 'S' based on rk3288, and three now boards
based on the popular RK3399 chip:
- ROC-RK3399-PC: https://libre.computer/products/boards/roc-rk3399-pc/
- Rock960: https://www.96boards.org/product/rock960/
- RockPro64: https://www.pine64.org/?page_id=61454
These are all quite powerful boards with lots of RAM and I/O, and the
RK3399 is the same chip used in several Chromebooks. Finally, we get
support for the PX30 (aka rk3326) chip, which is based on the low-end
64-bit Cortex-A35 CPU core. So far, only the evaluation board is
supported.
One more Banana Pi is added with a Mediatek chip: Banana Pi R64 is
based on the MT7622 WiFi router platform, and the first product I've
seen with a 64-bit Mediatek chip in that market:
http://www.banana-pi.org/r64.html
For HiSilicon, we gain support for the Hi3670 SoC and HiKey 370
development board, which are similar to the Hi3660 and Hikey 360
respectively, but add support for an NPU.
Amlogic gets initial support for the Meson-G12A chip (S905D2), another
quad-core Cortex-A53 SoC, and its evaluation platform. On the 32-bit
side, we gain support for an actual end-user product, the Endless
Computers Endless Mini based on Meson8b (S805), see
https://endlessos.com/computers/
Qualcomm adds support for their MSM8998 SoC and evaluation platform.
This chip is commonly known as the Snapdragon 835, and is used in
high-end phones as well as low-end laptops.
For Renesas, a very bare support for the r8a774a1 (RZ/G2M) is added,
but no boards for this one. However, we do add boards for the
previously added r8a77965 (R-Car M3-N): the M3NULCB Kingfisher and the
M3NULCB Starter Kit Pro.
While we have lots of DT changes for NVIDIA to update the existing
files, the only board that gets added is the Toradex Colibri T20 on
Colibri Evaluation Board for the old Tegra2.
Synaptics add support for their AS370 SoC, which is part of the
(formerly Marvell) Berlin line of set-top-box chips used e.g. in the
various Google Chromecast. Only the .dtsi gets added at this point, no
actual machines"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (721 commits)
ARM: dts: socfgpa: remove ethernet aliases from dtsi
arm64: dts: stratix10: add ethernet aliases
dt-bindings: mediatek: Add bindig for MT7623 IOMMU and SMI
dt-bindings: mediatek: Add JPEG Decoder binding for MT7623
dt-bindings: iommu: mediatek: Add binding for MT7623
dt-bindings: clock: mediatek: add support for MT7623
ARM: dts: mvebu: armada-385-db-88f6820-amc: auto-detect nand ECC properites
ARM: dts: da850-lego-ev3: slow down A/DC as much as possible
ARM: dts: da850-evm: Enable tca6416 on baseboard
arm64: dts: uniphier: Add USB2 PHY nodes
arm64: dts: uniphier: Add USB3 controller nodes
ARM: dts: uniphier: Add USB2 PHY nodes
ARM: dts: uniphier: Add USB3 controller nodes
arm64: dts: meson-axg: s400: disable emmc
arm64: dts: meson-axg: s400: add missing emmc pwrseq
arm64: dts: clearfog-gt-8k: add PCIe slot description
ARM: dts: at91: sama5d4_xplained: even nand memory partitions
ARM: dts: at91: sama5d3_xplained: even nand memory partitions
ARM: dts: at91: at91sam9x5cm: even nand memory partitions
ARM: dts: at91: sama5d2_ptc_ek: fix bootloader env offsets
...
These updates bring:
- Debugfs support for the Intel VT-d driver. When enabled, it
now also exposes some of its internal data structures to
user-space for debugging purposes.
- ARM-SMMU driver now uses the generic deferred flushing
and fast-path iova allocation code. This is expected to be a
major performance improvement, as this allocation path scales
a lot better.
- Support for r8a7744 in the Renesas iommu driver
- Couple of minor fixes and improvements all over the place
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Merge tag 'iommu-updates-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU updates from Joerg Roedel:
- Debugfs support for the Intel VT-d driver.
When enabled, it now also exposes some of its internal data
structures to user-space for debugging purposes.
- ARM-SMMU driver now uses the generic deferred flushing and fast-path
iova allocation code.
This is expected to be a major performance improvement, as this
allocation path scales a lot better.
- Support for r8a7744 in the Renesas iommu driver
- Couple of minor fixes and improvements all over the place
* tag 'iommu-updates-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (39 commits)
iommu/arm-smmu-v3: Remove unnecessary wrapper function
iommu/arm-smmu-v3: Add SPDX header
iommu/amd: Add default branch in amd_iommu_capable()
dt-bindings: iommu: ipmmu-vmsa: Add r8a7744 support
iommu/amd: Move iommu_init_pci() to .init section
iommu/arm-smmu: Support non-strict mode
iommu/io-pgtable-arm-v7s: Add support for non-strict mode
iommu/arm-smmu-v3: Add support for non-strict mode
iommu/io-pgtable-arm: Add support for non-strict mode
iommu: Add "iommu.strict" command line option
iommu/dma: Add support for non-strict mode
iommu/arm-smmu: Ensure that page-table updates are visible before TLBI
iommu/arm-smmu-v3: Implement flush_iotlb_all hook
iommu/arm-smmu-v3: Avoid back-to-back CMD_SYNC operations
iommu/arm-smmu-v3: Fix unexpected CMD_SYNC timeout
iommu/io-pgtable-arm: Fix race handling in split_blk_unmap()
iommu/arm-smmu-v3: Fix a couple of minor comment typos
iommu: Fix a typo
iommu: Remove .domain_{get,set}_windows
iommu: Tidy up window attributes
...
Hygon Dhyana support (Pu Wen)
- sb_edac: New maintainer + fixes (Tony Luck)
Error reporting improvements and fixes (Qiuxu Zhuo)
- ghes_edac: SMBIOS handle type 17 for DIMM locating and per-DIMM error
accounting (Fan Wu)
- altera_edac: Stratix10 support and refactoring (Thor Thayer)
Out of tree addition:
- acpi_adxl: Address Translation interface using an ACPI DSM (Tony Luck)
- the usual amount of other misc fixes and cleanups all over.
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Merge tag 'edac_for_4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
Pull EDAC updates from Borislav Petkov:
"The EDAC tree was busier than usual this cycle as the shortlog below
shows.
Also, this pull request is carrying an ACPI DSM driver which is used
to ask the platform to supply the DIMM location of a reported hardware
error and thus simplify all the EDAC logic when trying to map the
error address to the respective DIMM.
Core EDAC updates:
- amd64_edac: AMD family 0x17, models 0x10-0x2f support (Michael Jin)
Hygon Dhyana support (Pu Wen)
- sb_edac: New maintainer + fixes (Tony Luck) Error reporting
improvements and fixes (Qiuxu Zhuo)
- ghes_edac: SMBIOS handle type 17 for DIMM locating and per-DIMM
error accounting (Fan Wu)
- altera_edac: Stratix10 support and refactoring (Thor Thayer)
Out of tree addition:
- acpi_adxl: Address Translation interface using an ACPI DSM (Tony
Luck)
- the usual amount of other misc fixes and cleanups all over"
* tag 'edac_for_4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: (22 commits)
ACPI/ADXL: Add address translation interface using an ACPI DSM
EDAC, thunderx: Fix memory leak in thunderx_l2c_threaded_isr()
EDAC, skx_edac: Fix logical channel intermediate decoding
EDAC, {i7core,sb,skx}_edac: Fix uncorrected error counting
EDAC, altera: Work around int-to-pointer-cast warnings
EDAC, amd64: Add Hygon Dhyana support
EDAC: Raise the maximum number of memory controllers
arm64: dts: stratix10: Add peripheral EDAC nodes
EDAC, altera: Add Stratix10 peripheral support
EDAC, altera: Merge Stratix10 into the Arria10 SDRAM probe routine
arm64: dts: stratix10: Add SDRAM node
EDAC, altera: Combine Stratix10 and Arria10 probe functions
arm64: dts: stratix10: Additions to EDAC System Manager
EDAC, i7core: Remove set but not used variable pvt
EDAC, ghes: Use CPER module handles to locate DIMMs
EDAC: Correct DIMM capacity unit symbol
EDAC, sb_edac: Fix signedness bugs in *_get_ha() functions
EDAC, sb_edac: Fix reporting for patrol scrubber errors
EDAC, sb_edac: Return early on ADDRV bit and address type test
MAINTAINERS: Update maintainer for drivers/edac/sb_edac.c
...
Properly specify the RX and TX FIFO size which is important
for Jumbo frames.
Update the max-frame-size to support Jumbo frames.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
- Add System Error Interrupt support to Armada SoCs (7K/8K)
- Add CPU idle support on Armada 8K
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Merge tag 'mvebu-dt64-4.20-2' of git://git.infradead.org/linux-mvebu into next/dt
mvebu dt64 for 4.20 (part 2)
- Add System Error Interrupt support to Armada SoCs (7K/8K)
- Add CPU idle support on Armada 8K
* tag 'mvebu-dt64-4.20-2' of git://git.infradead.org/linux-mvebu:
arm64: dts: clearfog-gt-8k: add PCIe slot description
arm64: dts: marvell: add CP110 ICU SEI subnode
arm64: dts: marvell: use new bindings for CP110 interrupts
arm64: dts: marvell: add AP806 SEI subnode
arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8K
arm64: dts: marvell: Add node labels for the cpus
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
as the Vamrs Rock960. Another big feature is display support including hdmi
and the Innosilicon hdmiphy on the rk3328, right now enabled on the rock64.
The rock64 also got its spi-nor and spdif enabled. On the px30 we can see
dwc2-based usb support now and finally some misc fixes, like for a new dtc
warning, missing address and size cells and microSD fix on sapphire.
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Merge tag 'v4.20-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Some additional new boards, the rk3399-based RockPro64 from Pine64, as well
as the Vamrs Rock960. Another big feature is display support including hdmi
and the Innosilicon hdmiphy on the rk3328, right now enabled on the rock64.
The rock64 also got its spi-nor and spdif enabled. On the px30 we can see
dwc2-based usb support now and finally some misc fixes, like for a new dtc
warning, missing address and size cells and microSD fix on sapphire.
* tag 'v4.20-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: enable display nodes on rk3328-rock64
arm64: dts: rockchip: add rk3328 display nodes
arm64: dts: rockchip: add Innosilicon hdmi phy node to rk3328
arm64: dts: rockchip: add missing address and size cells for rk3399 mipi dsi
arm64: dts: rockchip: Enable SPI NOR flash on Rock64
arm64: dts: rockchip: add initial dts support for Rockpro64
arm64: dts: rockchip: enable dwc2-based otg controller on px30-evb
arm64: dts: rockchip: add dwc2 otg controller on px30
dt-bindings: usb: dwc2: add description for px30
arm64: dts: rockchip: Enable SD card detection for Rock960 boards
arm64: dts: rockchip: Add support for Rock960 board
dt-bindings: arm: rockchip: Add binding for Rock960 board
arm64: dts: rockchip: Split out common nodes for Rock960 based boards
arm64: dts: rockchip: add spdif sound node for rock64
arm64: dts: rockchip: Fix microSD in rk3399 sapphire board
arm64: dts: rockchip: Fix I2C bus unit-address error on rk3399-puma-haikou
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add USB3 controller nodes including usb-core, resets, regulator, ss-phy
and hs-phy. This supports for LD20, PXs3 and the boards. This includes
additional efuse nodes for obtaining PHY trimming values.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
While it is possible to rework the s400 board to solder an eMMC on it,
it is not the default option and most boards are fitted with a NAND
instead.
Let's disable the emmc device by default to reflect this. The board
equipped with an eMMC will just have to alter the DT in the
bootloader, like we do for the reserved memory regions.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
eMMC pwrseq is defined in the s400 dts but not used in the emmc node.
This is probably just a copy/paste error
Fixes: 221cf34bac ("ARM64: dts: meson-axg: enable the eMMC controller")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This adds support for the PCIe interface on the CON4 mini-PCIe
connector.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The ICU handles several interrupt groups, each of them being a subpart
of the ICU node.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Create an ICU subnode for the NSR interrupts. This subnode becomes the
CP110 interrupt parent, removing the need for the ICU_GRP_NSR parameter.
Move all DT110 nodes to use these new bindings.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add SD controller nodes for LD20 and PXs3.
LD20 does not support the UHS mode, while PXs3 supports it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add the System Error Interrupt node, representing an IRQ chip which is
part of the GIC. The SEI node aggregates interrupts from the AP through
wired interrupts, and from the CPs through MSIs.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This patch adds CPU deep Idle and Cluster deep Idle states BUT it defines
the idle state for each cpu (defined under cpu-idle-states parameter)
only for the quad version therefore it does NOT activate CPU Idle
capability for the other version.
[gregory: extract from a larger patch]
Signed-off-by: orenbh <orenbh@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Aligned with what we have done for the others nodes. It will also allow
to easily modify the cpu configuration at board (or sub-SoC) level.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
- Add watchdog node on Armada 37xx
- Update PPv2 interrupts name
- Add support for the SolidRun Clearfog GT 8K (Aramda 8040 based)
- Add thermal-zone nodes for Aramda 7K/8K
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Merge tag 'mvebu-dt64-4.20-1' of git://git.infradead.org/linux-mvebu into next/dt
mvebu dt64 for 4.20 (part 1)
- Add watchdog node on Armada 37xx
- Update PPv2 interrupts name
- Add support for the SolidRun Clearfog GT 8K (Aramda 8040 based)
- Add thermal-zone nodes for Aramda 7K/8K
* tag 'mvebu-dt64-4.20-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: armada-37xx: add nodes to support watchdog
arm64: dts: marvell: armada-cp110: describe more PPv2 interrupts
arm64: dts: marvell: armada-cp110: change the PPv2 IRQ names
arm64: dts: add support for SolidRun Clearfog GT 8K
arm64: dts: marvell: add thermal-zone node in cp110 DTSI file
arm64: dts: marvell: add macro to make distinction between node names
arm64: dts: marvell: add thermal-zone node in ap806 DTSI file
arm64: dts: marvell: move AP806/CP110 thermal nodes into a new syscon
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add the second Dual UART device for LS208xA SoCs.
- Add necessary big-endian property for NOR device on LS104xA based
boards, remove unneeded big-endian property from IFC controller.
- DTC has new checks for I2C and SPI buses to land into 4.20. A patch
from Rob to fix the bus node names and warnings in unit-addresses.
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Merge tag 'imx-dt64-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
Freescale arm64 device tree update for 4.20:
- Add the second Dual UART device for LS208xA SoCs.
- Add necessary big-endian property for NOR device on LS104xA based
boards, remove unneeded big-endian property from IFC controller.
- DTC has new checks for I2C and SPI buses to land into 4.20. A patch
from Rob to fix the bus node names and warnings in unit-addresses.
* tag 'imx-dt64-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: fsl: Fix I2C and SPI bus warnings
arm64: dts: ls208xa: add second duart
arm64: dts: fsl: remove big-endian field from IFC controller
arm64: dts: Add big-endian in nor node for ls104xa
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Our usual set of DT changes for the arm64 Allwinner SoCs.
The most notable things are:
- HDMI support on the A64
- New boards: OrangePi One Plus
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Merge tag 'sunxi-dt64-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Allwinner arm64 DT changes for 4.20
Our usual set of DT changes for the arm64 Allwinner SoCs.
The most notable things are:
- HDMI support on the A64
- New boards: OrangePi One Plus
* tag 'sunxi-dt64-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (28 commits)
arm64: dts: allwinner: a64: a64-olinuxino: set the PHY TX delay
arm64: dts: allwinner: a64: Enable HDMI output on A64 boards w/ HDMI
arm64: dts: allwinner: a64: Add display pipeline
arm64: dts: allwinner: h6: add system controller device tree node
arm64: dts: allwinner: h6: Add OrangePi One Plus initial support
arm64: dts: allwinner: a64: Rename r_i2c_pins_a label to r_i2c_pl89_pins
arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins
arm64: dts: allwinner: a64: Split out data strobe pin from mmc2 pinmux
arm64: dts: allwinner: a64: NanoPi-A64: Add blue status LED
arm64: dts: allwinner: a64: NanoPi-A64: Add Wifi chip
arm64: dts: allwinner: a64: NanoPi-A64: Add Ethernet
arm64: dts: allwinner: a64: NanoPi-A64: Fix DCDC1 voltage
arm64: dts: allwinner: a64: Olinuxino: enable USB
arm64: dts: allwinner: a64: Olinuxino: add Ethernet nodes
arm64: dts: allwinner: a64: Olinuxino: fix DRAM voltage
arm64: dts: allwinner: a64: Orange Pi Win: Adjust CSI power rails
arm64: dts: allwinner: a64: Orange Pi Win: Add SPI flash node
arm64: dts: allwinner: a64: Orange Pi Win: Add SDIO node
arm64: dts: allwinner: a64: Orange Pi Win: Add LED node
arm64: dts: allwinner: a64: Orange Pi Win: Add UARTs
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This is our usual H3/H5 pull request
The most notable changes are:
- the video decoding / encoding unit is finally enabled on the H3
- Mali support for the H5
- New boards: BananaPi M2+ v1.2, Orange Pi Zero Plus 2 H3 support
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Merge tag 'sunxi-h3-h5-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Allwinner H3 and H5 DT additions for 4.20
This is our usual H3/H5 pull request
The most notable changes are:
- the video decoding / encoding unit is finally enabled on the H3
- Mali support for the H5
- New boards: BananaPi M2+ v1.2, Orange Pi Zero Plus 2 H3 support
* tag 'sunxi-h3-h5-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device trees
ARM: dts: sun8i-h3: Add Video Engine and reserved memory nodes
arm64: dts: allwinner: h5: Add device tree for Bananapi M2 Plus H5
ARM: dts: sun8i: h3: Split out non-SoC-specific parts of Bananapi M2 Plus
ARM: dts: sun8i: h3: bpi-m2-plus: Fix address for external RGMII Ethernet PHY
ARM: dts: sun8i: h3-h5: ir register size should be the whole memory block
arm64: dts: allwinner: h5: Add device node for Mali-450 GPU
ARM: dts: sun8i: Add initial Orangepi Zero Plus 2 H3 support
nvmem: sunxi-sid: add support for H5's SID controller
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Remove fixed clock in Cubieboard 7 and use Clock Management Unit clocks
for all UART nodes in Actions Semi S700 SoC.
Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Signed-off-by: Saravanan Sekar <sravanhome@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[AF: Moved/added to SoC]
Signed-off-by: Andreas Färber <afaerber@suse.de>
Add pinctrl definitions for Actions Semiconductor S900 I2C controllers.
Pinctrl definitions are only available for I2C0, I2C1, and I2C2.
Enable I2C1 and I2C2 exposed on the low speed expansion connector in
Bubblegum-96 board.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[AF: Squashed]
Signed-off-by: Andreas Färber <afaerber@suse.de>
Bananapi released an updated revision of the H3/H5 based Bananapi M2+.
Version 1.2 enables voltage control for the CPU's regulator by using
a GPIO line to toggle a MOSFET that can change the effective resistance
value in the regulator's feedback network.
This patch adds a common .dtsi file for this new revision, which
includes the original common sunxi-bananapi-m2-plus.dtsi file, and
adds the GPIO-controlled regulator and a cpu-supply reference. H3
and H5 variant dts files are added as well.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The Bananapi M2 Plus H5 is a variant of the original Bananapi M2 Plus,
with the H3 SoC replaced with an H5. Everything else is the same.
Add a stub device tree incorporating the shared bananapi-m2-plus dtsi
file.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The H5 has a Mali-450 GPU with 4 Pixel Processor cores.
Interestingly, while the datasheet lists an interrupt line for the GPU's
PMU, the hardware block itself doesn't seem to have it. Reads from the
PMU address range all return zero, and writes are ignored.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This contains mostly device tree changes to support faster SDHCI modes
on Tegra210 and Tegra186.
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Merge tag 'tegra-for-4.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
arm64: tegra: Device tree changes for v4.20-rc1
This contains mostly device tree changes to support faster SDHCI modes
on Tegra210 and Tegra186.
* tag 'tegra-for-4.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: I2C on Tegra194 is not compatible with Tegra114
arm64: dts: tegra186: Enable HS400
arm64: dts: tegra210: Enable HS400
arm64: dts: tegra186: Add SDMMC4 DQS trim value
arm64: dts: tegra210: Add SDMMC4 DQS trim value
arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4
arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4
arm64: dts: tegra186: Add SDHCI tap and trim values
arm64: dts: tegra210: Add SDHCI tap and trim values
arm64: dts: tegra186: Add sdmmc pad auto calibration offsets
arm64: dts: tegra210: Add sdmmc pad auto calibration offsets
arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1
arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply
arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V
arm64: dts: Add Tegra186 sdmmc pinctrl voltage states
arm64: dts: Add Tegra210 sdmmc pinctrl voltage states
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add the chain of display nodes from the core display-subsystem
through the one vop to the dw-hdmi output.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Robin Murphy <robin.murphy@arm.com>
changes in v3:
- drop reg from hdmi-in-port
changes in v2:
- remove trailing 0 from vop irq
The rk3328 uses a hdmiphy from Innosilicon, so add the necessary node
to the rk3328 soc devicetree.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Robin Murphy <robin.murphy@arm.com>
- new SoC support: basic support for G12A family
- new board: Amlogic U200 board, using G12A SoC
- fix SPI bus warnings from new dtc updates
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Merge tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt
Amlogic ARM64 DT updates for v4.20, round 2
- new SoC support: basic support for G12A family
- new board: Amlogic U200 board, using G12A SoC
- fix SPI bus warnings from new dtc updates
* tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support
dt-bindings: arm: amlogic: Add Meson G12A binding
arm64: dts: meson: Fix erroneous SPI bus warnings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
SPI controller nodes should be named 'spi' rather than 'ssp'. Fixing the
name enables dtc SPI bus checks.
Cc: Chanho Min <chanho.min@lge.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
dtc has new checks for SPI buses. Fix the warnings in node names.
arch/arm64/boot/dts/amd/amd-overdrive.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'
arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'
arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'
Cc: Brijesh Singh <brijeshkumar.singh@amd.com>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds the system controller node for CPU Miscellaneous Registers
(which is needed for the watchdog node) and the watchdog node.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The PHY found on the A64-OLinuXino requires a TX delay in order to
operate properly. Olimex uses a 600ps second delay in their BSP, and
that has been found to work, so let's use that value in the current
DT.
Signed-off-by: Rodrigo Exterckötter Tjäder <rodrigo@tjader.xyz>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Switch to updated coresight bindings for hw ports
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Tegra194 contains a version of the I2C controller that is no longer
compatible with the version found in Tegra114.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This patch describes 3 additional interrupts per PPv2 port. Those
interrupts will be used later in future versions of the Marvell PPv2
driver, and now the device tree description matches the hardware
capabilities.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This patch changes the PPv2 IRQ names in the CP110 device tree to match
a corresponding change in the Marvell PPv2 driver. The reason this was
updated is the IRQ where names after Tx/Rx interrupts, but this is not
true and can be configured. A following patch will add more of them and
the names wouldn't make sense.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The SolidRun Clearfog GT-8K is based on Marvell Armada 8040 SoC.
https://wiki.solid-run.com/doku.php?id=products:a8040:clearfoggt8k
The following devices were tested with this DT on top of kernel
v4.19-rc4:
* 1GB Ethernet WAN
* 4 ports 1GB Ethernet switch (2.5GB uplink)
* SFP port
* SATA on CON3 PCIe slot
* USB3 type A port
* SD card and eMMC
* 2 LEDs
* 2 push buttons
[gregory: fix block comment alignement]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
DSI controllers are also the hosts of their dsi bus and therefore contain
nodes describing the attached panels with their reg properties containing
the virtual ids.
The dsi controller nodes on rk3399 lacked the #address-cells and #size-cells
for these subnodes, so add them.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Pine64 Rock64 board comes with a GigaDevice GD25Q128CSIG
or GD25Q127CSIG chip, which is a 128 Mbit SPI NOR flash chip
that supports the JEDEC read-ID command.
This patch enables the SPI controller and adds a device node
for the flash chip using the generic "jedec,spi-nor" comaptible.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Rockpro64 is a rockchip RK3399 based board from pine64.org.
This patch adds basic device node support for Rockpro64 board and make it able
to bring up.
Peripheral Works
- Sdcard
- USB 2.0, 3.0
- Leds
- Ethernet
- Debug console
Not working:
- USB Type-C
Signed-off-by: Akash Gajjar <Akash_Gajjar@mentor.com>
Acked-by: Deepak Das <Deepak_Das@mentor.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Based on a similar patch of the R8A7796 device tree
by Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Adds LVDS decoder, HDMI encoder and connector for the Draak board.
The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and
EXTAL externals clocks. Two of them are provided to the SoC on the Draak
board, hook them up in DT.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the LVDS decoder, HDMI encoder, VGA encoder and HDMI and VGA
connectors, and wire up the display-related nodes with clocks, pinmux
and regulators.
The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and
EXTAL externals clocks. Two of them are provided to the SoC on the Ebisu
board, hook them up in DT.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
[uli: moved lvds* into the soc node, added PM domains, resets]
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Try to add basic DT support for the Amlogic's Meson-G12A S905D2 SoC,
which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
dtc has new checks for I2C and SPI buses. Fix the SPI bus node names
and warnings in unit-addresses.
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dtb: Warning (i2c_bus_reg): /soc/i2c@2180000/eeprom@57: I2C bus unit address format error, expected "53"
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dtb: Warning (i2c_bus_reg): /soc/i2c@2180000/eeprom@56: I2C bus unit address format error, expected "52"
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The R8A77990 (E3) platform has one RGB output and two LVDS outputs
connected to the DU. Add the DT nodes for the DU, LVDS encoders and
supporting VSP and FCP.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Commit a7eb26392b ("arm64: dts: broadcom: Add reference to Compute
Module IO Board V3") adds the bcm2837-rpi-cm3-io3.dts file as a target
in the Makefile, rather than the .dtb name. This will skip the
generation of the .dtb file at compile time and will fail the dtbs_install
target.
Fixes: a7eb26392b ("arm64: dts: broadcom: Add reference to Compute Module IO Board V3")
Signed-off-by: Liviu Dudau <liviu@dudau.co.uk>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add support for the bananapi R64 (BPI-R64) development board from
BIPAI KEJI. Detailed hardware information for BPI-R64 which could be
found on http://wiki.banana-pi.org/Banana_Pi_BPI-R64
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Fix ram size to 512 megabytes and sort nodes in alphabetical order.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Acked-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add a built-in bluetooth 5 support for MT7622.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Acked-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add device tree entries for timer, ARM CCI-400 and its PMU.
Otherwise, we add a cortex-a53-pmu node to enable hw perfevents.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Enable all necessary device tree nodes and add connector node to device
trees for all supported A64 boards with HDMI.
Jagan, tested on BPI-M64, OPI-Win, A64-Olinuxino, NPI-A64
Vasily, tested on pine64-lts
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
[Icenowy: squash all board patches altogether and change supply name]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Allwinner A64 have a display pipeline with 2 mixers/TCONs, the first
TCON is connected to LCD and the second is to HDMI.
The HDMI controller/PHY pair is similar to the one on H3/H5.
Add all required device tree nodes of the display pipeline, including
the TCON0 LCD one and the TCON1 HDMI one.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
[Icenowy: refactor commit message and add 1st pipeline]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
fsl-mc bus support the new iommu-map property. Comply to this binding
for fsl_mc bus.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Reviewed-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Describe TPU in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
R-Car Gen3 SoCs need to enable/deassert clocks/resets of both usb 2.0
host (included phy) and peripheral. Otherwise, other side device
cannot work correctly. So, this patch revises properties of clocks
and resets. After that, each device driver can enable/deassert
clocks/resets by its self.
Notes:
- To work the renesas_usbhs driver correctly when host side drivers
are disabled and the renesas_usbhs driver doesn't have multiple
clock management, this patch doesn't change the order of the clocks
property in each hsusb node.
- This patch doesn't have any side-effects even if the renesas_usbhs
driver doesn't have reset_control and multiple clock management.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
MMC host controller bindings and MMC core defines card detect pin as
active low. Therefore there is no point to invert it twice.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
It can't boot without bootargs settings on Uboot on ulcb board.
This patch adds missing default bootargs.
ulcb BSP can overwrite it by own UBoot settings.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This branch adds changes for the Texas Instruments AM654 SoC. Included
changes are:
- Add uart nodes
- Change address cells and size-cells of interconnect tfrom 1 to 2
- Add secure proxy instance for main domain
- Add DMSC support
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Merge tag 'am654-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into next/dt
TI AM654 support for v4.20 merge window.
This branch adds changes for the Texas Instruments AM654 SoC. Included
changes are:
- Add uart nodes
- Change address cells and size-cells of interconnect tfrom 1 to 2
- Add secure proxy instance for main domain
- Add DMSC support
* tag 'am654-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
arm64: dts: ti: k3-am6: Add Device Management Security Controller support
arm64: dts: ti: am654: Add secure proxy instance for main domain
arm64: dts: ti: am654: Add uart nodes
arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
Signed-off-by: Olof Johansson <olof@lixom.net>
for 4.20, please pull the following:
- Stefan provides a reference to the Compute Module IO Board V3 such
that we can reference the arm counterpart and still build it for arm64
- Rob fixes I2C and SPI bus warnings which are going to show up with his
update to DTC scheduled for 4.20
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Merge tag 'arm-soc/for-4.20/devicetree-arm64' of https://github.com/Broadcom/stblinux into next/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree changes
for 4.20, please pull the following:
- Stefan provides a reference to the Compute Module IO Board V3 such
that we can reference the arm counterpart and still build it for arm64
- Rob fixes I2C and SPI bus warnings which are going to show up with his
update to DTC scheduled for 4.20
* tag 'arm-soc/for-4.20/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Fix I2C and SPI bus warnings
arm64: dts: broadcom: Add reference to Compute Module IO Board V3
Signed-off-by: Olof Johansson <olof@lixom.net>
New boards are the px30 eval board and roc-rk3399-pc.
The rk3328 got support for the one gpio controlled via the general
register files and the rk3399 finally got its idle-states defined.
And finally fixes and improvements for firefly-rk3399 (wifi),
roc-rk3328-cc (sdmmc-uhs, io-domains), rk3328-rock64 (gpio-regulator
pin fix) and rk3399-sapphire (gpio-regulator pin fix, pmic pin fix
and type-c port supply).
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Merge tag 'v4.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
New soc support for the px30 quad-core Cortex-A35.
New boards are the px30 eval board and roc-rk3399-pc.
The rk3328 got support for the one gpio controlled via the general
register files and the rk3399 finally got its idle-states defined.
And finally fixes and improvements for firefly-rk3399 (wifi),
roc-rk3328-cc (sdmmc-uhs, io-domains), rk3328-rock64 (gpio-regulator
pin fix) and rk3399-sapphire (gpio-regulator pin fix, pmic pin fix
and type-c port supply).
* tag 'v4.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Add type-c port supply on rk3399-sapphire board
arm64: dts: rockchip: fix vcc_host1_5v pin assign on rk3328-rock64
arm64: dts: rockchip: add WiFi module support for Firefly-RK3399
arm64: dts: rockchip: remove dvs2 pinctrl from pmic on rk3399-sapphire
arm64: dts: rockchip: Fix VCC5V0_HOST_EN on rk3399-sapphire
arm64: dts: rockchip: re-order vcc_sys on rk3399-sapphire
arm64: dts: rockchip: add missing vop properties for px30
arm64: dts: rockchip: Add idle-states to device tree for rk3399
arm64: dts: rockchip: add sdmmc UHS support for roc-rk3328-cc
arm64: dts: rockchip: add GRF GPIO controller to rk3328
arm64: dts: rockchip: add io-domain to roc-rk3328-cc
arm64: dts: rockchip: add PX30 evaluation board devicetree
arm64: dts: rockchip: add core dtsi file for PX30 SoCs
dt-bindings: rockchip: grf: add grf and pmugrf description for px30
arm64: dts: rockchip: add support for ROC-RK3399-PC board
Signed-off-by: Olof Johansson <olof@lixom.net>
For proper working of SD cards, let's add the Card Detect GPIO property
to the common devicetree for Rock960 family boards.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add devicetree support for Rock960 board, one of the Consumer Edition
boards of the 96Boards family. This board support utilizes the common
Rock960 family board support that includes Ficus 96Board.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Since the same family members of Rock960 boards (Rock960 and Ficus)
share the same configuration, split out the common nodes into a common
dtsi file for reducing code duplication. The board specific nodes for
Ficus boards are then placed in corresponding board DTS file.
Below are some of the key differences between both Rock960 and Ficus
boards:
1. Different host enable GPIO for USB
2. Different power and reset GPIO for PCI-E
3. No Ethernet port on Rock960
Only the properties which differ between both boards are placed in the
board specific dts and the reset of the nodes are placed in common dtsi
file.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch adds sound card node for rock64. Currently we can support
S/PDIF only. It seems the lack of codec driver of rk3328 to enable
analog audio out.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The microSD card slot in the Sapphire board is not working because of
several issues:
1.- The vmmc power supply is missing in the DTS. It is capable of 3.0V
and has a GPIO-based enable control.
2.- The vqmmc power supply can provide up to 3.3V, but it is capped in
the DTS to just 3.0V because of the vmmc capability. This results in a
conflict from the mmc driver requesting an unsupportable voltage range
from 3.3V to 3.0V (min > max) as reported in dmesg. So, extend the
range up to 3.3V. The hw should be able to stand this 0.3V tolerance.
See mmc_regulator_set_vqmmc in drivers/mmc/core/core.c.
3.- The card detect signal is non-working. There is a known conflict
with jtag, but the workaround in drivers/soc/rockchip/grf.c does not
work. Adding the broken-cd attribute to the DTS fixes the issue.
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
OF graph describes USB data lanes between USB-PHY and respective MUIC.
Since graph is present and DWC driver can use it to get extcon, obsolete
extcon property can be removed.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Add a thermal-zone node and fill in all the sensors available in a
cp110 (only one in the thermal IP).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Because the label is different between CPs, the full path of a node is
unique. However, when referring to the end of the path only (the node
name), this name is not unique anymore.
The *thermal_zone_of_sensor_register() functions of the thermal core
present this limitation and prevent having a thermal-zone per CP.
Add a macro to make the distinction between node names to solve this
situation.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add a thermal-zone node and fill in all the sensors available in an
ap806 (one in the IC plus one per CPU).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
New bindings impose to declare the thermal IP from within a new syscon.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add devicetree support for HiKey970 development board which
based on Hi3670 SoC and is also one of the 96Boards Consumer
Edition and AI platform.
Only UART6 is enabled which is the default console required
by the 96Boards Consumer Edition Specification.
This patch has been tested on HiKey970 Board.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add initial devicetree support for Hisilicon Hi3670 SoC which
is similar to Hi3660 SoC with NPU support.
This SoC has Octal core BigLittle CPUs in two clusters(4 * A53 & 4 * A73).
Only UART6 has been added for console support which is
pre configured by the bootloader. A fixed clock is sourcing
the UART6 which will get replaced by the clock driver when available.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
The clocks property should either be present for all the CPUs of a
cluster or none. If these are present only for a subset of CPUs of a
cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add missing clocks property.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Describe CMTs in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The PMIC and EEPROM can operate at 400kHz, so use this speed.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
For R-Car V3H hook up SYS-DMAC1 and SYS-DMAC2 to IPMMU-DS1 to match
information in the R-Car Gen3 Rev.1.00 (April 2018) datasheet.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
For R-Car E3 hook up SYS-DMAC0, SYS-DMAC1 and SYS-DMAC2 to
IPMMU-DS0 and IPMMU-DS1 in same way as for R-Car H3.
This follows the R-Car Gen3 Rev.1.00 (April 2018) datasheet.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add TISCI compatible System controller for AM6 SoCs.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add secure proxy instance for Main domain
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add uart nodes for AM654 device tree components.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
AM65 has two PCIe controllers and each PCIe controller has '2' address
spaces one within the 4GB address space of the SoC and the other above
the 4GB address space of the SoC (cbass_main) in addition to the
register space. The size of the address space above the 4GB SoC address
space is 4GB. These address ranges will be used by CPU/DMA to access
the PCIe address space. In order to represent the address space above
the 4GB SoC address space and to represent the size of this address
space as 4GB, change address-cells and size-cells of interconnect to 2.
Since OSPI has similar need in MCU Domain Memory Map, change
address-cells and size-cells of cbass_mcu interconnect also to 2.
Fixes: ea47eed33a ("arm64: dts: ti: Add Support for AM654 SoC")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vignesh R <vigneshr@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
dtc has new checks for I2C buses. Fix the warnings in unit-addresses.
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dtb: Warning (i2c_bus_reg): /i2c@ff3d0000/codec@0a: I2C bus unit address format error, expected "a"
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add HDMI and CVBS inputs device nodes to R-Car E3 Ebisu board.
Both HDMI and CVBS inputs are connected to an ADV7482 video decoder hooked to
the SoC CSI-2 receiver port.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
dtc has new checks for SPI buses. The meson dts files have a node named
spi' which causes false positive warnings. As the node is a pinctrl child
node, change the node name to be 'spi-pins' to fix the warnings.
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dtb: Warning (spi_bus_bridge): /soc/periphs@c8834000/pinctrl@4b0/spi: incorrect #address-cells for SPI bus
Cc: Carlo Caione <carlo@caione.org>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: linux-amlogic@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The thermal device is supposed to be always enabled. As the default
value of the status property is "okay", there is no need to make this
explicit in SoC-specific .dtsi files where no override is involved.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
dtc has new checks for I2C and SPI buses. Fix the warnings in node names
and unit-addresses.
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (i2c_bus_reg): /hsls/i2c@e0000/pcf8574@20: I2C bus unit address format error, expected "27"
arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dtb: Warning (i2c_bus_reg): /hsls/i2c@e0000/pcf8574@20: I2C bus unit address format error, expected "27"
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (spi_bus_bridge): /hsls/ssp@180000: node name for SPI buses should be 'spi'
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (spi_bus_bridge): /hsls/ssp@190000: node name for SPI buses should be 'spi'
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: Jon Mason <jonmason@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The smd and smp2p drivers now support accessing the APCS GLOBAL IPC
register through the mailbox framework, so migrate the msm8996 dts to
use this and remove the syscon based APCS node.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The thermal zone uses spmi-temp-alarm as sensor, the trip points
correspond to the PMIC thermal stages 1 and 2. The critical trip
point at 125°C disables the partial PMIC shutdown at stage 2.
Without an IIO input the sensor only reports a limited number of
temperatures:
- 37°C for temperatures below 105°C
- 107°C for temperatures >= 105°C and < 125°C
- 127°C for temperatures >= 125°C
(the numbers correspond to a stage 1 threshold of 105°C)
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds the spmi-temp-alarm node to pm8998 based on the examples in the
bindings.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds the display clock controller node to sdm845 based on the
examples in the bindings.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the SMP2P nodes for the remoteproc states for adsp, cdsp and slpi.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Set the various nodes to "okay" and hook up the regulators.
NOTE: For now the main USB port (the one that goes out the Type C
connector) is forced to host. Eventually someone will need to get the
Type C detection hooked up and get this all integrated with the
PMI8998 PMIC. The reason for forcing to "host" in the meantime is
that this will leave us with one "host" and one "peripheral" port.
In order for host mode this to work, we assume that the bootloader
left things configured enough for us. Apparently the magic for that
is is to do these writes on pmi8998:
- pm_comm_write_byte(2, 0x1153, 0x2C, 0);
- pm_comm_write_byte(2, 0x1152, 0x07, 0);
- pm_comm_write_byte(2, 0x1140, 0x00, 0);
- pm_comm_write_byte(2, 0x1140, 0x01, 0);
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add regulator devices for PMIC regulators managed via VRM and XOB
RPMh accelerators.
A few notes here:
- Regulators are added directly to the board file. While it's true
that this will mean a bunch of copy/pasting for other boards that
are very similar, this is probably the right call since boards
could make changes to the way these regulators are hooked up and
trying to find a way to avoid duplication will result in some
confusing node overrides.
- Regulators that are hooked up to supply pins on the SoC are given
an alias matching the name of that pin (pin name comes from the
Qualcomm SoC "device specification" doc).
- Other regulator labels are based on the schematic. If there is
more than one logical name on the schematic for the same rail the
secondary names are also listed and should be referred to as
appropriate.
- Regulators all default to HPM mode w/ no ability to switch modes.
Future patches can switch things to LPM and possibly add
dynamic load switching if we have determined there's a benefit.
This should only be done for rails where we'll actually be able
to take advantage of the lower power modes so we don't need to
churn with lots of patches adding regulator_set_load() calls
to drivers.
NOTE: This patch is loosely based on one originally shared to me by
David Collins.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds nodes for USB and related PHYs.
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
[dianders: reworked quite a bit]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds the node to support AOSS reset driver on
SDM845
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
[bjorn: Updated addresses to match the binding that was merged]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
DTS board files should always specify model and compatible.
All DTS board files that includes msm8996.dtsi
already specifies model and compatible, and will thus
override the model and compatible in msm8996.dtsi.
Drop model from msm8916.dtsi, since it is only a source of confusion.
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
DTS board files should always specify model and compatible.
All DTS board files that includes msm8916.dtsi
already specifies model and compatible, and will thus
override the model and compatible in msm8916.dtsi.
Drop model and compatible from msm8916.dtsi,
since they are only a source of confusion.
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add qcom,apq8096 to compatible string.
This compatible is defined in Documentation/devicetree/bindings/arm/qcom.txt
and is needed for e.g. drivers/cpufreq/qcom-cpufreq-kryo.c to be probed
correctly (and for drivers/cpufreq/cpufreq-dt-platdev.c to work properly).
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add pon, coincell and rtc to the first pm8998 sid.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the adsp, modem and slpi smp2p nodes to msm8998.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the firmware and scm nodes for msm8998
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add new dtsi file for the PMI8998, with its gpios and include all three
PMICs in the MSM8998 MTP dts.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the two tsens instances and the thermal zones for CPUs, GPUs,
battery and skin sensors.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add nodes for RPM communication for MSM8998 and the regulator nodes for
the MTP.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add initial device tree support for the Qualcomm MSM8998 SoC and
MTP8998 evaluation board.
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
Signed-off-by: Imran Khan <kimran@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
[bjorn: Restructured, removed its node and moved to SPDX headers]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds the adc node to pm8998 based on the examples in the
bindings. It also fixes the order of the included headers.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Resin is board specific, so add the resin node in apq8096-db820c dtsi
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Resin is board specific so add the resin node in apq8016-sbc dtsi
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add PON and pwrkey as child nodes for PON device. Also
add additional properties for pwrkey i.e., linux,code
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The order between "syscon" and "simple-mfd" is important because in these
particular cases, the node needs to be first a "simple-mfd" to expose
it's sub-nodes, and later on a "syscon" to permit other nodes to access
this register space through the "syscon" mechanism.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The r8a77965 has a single FDP1 instance.
Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
- Device nodes with unit addresses are sorted by unit address,
- Device nodes without unit addresses and references are sorted
alphabetically.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Successfully tested on H3 ES1.0 and ES2.0, M3-W ES1.0, and M3-N ES1.0.
Even previously stubborn cards work fine. Transfer rates were >60MB/s.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device nodes for all MSIOF SPI controllers, incl. clocks, power
domains, and resets properties.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device node for the external SCIF_CLK, and describe the clock
inputs for the Baud Rate Generator for External Clock (BRG) for SCIF2,
which can increase serial clock accuracy.
The presence of the SCIF_CLK crystal and its clock frequency depend on
the actual board.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Enhance patch description]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Use the SoC-specific CPG/MSSR include file to allow future use of
R8A77990_CLK_* symbols.
Replace the hardcoded power domain indices by R8A77990_PD_* symbols.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The comments describing the non-default switch settings to use SATA are
confusing: 'Off' refers to the switch position, not to the MD12 logic
value, while the parentheses suggest otherwise. Rephrase to fix this.
Fixes: bec000784d5bb571 ("arm64: dts: renesas: salvator-xs: enable SATA")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: updated for a few new cases]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This is based on the existing KF device tree sources:
$ ls -1 arch/arm64/boot/dts/renesas/*-kf.dts
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
board.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device
tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add usb3.0 phy, host and function device nodes on RZ/G2M SoC dtsi.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add usb dmac and hsusb device nodes on RZ/G2M SoC dtsi.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add FCPF and FCPV instances to the r8a774a1 dtsi, similarly
to what was done for the r8a7796 with commit 41dbbf0c5b
("arm64: dts: r8a7796: Add FCPF and FCPV instances"),
commit 69490bc966 ("arm64: dts: renesas: r8a7796: Point
FDP1 via FCPF to IPMMU-VI0"), and commit cef942d0bd ("arm64:
dts: renesas: r8a7796: Point VSPI via FCPVI to IPMMU-VC0").
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add sound support for the RZ/G2M SoC (a.k.a. R8A774A1).
This work is based on similar work done on the R8A7796 SoC
by Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds PWM[0123456] device nodes to the RZ/G2M (a.k.a R8A774A1)
device tree.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds definitions for L2 cache for the Cortex-A53 CPU
cores (512 KiB in size, organized as 32 KiB x 16 ways), adds
Cortex-A53 CPU cores (setting a total of 6 cores, 2 x Cortex-A57
+ 4 x Cortex-A53), and finally enables the performance monitor
unit for the Cortex-A53 cores on the R8A774A1 SoC.
Based on work done for r8a7796 SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device nodes for all MSIOF SPI controllers on RZ/G2M SoC.
Based on several similar patches of the R8A7796 device tree
by Geert Uytterhoeven <geert+renesas@glider.be>
and Simon Horman <horms+renesas@verge.net.au>.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add thermal support for R8A774A1 (RZ/G2M) SoC.
Based on the work done for r8a7796 SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the I2C[0-6] and IIC Bus Interface for DVFS (IIC for DVFS)
devices nodes to the r8a774a1 device tree.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add SDHI nodes to the DT of the r8a774a1 SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add GPIO device nodes to the DT of the r8a774a1 SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
RZ/G2M (r8a774a1) SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds the SoC specific part of the Ethernet AVB
device tree node.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add support for the Interrupt Controller for External Devices
(INTC-EX) on RZ/G2M.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the device nodes for all RZ/G2M SCIF and HSCIF serial ports,
incl. clocks, power domains and DMAs.
According to the HW user manual, SCIF[015] and HSCIF[012] are
connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and
HSCIF[34] are connected to SYS-DMAC0.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Define the Condor/V3HSK board dependent parts of the DU and LVDS device
nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and
Analog Devices ADV7511W HDMI transmitter...
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the eMMC chip support for the V3M Started Kit board.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Define the generic R8A77970 part of the MMC0 (SDHI2) device node.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds OPPs table for CA57{0,1} cpu devices
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
[simon: do not give nodes unit names as they have no bus addresses]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Allow the bare M3-N-based ULCB board to boot.
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to R-Car Gen3 HW manual rev1.00, R-Car M3-N has two CAN
interfaces, similar to H3, M3-W and other SoCs from the same family.
Add CAN placeholder nodes to avoid below DTC errors:
Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:19.1-6 Label or path can0 not found
Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:25.1-6 Label or path can1 not found
These errors occur *after* the addition of r8a77965-m3nulcb-kf.dts.
Fix them beforehand.
CAN support is inspired from below commits:
- v4.7 commit 308b7e4ba6 ("arm64: dts: r8a7795: Add CAN support")
- v4.11 commit 909c162524 ("arm64: dts: r8a7796: Add CAN support")
- v4.12 commit bec0948e81 ("arm64: dts: r8a7796: Add reset control properties")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
[simon: make placeholder minimal by only including reg property]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
For R-Car M3-N hook up SYS-DMAC0, SYS-DMAC1 and SYS-DMAC2 to
IPMMU-DS0 and IPMMU-DS1 in same way as for R-Car M3-W.
This follows the R-Car Gen3 Rev.1.00 (April 2018) datasheet.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Basic support for the RZ/G2M SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Ensure that the ADV748x device addresses do not conflict, and group them
together (visually in i2cdetect)
Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe the CSI2 and VIN (and their interconnections) in the R8A77980
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the nodes to enable SATA. Note that MD12 (SW12-7) must be switched
off for that to work.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds SATA controller node for the R8A77965 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[wsa: rebased to upstream base]
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add missing chosen and memory nodes.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Use the correct compatible for the AXG ethernet mac node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Enable the PDM input device on the S400 and it to the sound card
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
There are 7 digital mics on the MIC daughter board attached
to the s400 board, so add the digital microphone codec to
its DTS
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
DMC is a small memory region with various registers,
including the ones needed for the canvas module.
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
There is actually several different libretech board with the CC suffix
so the model name is not appropriate here. Update to something more
specific
Reported-by: Da Xue <da@lessconfused.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Devices using the new V4L2 mem2mem vdec require a larger CMA pool. As
nearly all GX* devices are video/media focused and will use it, set a
larger (256MB) default value.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Sort DT nodes by address when possible, by node node name otherwise.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
As we have already binding for the H6 system controller, add its node
to the device tree.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[fixed compatible string]
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The CAN clock node should precede the "cpus" node in the R8A779{7|8}0
device trees, according to the alphanumeric node sorting rule...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The IPMMU nodes should follow the GEther node, not the CAN-FD node,
according to the <unit-address> part of the startng IPMMU-DS1 node.
While moving the nodes, also do sort them by label alphanumerically...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds PWM device nodes and enables PWM3 and PWM5 for
R-Car E3 Ebisu board. These devices are used for backlight control.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
the R8A77980 SoC's device tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
We do not enable scatter-gather mode in the TMC-ETR by default
to prevent malfunctioning of systems where the ETR may not be
properly connected to the memory subsystem to allow for simultaneous
READ/WRITE transactions when used in SG mode. Instead we whitelist
the platforms where we know that it is safe to use the mode.
All revisions of Juno have a proper ETR connection and hence
white list them.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Lorenzo Pierlisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Add the gpio-controlled regulator and add the supply to the otg-port of phy0.
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch fixes pin assign of vcc_host1_5v. This regulator is
controlled by USB20_HOST_DRV signal.
ROCK64 schematic says that GPIO0_A2 pin is used as USB20_HOST_DRV.
GPIO0_D3 pin is for SPDIF_TX_M0.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit adds WiFi module support for the Firefly-RK3399.
Signed-off-by: Shohei Maruyama <cheat.sc.linux@outlook.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
On the board DVS2 is disabled and not connected, see schematic, page 16.
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The pin is GPIO4-D1 not GPIO1-D1, see schematic, page 15 for reference.
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
OrangePi One Plus is Allwinner H6 based open-source SBC,
which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 1GB LPDDR3 RAM
- AXP805 PMIC
- 1Gbps GMAC via RTL8211
- USB 2.0 Host, OTG
- HDMI port
- 5V/2A DC power supply
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The NXP LS208xA SoCs have two dual uarts. Thus, add the second one.
Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
As per IFC binding, Absence of "little-endian" field causes registers
access in big-endian mode.
So no need to set explicit big-endian field IFC node for LS1043A and
LS1046A.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
NOR and IFC controller connectivity is big-endian.
So add big-endian field in nor device tree node allowing
IFC controller to read/write data from/to the flash correctly.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The pinmux name and label for a specific function should denote which
pingroup it is on, or if there is only one option for the function, have
not enumerating prefix/suffix at all.
The "r_i2c_pins_a" label is renamed to "r_i2c_pl89_pins" to fit our
current style. The node name "i2c" is also changed to "r-i2c-pl89-pins"
to match. The reason for the peculiar name is that the other option for
muxing R_I2C is on the PL0/PL1 pins, so the name has to mention the pin
numbers in addition to the pingroup.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The pinmux name and label for a specific function should denote which
pingroup it is on, or if there is only one option for the function, have
not enumerating prefix/suffix at all.
The "uart0_pins_a" label is renamed to "uart0_pb_pins" to fit our
current style. The node name "uart0" is also changed to "uart0-pb-pins"
to match.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The eMMC 5.0 standard introduced the data strobe (DS) pin. This pin is
not used for pre-5.0 data modes, nor is it found on pre-5.0 eMMC chips.
On the A64, this pin is muxed with spi0's MISO pin. If the DS pin is
included in the mmc2 pinmux by default, this wil prevent the usage
of both mmc2 and spi0 together.
Instead, split out the DS pin to a separate pinmux that only gets used
by boards that actually have it wired up. Currently supported ones
include the Bananapi M64 and Pine64 Pinebook. These are fixed up.
Fixes: a3e8f49262 ("arm64: allwinner: a64: Add MMC pinctrl nodes")
Fixes: b8bcf0e1b2 ("arm64: allwinner: add BananaPi-M64 support")
Fixes: df35fbcfa3 ("arm64: dts: allwinner: add support for Pinebook")
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
This adds a reference to the dts of the Compute Module IO Board V3 in arm,
so we don't need to maintain the content in arm64.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
DesignWare I2C controller was observed running at 105.93kHz rather
than the specified 100kHz. Adjust device tree settings to bring it
within spec (a slightly conservative 98 MHz).
Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Add the sound card of the s400. With it the following interface
should be working:
* Lineout
* Daugther card speaker 1 (same output as lineout)
* Linein
* SPDIF output
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add TODDR and FRDDR audio fifos of the AXG SoC.
These fifos are the capture and playback memory interfaces of audio
subsystem of the AXG.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Catch up with the new binding of the Denali IP where three clocks,
"nand", "nand_x", "ecc" are required.
For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they
are both 200MHz.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The internal LVDS encoder now has DT bindings separate from the DU. Port
the r8a7795 and r8a7796 device trees over to the new model.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Hook up SYS-DMAC0, SYS-DMAC1 and SYS-DMAC2 to IPMMU-DS0 and IPMMU-DS1
following the R-Car Gen3 Rev.1.00 (April 2018) datasheet.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Browsing the DTS for all the R-Car SoCs with similar part numbers
makes my head hurt, so to improve the user friendliness of the
DTS code base include R-Car product name in each DTSI file.
Product names are derived from
Documentation/devicetree/bindings/arm/shmobile.txt
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
