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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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arm64: tegra: Device tree changes for v4.20-rc1
This contains mostly device tree changes to support faster SDHCI modes on Tegra210 and Tegra186. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlutRCATHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoaEeD/9u+1Pv4ygX1eGlBCYoYDLNnzo+Eckn KiZzrBnK5Wxl6X/SagxQBOK8QmzTJrIAWo0oRBcUknBWKKlP7xdM4DKHnWhWHvZZ d7ulULfWDEaqcLXnlf5LH8XzrkG3UON/AA9IkAkx9jXwv7ipZVzDBN7kiLNBpZbU BPra4HRWAw2H7umDC0STSnfQoyvJ0zidk86xEWHNRTkjaQvPjuz7GmKWcgsM6cFv mh7ZdCqNYrW09D8CJwaCiSHx5DIVUyfoK9+BWxYyiYe2hOxZJHybVdOWZbjvg2K3 nD+tsV2/Ej9JUrBuxTz12IQ4Wpz/PQqkXTs3RBfzvh08+4tu20dWyt/Rj9LY5hWE R0P4RD3LOMGlycAFiSm30cRQPieYqScHsYsW6FKlE42W/4gyABgItv+nfrIVtBUd jg1XlDINhLcVTobKQAztssaPKm0iUbABrfCqccIdBSfSGIUSpxUsSlggmBYs11U+ +Yj20ObJgKvgY/1/t3VoIOYiSZ3foUq1ykqib1nVS84JJRPYVSMPy6cMu62tLT17 lyGP9SV/k5KuSrVyGyxtYiDrvWbXb+y4+4+5G3VepFkAo6CCf7GPYl92ZfAFMdGH h4IV7nZb3SLxgp7J1KtGXwblegOtt/nEWn4WqtKZiLYukKd1kdZ4wZDQx1lpb40s PCZzQrYnEKS/0w== =DHnl -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt arm64: tegra: Device tree changes for v4.20-rc1 This contains mostly device tree changes to support faster SDHCI modes on Tegra210 and Tegra186. * tag 'tegra-for-4.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: I2C on Tegra194 is not compatible with Tegra114 arm64: dts: tegra186: Enable HS400 arm64: dts: tegra210: Enable HS400 arm64: dts: tegra186: Add SDMMC4 DQS trim value arm64: dts: tegra210: Add SDMMC4 DQS trim value arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 arm64: dts: tegra186: Add SDHCI tap and trim values arm64: dts: tegra210: Add SDHCI tap and trim values arm64: dts: tegra186: Add sdmmc pad auto calibration offsets arm64: dts: tegra210: Add sdmmc pad auto calibration offsets arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V arm64: dts: Add Tegra186 sdmmc pinctrl voltage states arm64: dts: Add Tegra210 sdmmc pinctrl voltage states Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
f62309c873
@ -4,6 +4,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#include <dt-bindings/memory/tegra186-mc.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
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#include <dt-bindings/power/tegra186-powergate.h>
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#include <dt-bindings/reset/tegra186-reset.h>
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#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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@ -236,6 +237,20 @@ sdmmc1: sdhci@3400000 {
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clock-names = "sdhci";
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resets = <&bpmp TEGRA186_RESET_SDMMC1>;
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reset-names = "sdhci";
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pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
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pinctrl-0 = <&sdmmc1_3v3>;
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pinctrl-1 = <&sdmmc1_1v8>;
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nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
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nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
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nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
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nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
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nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
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nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
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nvidia,default-tap = <0x5>;
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nvidia,default-trim = <0xb>;
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assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
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<&bpmp TEGRA186_CLK_PLLP_OUT0>;
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assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
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status = "disabled";
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};
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@ -247,6 +262,15 @@ sdmmc2: sdhci@3420000 {
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clock-names = "sdhci";
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resets = <&bpmp TEGRA186_RESET_SDMMC2>;
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reset-names = "sdhci";
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pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
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pinctrl-0 = <&sdmmc2_3v3>;
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pinctrl-1 = <&sdmmc2_1v8>;
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nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
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nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
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nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
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nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
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nvidia,default-tap = <0x5>;
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nvidia,default-trim = <0xb>;
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status = "disabled";
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};
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@ -258,6 +282,17 @@ sdmmc3: sdhci@3440000 {
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clock-names = "sdhci";
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resets = <&bpmp TEGRA186_RESET_SDMMC3>;
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reset-names = "sdhci";
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pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
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pinctrl-0 = <&sdmmc3_3v3>;
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pinctrl-1 = <&sdmmc3_1v8>;
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nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
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nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
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nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
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nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
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nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
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nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
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nvidia,default-tap = <0x5>;
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nvidia,default-trim = <0xb>;
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status = "disabled";
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};
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@ -267,8 +302,19 @@ sdmmc4: sdhci@3460000 {
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
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clock-names = "sdhci";
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assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
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<&bpmp TEGRA186_CLK_PLLC4_VCO>;
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assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
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resets = <&bpmp TEGRA186_RESET_SDMMC4>;
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reset-names = "sdhci";
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nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
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nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
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nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
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nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
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nvidia,default-tap = <0x5>;
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nvidia,default-trim = <0x9>;
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nvidia,dqs-trim = <63>;
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mmc-hs400-1_8v;
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status = "disabled";
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};
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@ -368,6 +414,36 @@ pmc@c360000 {
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<0 0x0c380000 0 0x10000>,
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<0 0x0c390000 0 0x10000>;
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reg-names = "pmc", "wake", "aotag", "scratch";
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sdmmc1_3v3: sdmmc1-3v3 {
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pins = "sdmmc1-hv";
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power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
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};
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sdmmc1_1v8: sdmmc1-1v8 {
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pins = "sdmmc1-hv";
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power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
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};
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sdmmc2_3v3: sdmmc2-3v3 {
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pins = "sdmmc2-hv";
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power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
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};
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sdmmc2_1v8: sdmmc2-1v8 {
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pins = "sdmmc2-hv";
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power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
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};
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sdmmc3_3v3: sdmmc3-3v3 {
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pins = "sdmmc3-hv";
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power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
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};
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sdmmc3_1v8: sdmmc3-1v8 {
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pins = "sdmmc3-hv";
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power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
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};
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};
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ccplex@e000000 {
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@ -118,7 +118,7 @@ uartf: serial@3150000 {
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};
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gen1_i2c: i2c@3160000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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compatible = "nvidia,tegra194-i2c";
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reg = <0x03160000 0x10000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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@ -143,7 +143,7 @@ uarth: serial@3170000 {
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};
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cam_i2c: i2c@3180000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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compatible = "nvidia,tegra194-i2c";
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reg = <0x03180000 0x10000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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@ -157,7 +157,7 @@ cam_i2c: i2c@3180000 {
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/* shares pads with dpaux1 */
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dp_aux_ch1_i2c: i2c@3190000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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compatible = "nvidia,tegra194-i2c";
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reg = <0x03190000 0x10000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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@ -171,7 +171,7 @@ dp_aux_ch1_i2c: i2c@3190000 {
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/* shares pads with dpaux0 */
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dp_aux_ch0_i2c: i2c@31b0000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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compatible = "nvidia,tegra194-i2c";
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reg = <0x031b0000 0x10000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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@ -184,7 +184,7 @@ dp_aux_ch0_i2c: i2c@31b0000 {
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};
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gen7_i2c: i2c@31c0000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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compatible = "nvidia,tegra194-i2c";
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reg = <0x031c0000 0x10000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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@ -197,7 +197,7 @@ gen7_i2c: i2c@31c0000 {
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};
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gen9_i2c: i2c@31e0000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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compatible = "nvidia,tegra194-i2c";
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reg = <0x031e0000 0x10000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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@ -264,7 +264,7 @@ hsp_top0: hsp@3c00000 {
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};
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gen2_i2c: i2c@c240000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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compatible = "nvidia,tegra194-i2c";
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reg = <0x0c240000 0x10000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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@ -277,7 +277,7 @@ gen2_i2c: i2c@c240000 {
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};
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gen8_i2c: i2c@c250000 {
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compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
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compatible = "nvidia,tegra194-i2c";
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reg = <0x0c250000 0x10000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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@ -178,16 +178,7 @@ vdd_pex_1v05: ldo1 {
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vddio_sdmmc: ldo2 {
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regulator-name = "VDDIO_SDMMC";
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/*
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* Technically this supply should have
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* a supported range from 1.8 - 3.3 V.
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* However, that would cause the SDHCI
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* driver to request 2.7 V upon access
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* and that in turn will cause traffic
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* to be broken. Leave it at 3.3 V for
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* now.
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*/
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regulator-min-microvolt = <3300000>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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@ -282,6 +273,7 @@ sdhci@700b0600 {
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status = "okay";
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bus-width = <8>;
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non-removable;
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vqmmc-supply = <&vdd_1v8>;
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};
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clocks {
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@ -1452,7 +1452,6 @@ usb3-1 {
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sdhci@700b0000 {
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status = "okay";
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bus-width = <4>;
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no-1-8-v;
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cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
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@ -3,6 +3,7 @@
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#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/memory/tegra210-mc.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/tegra124-soctherm.h>
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@ -776,6 +777,26 @@ pd_vic: vic {
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#power-domain-cells = <0>;
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};
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};
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sdmmc1_3v3: sdmmc1-3v3 {
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pins = "sdmmc1";
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power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
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};
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sdmmc1_1v8: sdmmc1-1v8 {
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pins = "sdmmc1";
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power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
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};
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sdmmc3_3v3: sdmmc3-3v3 {
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pins = "sdmmc3";
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power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
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};
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sdmmc3_1v8: sdmmc3-1v8 {
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pins = "sdmmc3";
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power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
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};
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};
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fuse@7000f800 {
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@ -1027,6 +1048,20 @@ sdhci@700b0000 {
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clock-names = "sdhci";
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resets = <&tegra_car 14>;
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reset-names = "sdhci";
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pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
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pinctrl-0 = <&sdmmc1_3v3>;
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pinctrl-1 = <&sdmmc1_1v8>;
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nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
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nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
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nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
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nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
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nvidia,default-tap = <0x2>;
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nvidia,default-trim = <0x4>;
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assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
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<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
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<&tegra_car TEGRA210_CLK_PLL_C4>;
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assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
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assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
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status = "disabled";
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};
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@ -1038,6 +1073,10 @@ sdhci@700b0200 {
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clock-names = "sdhci";
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resets = <&tegra_car 9>;
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reset-names = "sdhci";
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nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
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nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
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nvidia,default-tap = <0x8>;
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nvidia,default-trim = <0x0>;
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status = "disabled";
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};
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@ -1049,6 +1088,15 @@ sdhci@700b0400 {
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clock-names = "sdhci";
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resets = <&tegra_car 69>;
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reset-names = "sdhci";
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pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
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pinctrl-0 = <&sdmmc3_3v3>;
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pinctrl-1 = <&sdmmc3_1v8>;
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nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
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nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
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nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
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nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
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nvidia,default-tap = <0x3>;
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nvidia,default-trim = <0x3>;
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status = "disabled";
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};
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@ -1060,6 +1108,15 @@ sdhci@700b0600 {
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clock-names = "sdhci";
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resets = <&tegra_car 15>;
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reset-names = "sdhci";
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nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
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nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
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nvidia,default-tap = <0x8>;
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nvidia,default-trim = <0x0>;
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assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
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<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
|
||||
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
|
||||
nvidia,dqs-trim = <40>;
|
||||
mmc-hs400-1_8v;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user