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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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arm64: dts: uniphier: Add USB2 PHY nodes
Add nodes of USB2 physical layer for UniPhier SoC. This supports LD11. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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@ -454,6 +454,8 @@ usb0: usb@5a800100 {
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<&mio_clk 12>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
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<&mio_rst 12>;
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phy-names = "usb";
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phys = <&usb_phy0>;
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has-transaction-translator;
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};
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@ -468,6 +470,8 @@ usb1: usb@5a810100 {
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<&mio_clk 13>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
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<&mio_rst 13>;
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phy-names = "usb";
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phys = <&usb_phy1>;
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has-transaction-translator;
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};
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@ -482,6 +486,8 @@ usb2: usb@5a820100 {
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<&mio_clk 14>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
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<&mio_rst 14>;
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phy-names = "usb";
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phys = <&usb_phy2>;
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has-transaction-translator;
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};
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@ -510,6 +516,27 @@ soc_glue: soc-glue@5f800000 {
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pinctrl: pinctrl {
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compatible = "socionext,uniphier-ld11-pinctrl";
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};
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usb-phy {
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compatible = "socionext,uniphier-ld11-usb2-phy";
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#address-cells = <1>;
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#size-cells = <0>;
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usb_phy0: phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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usb_phy1: phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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usb_phy2: phy@2 {
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reg = <2>;
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#phy-cells = <0>;
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};
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};
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};
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soc-glue@5f900000 {
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