mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 16:06:44 +07:00
mt2712 - add spi slave node
mt7622: - add timer node - add CCI node - add PMU node - add bluetooth node - add SPI slave node - fix reference board (rfb1) memory and sort node alphabetically - add support for Bananapi-R64 -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAluvglMXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00Pnzg//Ygw/So3J9SQNxPyKyk9uoKAy jyhdWiy0/QUMfDSeLcDTwYRqmdb/Ofmw6PYxG6MouNmxDW6/Nlt4uYjBGgJy7w5a eN0oonhZTANSSduve2SX4RmKH9RasM2+YCMVWnwHH2SLKEiOEytUATKQYzoPw4gh JgkErAL9otGSPRMLIcgRcOnL700k1yBGERwOb3+0CYTWbPAbiuF34UVkeYt/CVID CxyY8Pi6vHkk6MmcsCa6jFY1+YoZQhOwR6FDk2dahYBStYFF37NtRcPv+ea9+t6k PhN1QeNJ7NJuRmfTgffHgBTkap3qBQjJyK3Bgc+88yi1d1Giuy1vRJfxmtK2thzt OP4MOD/t4hrV6tOrZ1V0ztVyQZCAYDEopM9XXe0o5Nb9dR9+Q+MRvb2VdgCBNT1F 1lWwiZZtFNFzMPdNrC4fwhAPTM/9VBghCc2drxbizy2BtobDkkQK5/A7/UbHIVR5 AV2HLPvCac27BbbYiSYemv5quSuBGVy4JoMhatKMwE7F798NLHipcanNpHVQR86n BvwQpglWgIjomDgu83LkaJZgs07esa5y1TJJpzJ0o8kAn13FgzK0UdiYeNy5Rprz sy+KzWy0PoL4yladowIFZRnFzkgXd+F00gZKKNdAdY04ZUp5CaDn0GVt9WqCkDwr Z+O3Budk3jyNRpF+Nv4= =ySpY -----END PGP SIGNATURE----- Merge tag 'v4.19-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt mt2712 - add spi slave node mt7622: - add timer node - add CCI node - add PMU node - add bluetooth node - add SPI slave node - fix reference board (rfb1) memory and sort node alphabetically - add support for Bananapi-R64 * tag 'v4.19-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: arm64: dts: Add spi slave dts arm64: dts: mt7622: add bananapi BPI-R64 board arm64: dts: mt7622: fix ram size for rfb1 arm64: dts: mt7622: add a bluetooth 5 device node arm64: dts: mt7622: add timer, CCI-400 and PMU nodes Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
508b330b82
@ -5,4 +5,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
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@ -301,6 +301,17 @@ uart5: serial@1000f000 {
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status = "disabled";
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};
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spis1: spi@10013000 {
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compatible = "mediatek,mt2712-spi-slave";
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reg = <0 0x10013000 0 0x100>;
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interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_AO_SPI1>;
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clock-names = "spi";
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assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
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status = "disabled";
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};
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apmixedsys: syscon@10209000 {
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compatible = "mediatek,mt2712-apmixedsys", "syscon";
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reg = <0 0x10209000 0 0x1000>;
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530
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
Normal file
530
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
Normal file
@ -0,0 +1,530 @@
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*
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* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "mt7622.dtsi"
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#include "mt6380.dtsi"
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/ {
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model = "Bananapi BPI-R64";
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compatible = "bananapi,bpi-r64", "mediatek,mt7622";
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
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};
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cpus {
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cpu@0 {
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proc-supply = <&mt6380_vcpu_reg>;
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sram-supply = <&mt6380_vm_reg>;
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};
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cpu@1 {
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proc-supply = <&mt6380_vcpu_reg>;
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sram-supply = <&mt6380_vm_reg>;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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factory {
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label = "factory";
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linux,code = <BTN_0>;
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gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
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};
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wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
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};
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};
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leds {
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compatible = "gpio-leds";
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green {
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label = "bpi-r64:pio:green";
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gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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red {
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label = "bpi-r64:pio:red";
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gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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memory {
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reg = <0 0x40000000 0 0x40000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_5v: regulator-5v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&bch {
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status = "disabled";
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};
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&btif {
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status = "okay";
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};
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&cir {
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pinctrl-names = "default";
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pinctrl-0 = <&irrx_pins>;
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status = "okay";
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};
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ð {
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pinctrl-names = "default";
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pinctrl-0 = <ð_pins>;
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status = "okay";
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-handle = <&phy5>;
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};
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mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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phy5: ethernet-phy@5 {
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reg = <5>;
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phy-mode = "sgmii";
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};
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};
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins>;
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status = "okay";
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};
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&mmc0 {
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&emmc_pins_default>;
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pinctrl-1 = <&emmc_pins_uhs>;
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status = "okay";
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bus-width = <8>;
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max-frequency = <50000000>;
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cap-mmc-highspeed;
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mmc-hs200-1_8v;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
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non-removable;
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};
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&mmc1 {
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&sd0_pins_default>;
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pinctrl-1 = <&sd0_pins_uhs>;
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status = "okay";
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bus-width = <4>;
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max-frequency = <50000000>;
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cap-sd-highspeed;
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r_smpl = <1>;
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cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_3p3v>;
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assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
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};
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&nandc {
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pinctrl-names = "default";
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pinctrl-0 = <¶llel_nand_pins>;
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status = "disabled";
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};
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&nor_flash {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_nor_pins>;
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status = "disabled";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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};
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
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status = "okay";
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pcie@0,0 {
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status = "okay";
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};
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pcie@1,0 {
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status = "okay";
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};
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};
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&pio {
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/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
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* SATA functions. i.e. output-high: PCIe, output-low: SATA
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*/
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asm_sel {
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gpio-hog;
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gpios = <90 GPIO_ACTIVE_HIGH>;
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output-high;
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};
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/* eMMC is shared pin with parallel NAND */
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emmc_pins_default: emmc-pins-default {
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mux {
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function = "emmc", "emmc_rst";
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groups = "emmc";
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};
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/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
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* "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
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* DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
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*/
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conf-cmd-dat {
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pins = "NDL0", "NDL1", "NDL2",
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"NDL3", "NDL4", "NDL5",
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"NDL6", "NDL7", "NRB";
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input-enable;
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bias-pull-up;
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};
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conf-clk {
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pins = "NCLE";
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bias-pull-down;
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};
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};
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emmc_pins_uhs: emmc-pins-uhs {
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mux {
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function = "emmc";
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groups = "emmc";
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};
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conf-cmd-dat {
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pins = "NDL0", "NDL1", "NDL2",
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"NDL3", "NDL4", "NDL5",
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"NDL6", "NDL7", "NRB";
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input-enable;
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drive-strength = <4>;
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bias-pull-up;
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};
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conf-clk {
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pins = "NCLE";
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drive-strength = <4>;
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bias-pull-down;
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};
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};
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eth_pins: eth-pins {
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mux {
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function = "eth";
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groups = "mdc_mdio", "rgmii_via_gmac2";
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};
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};
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i2c1_pins: i2c1-pins {
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mux {
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function = "i2c";
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groups = "i2c1_0";
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};
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};
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i2c2_pins: i2c2-pins {
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mux {
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function = "i2c";
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groups = "i2c2_0";
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};
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};
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i2s1_pins: i2s1-pins {
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mux {
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function = "i2s";
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groups = "i2s_out_mclk_bclk_ws",
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"i2s1_in_data",
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"i2s1_out_data";
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};
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conf {
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pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
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"I2S_WS", "I2S_MCLK";
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drive-strength = <12>;
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bias-pull-down;
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};
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};
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irrx_pins: irrx-pins {
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mux {
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function = "ir";
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groups = "ir_1_rx";
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};
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};
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irtx_pins: irtx-pins {
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mux {
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function = "ir";
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groups = "ir_1_tx";
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};
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};
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/* Parallel nand is shared pin with eMMC */
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parallel_nand_pins: parallel-nand-pins {
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mux {
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function = "flash";
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groups = "par_nand";
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};
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};
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pcie0_pins: pcie0-pins {
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mux {
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function = "pcie";
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groups = "pcie0_pad_perst",
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"pcie0_1_waken",
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"pcie0_1_clkreq";
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||||
};
|
||||
};
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|
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pcie1_pins: pcie1-pins {
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mux {
|
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function = "pcie";
|
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groups = "pcie1_pad_perst",
|
||||
"pcie1_0_waken",
|
||||
"pcie1_0_clkreq";
|
||||
};
|
||||
};
|
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|
||||
pmic_bus_pins: pmic-bus-pins {
|
||||
mux {
|
||||
function = "pmic";
|
||||
groups = "pmic_bus";
|
||||
};
|
||||
};
|
||||
|
||||
pwm7_pins: pwm1-2-pins {
|
||||
mux {
|
||||
function = "pwm";
|
||||
groups = "pwm_ch7_2";
|
||||
};
|
||||
};
|
||||
|
||||
wled_pins: wled-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "wled";
|
||||
};
|
||||
};
|
||||
|
||||
sd0_pins_default: sd0-pins-default {
|
||||
mux {
|
||||
function = "sd";
|
||||
groups = "sd_0";
|
||||
};
|
||||
|
||||
/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
|
||||
* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
|
||||
* DAT2, DAT3, CMD, CLK for SD respectively.
|
||||
*/
|
||||
conf-cmd-data {
|
||||
pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
|
||||
"I2S2_IN","I2S4_OUT";
|
||||
input-enable;
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
conf-clk {
|
||||
pins = "I2S3_OUT";
|
||||
drive-strength = <12>;
|
||||
bias-pull-down;
|
||||
};
|
||||
conf-cd {
|
||||
pins = "TXD3";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sd0_pins_uhs: sd0-pins-uhs {
|
||||
mux {
|
||||
function = "sd";
|
||||
groups = "sd_0";
|
||||
};
|
||||
|
||||
conf-cmd-data {
|
||||
pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
|
||||
"I2S2_IN","I2S4_OUT";
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
conf-clk {
|
||||
pins = "I2S3_OUT";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
/* Serial NAND is shared pin with SPI-NOR */
|
||||
serial_nand_pins: serial-nand-pins {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "snfi";
|
||||
};
|
||||
};
|
||||
|
||||
spic0_pins: spic0-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spic0_0";
|
||||
};
|
||||
};
|
||||
|
||||
spic1_pins: spic1-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spic1_0";
|
||||
};
|
||||
};
|
||||
|
||||
/* SPI-NOR is shared pin with serial NAND */
|
||||
spi_nor_pins: spi-nor-pins {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "spi_nor";
|
||||
};
|
||||
};
|
||||
|
||||
/* serial NAND is shared pin with SPI-NOR */
|
||||
serial_nand_pins: serial-nand-pins {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "snfi";
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0-pins {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart0_0_tx_rx" ;
|
||||
};
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart2_1_tx_rx" ;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog_pins: watchdog-pins {
|
||||
mux {
|
||||
function = "watchdog";
|
||||
groups = "watchdog";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm7_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwrap {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_bus_pins>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
&sata_phy {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spic0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spic1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssusb {
|
||||
vusb33-supply = <®_3p3v>;
|
||||
vbus-supply = <®_5v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u3phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&watchdog_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
@ -51,7 +51,7 @@ wps {
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0 0x40000000 0 0x3F000000>;
|
||||
reg = <0 0x40000000 0 0x20000000>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
@ -81,6 +81,103 @@ reg_5v: regulator-5v {
|
||||
};
|
||||
};
|
||||
|
||||
&bch {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&btif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cir {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&irrx_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <ð_pins>;
|
||||
status = "okay";
|
||||
|
||||
gmac1: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
|
||||
mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
pinctrl-0 = <&emmc_pins_default>;
|
||||
pinctrl-1 = <&emmc_pins_uhs>;
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
max-frequency = <50000000>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-hs200-1_8v;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
pinctrl-0 = <&sd0_pins_default>;
|
||||
pinctrl-1 = <&sd0_pins_uhs>;
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
max-frequency = <50000000>;
|
||||
cap-sd-highspeed;
|
||||
r_smpl = <1>;
|
||||
cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_3p3v>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
|
||||
};
|
||||
|
||||
&nandc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <¶llel_nand_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&nor_flash {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_nor_pins>;
|
||||
status = "disabled";
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie0_pins>;
|
||||
@ -344,103 +441,6 @@ mux {
|
||||
};
|
||||
};
|
||||
|
||||
&bch {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&btif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cir {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&irrx_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <ð_pins>;
|
||||
status = "okay";
|
||||
|
||||
gmac1: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
|
||||
mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
pinctrl-0 = <&emmc_pins_default>;
|
||||
pinctrl-1 = <&emmc_pins_uhs>;
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
max-frequency = <50000000>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-hs200-1_8v;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
pinctrl-0 = <&sd0_pins_default>;
|
||||
pinctrl-1 = <&sd0_pins_uhs>;
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
max-frequency = <50000000>;
|
||||
cap-sd-highspeed;
|
||||
r_smpl = <1>;
|
||||
cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_3p3v>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
|
||||
};
|
||||
|
||||
&nandc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <¶llel_nand_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&nor_flash {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_nor_pins>;
|
||||
status = "disabled";
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm7_pins>;
|
||||
|
||||
@ -79,6 +79,7 @@ cpu0: cpu@0 {
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <1300000000>;
|
||||
cci-control-port = <&cci_control2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
@ -92,6 +93,7 @@ cpu1: cpu@1 {
|
||||
#cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <1300000000>;
|
||||
cci-control-port = <&cci_control2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -113,6 +115,13 @@ psci {
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
@ -218,6 +227,16 @@ pericfg: pericfg@10002000 {
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
timer: timer@10004000 {
|
||||
compatible = "mediatek,mt7622-timer",
|
||||
"mediatek,mt6577-timer";
|
||||
reg = <0 0x10004000 0 0x80>;
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infracfg CLK_INFRA_APXGPT_PD>,
|
||||
<&topckgen CLK_TOP_RTC>;
|
||||
clock-names = "system-clk", "rtc-clk";
|
||||
};
|
||||
|
||||
scpsys: scpsys@10006000 {
|
||||
compatible = "mediatek,mt7622-scpsys",
|
||||
"syscon";
|
||||
@ -325,6 +344,42 @@ gic: interrupt-controller@10300000 {
|
||||
<0 0x10360000 0 0x2000>;
|
||||
};
|
||||
|
||||
cci: cci@10390000 {
|
||||
compatible = "arm,cci-400";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0 0x10390000 0 0x1000>;
|
||||
ranges = <0 0 0x10390000 0x10000>;
|
||||
|
||||
cci_control0: slave-if@1000 {
|
||||
compatible = "arm,cci-400-ctrl-if";
|
||||
interface-type = "ace-lite";
|
||||
reg = <0x1000 0x1000>;
|
||||
};
|
||||
|
||||
cci_control1: slave-if@4000 {
|
||||
compatible = "arm,cci-400-ctrl-if";
|
||||
interface-type = "ace";
|
||||
reg = <0x4000 0x1000>;
|
||||
};
|
||||
|
||||
cci_control2: slave-if@5000 {
|
||||
compatible = "arm,cci-400-ctrl-if";
|
||||
interface-type = "ace";
|
||||
reg = <0x5000 0x1000>;
|
||||
};
|
||||
|
||||
pmu@9000 {
|
||||
compatible = "arm,cci-400-pmu,r1";
|
||||
reg = <0x9000 0x5000>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
auxadc: adc@11001000 {
|
||||
compatible = "mediatek,mt7622-auxadc";
|
||||
reg = <0 0x11001000 0 0x1000>;
|
||||
@ -475,6 +530,13 @@ btif: serial@1100c000 {
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
|
||||
bluetooth {
|
||||
compatible = "mediatek,mt7622-bluetooth";
|
||||
power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
|
||||
clocks = <&clk25m>;
|
||||
clock-names = "ref";
|
||||
};
|
||||
};
|
||||
|
||||
nandc: nfi@1100d000 {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user