2010-05-22 03:26:39 +07:00
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/*
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* Copyright © 2008-2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Zou Nan hai <nanhai.zou@intel.com>
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* Xiang Hai hao<haihao.xiang@intel.com>
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*
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*/
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2015-12-06 17:26:30 +07:00
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#include <linux/log2.h>
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2012-10-03 00:01:07 +07:00
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#include <drm/drmP.h>
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2010-05-22 03:26:39 +07:00
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#include "i915_drv.h"
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2012-10-03 00:01:07 +07:00
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#include <drm/i915_drm.h>
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2010-05-22 03:26:39 +07:00
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#include "i915_trace.h"
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2010-09-19 20:40:43 +07:00
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#include "intel_drv.h"
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2010-05-22 03:26:39 +07:00
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2016-04-29 15:07:05 +07:00
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/* Rough estimate of the typical request size, performing a flush,
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* set-context and then emitting the batch.
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*/
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#define LEGACY_REQUEST_SIZE 200
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2014-07-24 23:04:26 +07:00
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int __intel_ring_space(int head, int tail, int size)
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2011-01-21 00:00:10 +07:00
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{
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2014-11-27 18:22:48 +07:00
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int space = head - tail;
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if (space <= 0)
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2014-05-05 15:07:33 +07:00
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space += size;
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2014-11-27 18:22:48 +07:00
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return space - I915_RING_FREE_SPACE;
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2011-01-21 00:00:10 +07:00
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}
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2014-11-27 18:22:49 +07:00
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void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
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{
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if (ringbuf->last_retired_head != -1) {
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ringbuf->head = ringbuf->last_retired_head;
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ringbuf->last_retired_head = -1;
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}
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ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
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ringbuf->tail, ringbuf->size);
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}
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2016-03-16 18:00:40 +07:00
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bool intel_engine_stopped(struct intel_engine_cs *engine)
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2013-08-11 04:16:32 +07:00
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{
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2016-05-06 21:40:21 +07:00
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struct drm_i915_private *dev_priv = engine->i915;
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2016-03-16 18:00:39 +07:00
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return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
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2014-03-28 23:18:18 +07:00
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}
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2013-08-11 04:16:32 +07:00
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2016-03-16 18:00:37 +07:00
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static void __intel_ring_advance(struct intel_engine_cs *engine)
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2014-03-28 23:18:18 +07:00
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{
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2016-03-16 18:00:37 +07:00
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struct intel_ringbuffer *ringbuf = engine->buffer;
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2014-05-22 20:13:36 +07:00
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ringbuf->tail &= ringbuf->size - 1;
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2016-03-16 18:00:40 +07:00
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if (intel_engine_stopped(engine))
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2013-08-11 04:16:32 +07:00
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return;
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2016-03-16 18:00:37 +07:00
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engine->write_tail(engine, ringbuf->tail);
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2013-08-11 04:16:32 +07:00
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}
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2011-01-05 00:34:02 +07:00
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static int
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2015-05-29 23:43:57 +07:00
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gen2_render_ring_flush(struct drm_i915_gem_request *req,
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2012-04-18 17:12:11 +07:00
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u32 invalidate_domains,
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u32 flush_domains)
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{
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2016-03-16 18:00:38 +07:00
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struct intel_engine_cs *engine = req->engine;
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2012-04-18 17:12:11 +07:00
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u32 cmd;
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int ret;
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cmd = MI_FLUSH;
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2012-04-19 21:45:22 +07:00
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if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
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2012-04-18 17:12:11 +07:00
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cmd |= MI_NO_WRITE_FLUSH;
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if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
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cmd |= MI_READ_FLUSH;
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2015-05-29 23:44:07 +07:00
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ret = intel_ring_begin(req, 2);
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2012-04-18 17:12:11 +07:00
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if (ret)
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return ret;
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2016-03-16 18:00:36 +07:00
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intel_ring_emit(engine, cmd);
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intel_ring_emit(engine, MI_NOOP);
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intel_ring_advance(engine);
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2012-04-18 17:12:11 +07:00
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return 0;
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}
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static int
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2015-05-29 23:43:57 +07:00
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gen4_render_ring_flush(struct drm_i915_gem_request *req,
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2012-04-18 17:12:11 +07:00
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u32 invalidate_domains,
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u32 flush_domains)
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2010-05-22 03:26:39 +07:00
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{
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2016-03-16 18:00:38 +07:00
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struct intel_engine_cs *engine = req->engine;
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2010-08-07 17:01:22 +07:00
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u32 cmd;
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2011-01-05 00:34:02 +07:00
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int ret;
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2010-08-07 17:01:22 +07:00
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2011-03-20 05:26:49 +07:00
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/*
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* read/write caches:
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*
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* I915_GEM_DOMAIN_RENDER is always invalidated, but is
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* only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
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* also flushed at 2d versus 3d pipeline switches.
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*
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* read-only caches:
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*
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* I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
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* MI_READ_FLUSH is set, and is always flushed on 965.
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*
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* I915_GEM_DOMAIN_COMMAND may not exist?
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*
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* I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
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* invalidated when MI_EXE_FLUSH is set.
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*
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* I915_GEM_DOMAIN_VERTEX, which exists on 965, is
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* invalidated with every MI_FLUSH.
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*
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* TLBs:
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*
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* On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
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* and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
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* I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
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* are flushed at any MI_FLUSH.
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*/
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cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
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2012-04-18 17:12:11 +07:00
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if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
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2011-03-20 05:26:49 +07:00
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cmd &= ~MI_NO_WRITE_FLUSH;
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if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
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cmd |= MI_EXE_FLUSH;
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2010-05-22 03:26:39 +07:00
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2011-03-20 05:26:49 +07:00
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if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
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2016-05-06 21:40:21 +07:00
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(IS_G4X(req->i915) || IS_GEN5(req->i915)))
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2011-03-20 05:26:49 +07:00
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cmd |= MI_INVALIDATE_ISP;
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2010-11-30 21:07:47 +07:00
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2015-05-29 23:44:07 +07:00
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ret = intel_ring_begin(req, 2);
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2011-03-20 05:26:49 +07:00
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if (ret)
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return ret;
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2011-01-05 00:34:02 +07:00
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2016-03-16 18:00:36 +07:00
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intel_ring_emit(engine, cmd);
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intel_ring_emit(engine, MI_NOOP);
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intel_ring_advance(engine);
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2011-01-05 00:34:02 +07:00
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return 0;
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2010-05-21 08:08:55 +07:00
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}
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2011-10-16 15:23:31 +07:00
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/**
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* Emits a PIPE_CONTROL with a non-zero post-sync operation, for
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* implementing two workarounds on gen6. From section 1.4.7.1
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* "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
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*
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* [DevSNB-C+{W/A}] Before any depth stall flush (including those
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* produced by non-pipelined state commands), software needs to first
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* send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
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* 0.
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*
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* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
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* =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
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*
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* And the workaround for these two requires this workaround first:
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*
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* [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
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* BEFORE the pipe-control with a post-sync op and no write-cache
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* flushes.
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*
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* And this last workaround is tricky because of the requirements on
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* that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
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* volume 2 part 1:
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*
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* "1 of the following must also be set:
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* - Render Target Cache Flush Enable ([12] of DW1)
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* - Depth Cache Flush Enable ([0] of DW1)
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* - Stall at Pixel Scoreboard ([1] of DW1)
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* - Depth Stall ([13] of DW1)
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* - Post-Sync Operation ([13] of DW1)
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* - Notify Enable ([8] of DW1)"
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*
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* The cache flushes require the workaround flush that triggered this
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* one, so we can't use it. Depth stall would trigger the same.
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* Post-sync nonzero is what triggered this second workaround, so we
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* can't use that one either. Notify enable is IRQs, which aren't
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* really our business. That leaves only stall at scoreboard.
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*/
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static int
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2015-05-29 23:43:58 +07:00
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intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
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2011-10-16 15:23:31 +07:00
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{
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2016-03-16 18:00:38 +07:00
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struct intel_engine_cs *engine = req->engine;
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2016-03-16 18:00:36 +07:00
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u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
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2011-10-16 15:23:31 +07:00
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int ret;
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2015-05-29 23:44:07 +07:00
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ret = intel_ring_begin(req, 6);
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2011-10-16 15:23:31 +07:00
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if (ret)
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return ret;
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2016-03-16 18:00:36 +07:00
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intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
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intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
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2011-10-16 15:23:31 +07:00
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PIPE_CONTROL_STALL_AT_SCOREBOARD);
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2016-03-16 18:00:36 +07:00
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intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
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intel_ring_emit(engine, 0); /* low dword */
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intel_ring_emit(engine, 0); /* high dword */
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intel_ring_emit(engine, MI_NOOP);
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intel_ring_advance(engine);
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2011-10-16 15:23:31 +07:00
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2015-05-29 23:44:07 +07:00
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ret = intel_ring_begin(req, 6);
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2011-10-16 15:23:31 +07:00
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if (ret)
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return ret;
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2016-03-16 18:00:36 +07:00
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intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
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intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
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intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
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intel_ring_emit(engine, 0);
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intel_ring_emit(engine, 0);
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intel_ring_emit(engine, MI_NOOP);
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intel_ring_advance(engine);
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2011-10-16 15:23:31 +07:00
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return 0;
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}
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static int
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2015-05-29 23:43:57 +07:00
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gen6_render_ring_flush(struct drm_i915_gem_request *req,
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u32 invalidate_domains, u32 flush_domains)
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2011-10-16 15:23:31 +07:00
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{
|
2016-03-16 18:00:38 +07:00
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struct intel_engine_cs *engine = req->engine;
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2011-10-16 15:23:31 +07:00
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u32 flags = 0;
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2016-03-16 18:00:36 +07:00
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u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
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2011-10-16 15:23:31 +07:00
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int ret;
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2012-08-18 04:35:42 +07:00
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/* Force SNB workarounds for PIPE_CONTROL flushes */
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2015-05-29 23:43:58 +07:00
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ret = intel_emit_post_sync_nonzero_flush(req);
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2012-08-18 04:35:42 +07:00
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if (ret)
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return ret;
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2011-10-16 15:23:31 +07:00
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/* Just flush everything. Experiments have shown that reducing the
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* number of bits based on the write domains has little performance
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* impact.
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*/
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2012-08-10 16:18:10 +07:00
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if (flush_domains) {
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flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
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flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
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/*
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* Ensure that any following seqno writes only happen
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* when the render cache is indeed flushed.
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*/
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2012-06-28 14:48:42 +07:00
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flags |= PIPE_CONTROL_CS_STALL;
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2012-08-10 16:18:10 +07:00
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}
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if (invalidate_domains) {
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flags |= PIPE_CONTROL_TLB_INVALIDATE;
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flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
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/*
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* TLB invalidate requires a post-sync write.
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*/
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2012-10-26 02:15:47 +07:00
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flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
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2012-08-10 16:18:10 +07:00
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}
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2011-10-16 15:23:31 +07:00
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2015-05-29 23:44:07 +07:00
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ret = intel_ring_begin(req, 4);
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2011-10-16 15:23:31 +07:00
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if (ret)
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return ret;
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2016-03-16 18:00:36 +07:00
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intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
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intel_ring_emit(engine, flags);
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intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
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intel_ring_emit(engine, 0);
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intel_ring_advance(engine);
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2011-10-16 15:23:31 +07:00
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return 0;
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}
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|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-18 04:35:43 +07:00
|
|
|
static int
|
2015-05-29 23:43:58 +07:00
|
|
|
gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-18 04:35:43 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-18 04:35:43 +07:00
|
|
|
int ret;
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 4);
|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-18 04:35:43 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
|
|
|
|
intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-18 04:35:43 +07:00
|
|
|
PIPE_CONTROL_STALL_AT_SCOREBOARD);
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, 0);
|
|
|
|
intel_ring_emit(engine, 0);
|
|
|
|
intel_ring_advance(engine);
|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-18 04:35:43 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-08-18 04:35:41 +07:00
|
|
|
static int
|
2015-05-29 23:43:57 +07:00
|
|
|
gen7_render_ring_flush(struct drm_i915_gem_request *req,
|
2012-08-18 04:35:41 +07:00
|
|
|
u32 invalidate_domains, u32 flush_domains)
|
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2012-08-18 04:35:41 +07:00
|
|
|
u32 flags = 0;
|
2016-03-16 18:00:36 +07:00
|
|
|
u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
|
2012-08-18 04:35:41 +07:00
|
|
|
int ret;
|
|
|
|
|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-18 04:35:43 +07:00
|
|
|
/*
|
|
|
|
* Ensure that any following seqno writes only happen when the render
|
|
|
|
* cache is indeed flushed.
|
|
|
|
*
|
|
|
|
* Workaround: 4th PIPE_CONTROL command (except the ones with only
|
|
|
|
* read-cache invalidate bits set) must have the CS_STALL bit set. We
|
|
|
|
* don't try to be clever and just set it unconditionally.
|
|
|
|
*/
|
|
|
|
flags |= PIPE_CONTROL_CS_STALL;
|
|
|
|
|
2012-08-18 04:35:41 +07:00
|
|
|
/* Just flush everything. Experiments have shown that reducing the
|
|
|
|
* number of bits based on the write domains has little performance
|
|
|
|
* impact.
|
|
|
|
*/
|
|
|
|
if (flush_domains) {
|
|
|
|
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
|
|
|
|
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
|
2016-01-14 09:59:39 +07:00
|
|
|
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
|
2015-08-21 22:08:41 +07:00
|
|
|
flags |= PIPE_CONTROL_FLUSH_ENABLE;
|
2012-08-18 04:35:41 +07:00
|
|
|
}
|
|
|
|
if (invalidate_domains) {
|
|
|
|
flags |= PIPE_CONTROL_TLB_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
|
2014-12-16 15:44:31 +07:00
|
|
|
flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
|
2012-08-18 04:35:41 +07:00
|
|
|
/*
|
|
|
|
* TLB invalidate requires a post-sync write.
|
|
|
|
*/
|
|
|
|
flags |= PIPE_CONTROL_QW_WRITE;
|
2013-02-15 02:53:51 +07:00
|
|
|
flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-18 04:35:43 +07:00
|
|
|
|
2014-12-16 15:44:32 +07:00
|
|
|
flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
|
|
|
|
|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-18 04:35:43 +07:00
|
|
|
/* Workaround: we must issue a pipe_control with CS-stall bit
|
|
|
|
* set before a pipe_control command that has the state cache
|
|
|
|
* invalidate bit set. */
|
2015-05-29 23:43:58 +07:00
|
|
|
gen7_render_ring_cs_stall_wa(req);
|
2012-08-18 04:35:41 +07:00
|
|
|
}
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 4);
|
2012-08-18 04:35:41 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
|
|
|
|
intel_ring_emit(engine, flags);
|
|
|
|
intel_ring_emit(engine, scratch_addr);
|
|
|
|
intel_ring_emit(engine, 0);
|
|
|
|
intel_ring_advance(engine);
|
2012-08-18 04:35:41 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-06-28 06:04:20 +07:00
|
|
|
static int
|
2015-05-29 23:43:58 +07:00
|
|
|
gen8_emit_pipe_control(struct drm_i915_gem_request *req,
|
2014-06-28 06:04:20 +07:00
|
|
|
u32 flags, u32 scratch_addr)
|
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2014-06-28 06:04:20 +07:00
|
|
|
int ret;
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 6);
|
2014-06-28 06:04:20 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
|
|
|
|
intel_ring_emit(engine, flags);
|
|
|
|
intel_ring_emit(engine, scratch_addr);
|
|
|
|
intel_ring_emit(engine, 0);
|
|
|
|
intel_ring_emit(engine, 0);
|
|
|
|
intel_ring_emit(engine, 0);
|
|
|
|
intel_ring_advance(engine);
|
2014-06-28 06:04:20 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-11-03 11:07:27 +07:00
|
|
|
static int
|
2015-05-29 23:43:57 +07:00
|
|
|
gen8_render_ring_flush(struct drm_i915_gem_request *req,
|
2013-11-03 11:07:27 +07:00
|
|
|
u32 invalidate_domains, u32 flush_domains)
|
|
|
|
{
|
|
|
|
u32 flags = 0;
|
2016-03-16 18:00:38 +07:00
|
|
|
u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
|
2014-01-28 05:20:16 +07:00
|
|
|
int ret;
|
2013-11-03 11:07:27 +07:00
|
|
|
|
|
|
|
flags |= PIPE_CONTROL_CS_STALL;
|
|
|
|
|
|
|
|
if (flush_domains) {
|
|
|
|
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
|
|
|
|
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
|
2016-01-14 09:59:39 +07:00
|
|
|
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
|
2015-08-21 22:08:41 +07:00
|
|
|
flags |= PIPE_CONTROL_FLUSH_ENABLE;
|
2013-11-03 11:07:27 +07:00
|
|
|
}
|
|
|
|
if (invalidate_domains) {
|
|
|
|
flags |= PIPE_CONTROL_TLB_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_QW_WRITE;
|
|
|
|
flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
|
2014-01-28 05:20:16 +07:00
|
|
|
|
|
|
|
/* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
|
2015-05-29 23:43:58 +07:00
|
|
|
ret = gen8_emit_pipe_control(req,
|
2014-01-28 05:20:16 +07:00
|
|
|
PIPE_CONTROL_CS_STALL |
|
|
|
|
PIPE_CONTROL_STALL_AT_SCOREBOARD,
|
|
|
|
0);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-11-03 11:07:27 +07:00
|
|
|
}
|
|
|
|
|
2015-05-29 23:43:58 +07:00
|
|
|
return gen8_emit_pipe_control(req, flags, scratch_addr);
|
2013-11-03 11:07:27 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static void ring_write_tail(struct intel_engine_cs *engine,
|
2010-10-22 23:02:41 +07:00
|
|
|
u32 value)
|
2010-09-16 09:43:12 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE_TAIL(engine, value);
|
2010-09-16 09:43:12 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
|
2010-05-21 08:08:55 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2014-03-21 19:41:53 +07:00
|
|
|
u64 acthd;
|
2010-05-21 08:08:55 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
2016-03-16 18:00:37 +07:00
|
|
|
acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
|
|
|
|
RING_ACTHD_UDW(engine->mmio_base));
|
2016-05-06 21:40:21 +07:00
|
|
|
else if (INTEL_GEN(dev_priv) >= 4)
|
2016-03-16 18:00:37 +07:00
|
|
|
acthd = I915_READ(RING_ACTHD(engine->mmio_base));
|
2014-03-21 19:41:53 +07:00
|
|
|
else
|
|
|
|
acthd = I915_READ(ACTHD);
|
|
|
|
|
|
|
|
return acthd;
|
2010-05-21 08:08:55 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
|
2013-07-03 17:56:54 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2013-07-03 17:56:54 +07:00
|
|
|
u32 addr;
|
|
|
|
|
|
|
|
addr = dev_priv->status_page_dmah->busaddr;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (INTEL_GEN(dev_priv) >= 4)
|
2013-07-03 17:56:54 +07:00
|
|
|
addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
|
|
|
|
I915_WRITE(HWS_PGA, addr);
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
|
2015-02-11 02:32:17 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t mmio;
|
2015-02-11 02:32:17 +07:00
|
|
|
|
|
|
|
/* The ring status page addresses are no longer next to the rest of
|
|
|
|
* the ring registers as of gen7.
|
|
|
|
*/
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_GEN7(dev_priv)) {
|
2016-03-16 18:00:37 +07:00
|
|
|
switch (engine->id) {
|
2015-02-11 02:32:17 +07:00
|
|
|
case RCS:
|
|
|
|
mmio = RENDER_HWS_PGA_GEN7;
|
|
|
|
break;
|
|
|
|
case BCS:
|
|
|
|
mmio = BLT_HWS_PGA_GEN7;
|
|
|
|
break;
|
|
|
|
/*
|
|
|
|
* VCS2 actually doesn't exist on Gen7. Only shut up
|
|
|
|
* gcc switch check warning
|
|
|
|
*/
|
|
|
|
case VCS2:
|
|
|
|
case VCS:
|
|
|
|
mmio = BSD_HWS_PGA_GEN7;
|
|
|
|
break;
|
|
|
|
case VECS:
|
|
|
|
mmio = VEBOX_HWS_PGA_GEN7;
|
|
|
|
break;
|
|
|
|
}
|
2016-05-06 21:40:21 +07:00
|
|
|
} else if (IS_GEN6(dev_priv)) {
|
2016-03-16 18:00:37 +07:00
|
|
|
mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
|
2015-02-11 02:32:17 +07:00
|
|
|
} else {
|
|
|
|
/* XXX: gen8 returns to sanity */
|
2016-03-16 18:00:37 +07:00
|
|
|
mmio = RING_HWS_PGA(engine->mmio_base);
|
2015-02-11 02:32:17 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
|
2015-02-11 02:32:17 +07:00
|
|
|
POSTING_READ(mmio);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flush the TLB for this page
|
|
|
|
*
|
|
|
|
* FIXME: These two bits have disappeared on gen8, so a question
|
|
|
|
* arises: do we still need this and if so how should we go about
|
|
|
|
* invalidating the TLB?
|
|
|
|
*/
|
2016-05-10 16:57:08 +07:00
|
|
|
if (IS_GEN(dev_priv, 6, 7)) {
|
2016-03-16 18:00:37 +07:00
|
|
|
i915_reg_t reg = RING_INSTPM(engine->mmio_base);
|
2015-02-11 02:32:17 +07:00
|
|
|
|
|
|
|
/* ring should be idle before issuing a sync flush*/
|
2016-03-16 18:00:37 +07:00
|
|
|
WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
|
2015-02-11 02:32:17 +07:00
|
|
|
|
|
|
|
I915_WRITE(reg,
|
|
|
|
_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
|
|
|
|
INSTPM_SYNC_FLUSH));
|
2016-06-30 21:33:29 +07:00
|
|
|
if (intel_wait_for_register(dev_priv,
|
|
|
|
reg, INSTPM_SYNC_FLUSH, 0,
|
|
|
|
1000))
|
2015-02-11 02:32:17 +07:00
|
|
|
DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->name);
|
2015-02-11 02:32:17 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static bool stop_ring(struct intel_engine_cs *engine)
|
2010-05-21 08:08:55 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2010-05-21 08:08:55 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (!IS_GEN2(dev_priv)) {
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
|
2016-06-30 21:33:30 +07:00
|
|
|
if (intel_wait_for_register(dev_priv,
|
|
|
|
RING_MI_MODE(engine->mmio_base),
|
|
|
|
MODE_IDLE,
|
|
|
|
MODE_IDLE,
|
|
|
|
1000)) {
|
2016-03-16 18:00:37 +07:00
|
|
|
DRM_ERROR("%s : timed out trying to stop ring\n",
|
|
|
|
engine->name);
|
2014-08-11 15:21:35 +07:00
|
|
|
/* Sometimes we observe that the idle flag is not
|
|
|
|
* set even though the ring is empty. So double
|
|
|
|
* check before giving up.
|
|
|
|
*/
|
2016-03-16 18:00:37 +07:00
|
|
|
if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
|
2014-08-11 15:21:35 +07:00
|
|
|
return false;
|
2014-04-02 22:36:07 +07:00
|
|
|
}
|
|
|
|
}
|
2012-06-04 16:18:15 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE_CTL(engine, 0);
|
|
|
|
I915_WRITE_HEAD(engine, 0);
|
|
|
|
engine->write_tail(engine, 0);
|
2010-05-21 08:08:55 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (!IS_GEN2(dev_priv)) {
|
2016-03-16 18:00:37 +07:00
|
|
|
(void)I915_READ_CTL(engine);
|
|
|
|
I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
|
2014-04-02 22:36:07 +07:00
|
|
|
}
|
2014-03-12 18:09:40 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
|
2014-04-02 22:36:07 +07:00
|
|
|
}
|
2010-05-21 08:08:55 +07:00
|
|
|
|
2016-03-21 23:26:59 +07:00
|
|
|
void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static int init_ring_common(struct intel_engine_cs *engine)
|
2014-04-02 22:36:07 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-03-16 18:00:37 +07:00
|
|
|
struct intel_ringbuffer *ringbuf = engine->buffer;
|
2014-05-22 20:13:36 +07:00
|
|
|
struct drm_i915_gem_object *obj = ringbuf->obj;
|
2014-04-02 22:36:07 +07:00
|
|
|
int ret = 0;
|
|
|
|
|
2015-01-16 16:34:40 +07:00
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
2014-04-02 22:36:07 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
if (!stop_ring(engine)) {
|
2014-04-02 22:36:07 +07:00
|
|
|
/* G45 ring initialization often fails to reset head to zero */
|
2010-12-06 03:42:33 +07:00
|
|
|
DRM_DEBUG_KMS("%s head not reset to zero "
|
|
|
|
"ctl %08x head %08x tail %08x start %08x\n",
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->name,
|
|
|
|
I915_READ_CTL(engine),
|
|
|
|
I915_READ_HEAD(engine),
|
|
|
|
I915_READ_TAIL(engine),
|
|
|
|
I915_READ_START(engine));
|
2010-05-21 08:08:55 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
if (!stop_ring(engine)) {
|
2010-12-06 03:42:33 +07:00
|
|
|
DRM_ERROR("failed to set %s head to zero "
|
|
|
|
"ctl %08x head %08x tail %08x start %08x\n",
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->name,
|
|
|
|
I915_READ_CTL(engine),
|
|
|
|
I915_READ_HEAD(engine),
|
|
|
|
I915_READ_TAIL(engine),
|
|
|
|
I915_READ_START(engine));
|
2014-04-02 22:36:07 +07:00
|
|
|
ret = -EIO;
|
|
|
|
goto out;
|
2010-12-06 03:42:33 +07:00
|
|
|
}
|
2010-05-21 08:08:55 +07:00
|
|
|
}
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (I915_NEED_GFX_HWS(dev_priv))
|
2016-03-16 18:00:37 +07:00
|
|
|
intel_ring_setup_status_page(engine);
|
2014-04-02 22:36:07 +07:00
|
|
|
else
|
2016-03-16 18:00:37 +07:00
|
|
|
ring_setup_phys_status_page(engine);
|
2014-04-02 22:36:07 +07:00
|
|
|
|
2014-08-07 21:29:53 +07:00
|
|
|
/* Enforce ordering by reading HEAD register back */
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_READ_HEAD(engine);
|
2014-08-07 21:29:53 +07:00
|
|
|
|
2012-08-07 14:54:14 +07:00
|
|
|
/* Initialize the ring. This must happen _after_ we've cleared the ring
|
|
|
|
* registers with the above sequence (the readback of the HEAD registers
|
|
|
|
* also enforces ordering), otherwise the hw might lose the new ring
|
|
|
|
* register values. */
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
|
2014-08-07 21:39:54 +07:00
|
|
|
|
|
|
|
/* WaClearRingBufHeadRegAtInit:ctg,elk */
|
2016-03-16 18:00:37 +07:00
|
|
|
if (I915_READ_HEAD(engine))
|
2014-08-07 21:39:54 +07:00
|
|
|
DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->name, I915_READ_HEAD(engine));
|
|
|
|
I915_WRITE_HEAD(engine, 0);
|
|
|
|
(void)I915_READ_HEAD(engine);
|
2014-08-07 21:39:54 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE_CTL(engine,
|
2014-05-22 20:13:36 +07:00
|
|
|
((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
|
drm/i915: Remove use of the autoreported ringbuffer HEAD position
This is a revert of 6aa56062eaba67adfb247cded244fd877329588d.
This was originally introduced to workaround reads of the ringbuffer
registers returning 0 on SandyBridge causing hangs due to ringbuffer
overflow. The root cause here was reads through the GT powerwell require
the forcewake dance, something we only learnt of later. Now it appears
that reading the reported head position from the HWS is returning
garbage, leading once again to hangs.
For example, on q35 the autoreported head reports:
[ 217.975608] head now 00010000, actual 00010000
[ 436.725613] head now 00200000, actual 00200000
[ 462.956033] head now 00210000, actual 00210010
[ 485.501409] head now 00400000, actual 00400020
[ 508.064280] head now 00410000, actual 00410000
[ 530.576078] head now 00600000, actual 00600020
[ 553.273489] head now 00610000, actual 00610018
which appears reasonably sane. In contrast, if we look at snb:
[ 141.970680] head now 00e10000, actual 00008238
[ 141.974062] head now 02734000, actual 000083c8
[ 141.974425] head now 00e10000, actual 00008488
[ 141.980374] head now 032b5000, actual 000088b8
[ 141.980885] head now 03271000, actual 00008950
[ 142.040628] head now 02101000, actual 00008b40
[ 142.180173] head now 02734000, actual 00009050
[ 142.181090] head now 00000000, actual 00000ae0
[ 142.183737] head now 02734000, actual 00009050
In addition, the automatic reporting of the head position is scheduled
to be defeatured in the future. It has no more utility, remove it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45492
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Tested-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-08 20:34:13 +07:00
|
|
|
| RING_VALID);
|
2010-05-21 08:08:55 +07:00
|
|
|
|
|
|
|
/* If the head is still not zero, the ring is dead */
|
2016-03-16 18:00:37 +07:00
|
|
|
if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
|
|
|
|
I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
|
|
|
|
(I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
|
2010-11-09 17:16:56 +07:00
|
|
|
DRM_ERROR("%s initialization failed "
|
2014-04-09 15:19:44 +07:00
|
|
|
"ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->name,
|
|
|
|
I915_READ_CTL(engine),
|
|
|
|
I915_READ_CTL(engine) & RING_VALID,
|
|
|
|
I915_READ_HEAD(engine), I915_READ_TAIL(engine),
|
|
|
|
I915_READ_START(engine),
|
|
|
|
(unsigned long)i915_gem_obj_ggtt_offset(obj));
|
2012-06-04 16:18:15 +07:00
|
|
|
ret = -EIO;
|
|
|
|
goto out;
|
2010-05-21 08:08:55 +07:00
|
|
|
}
|
|
|
|
|
2014-11-27 18:22:49 +07:00
|
|
|
ringbuf->last_retired_head = -1;
|
2016-03-16 18:00:37 +07:00
|
|
|
ringbuf->head = I915_READ_HEAD(engine);
|
|
|
|
ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
|
2014-11-27 18:22:49 +07:00
|
|
|
intel_ring_update_space(ringbuf);
|
2010-12-04 18:30:53 +07:00
|
|
|
|
2016-03-21 23:26:59 +07:00
|
|
|
intel_engine_init_hangcheck(engine);
|
2013-06-10 17:20:19 +07:00
|
|
|
|
2012-06-04 16:18:15 +07:00
|
|
|
out:
|
2015-01-16 16:34:40 +07:00
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
2012-06-04 16:18:15 +07:00
|
|
|
|
|
|
|
return ret;
|
2010-05-21 08:08:55 +07:00
|
|
|
}
|
|
|
|
|
2014-07-24 23:04:24 +07:00
|
|
|
void
|
2016-03-16 18:00:37 +07:00
|
|
|
intel_fini_pipe_control(struct intel_engine_cs *engine)
|
2014-07-24 23:04:24 +07:00
|
|
|
{
|
2016-03-16 18:00:37 +07:00
|
|
|
if (engine->scratch.obj == NULL)
|
2014-07-24 23:04:24 +07:00
|
|
|
return;
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (INTEL_GEN(engine->i915) >= 5) {
|
2016-03-16 18:00:37 +07:00
|
|
|
kunmap(sg_page(engine->scratch.obj->pages->sgl));
|
|
|
|
i915_gem_object_ggtt_unpin(engine->scratch.obj);
|
2014-07-24 23:04:24 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
drm_gem_object_unreference(&engine->scratch.obj->base);
|
|
|
|
engine->scratch.obj = NULL;
|
2014-07-24 23:04:24 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
2016-03-16 18:00:37 +07:00
|
|
|
intel_init_pipe_control(struct intel_engine_cs *engine)
|
2010-12-15 16:56:50 +07:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
WARN_ON(engine->scratch.obj);
|
2010-12-15 16:56:50 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
engine->scratch.obj = i915_gem_object_create(engine->i915->dev, 4096);
|
2016-04-25 19:32:13 +07:00
|
|
|
if (IS_ERR(engine->scratch.obj)) {
|
2010-12-15 16:56:50 +07:00
|
|
|
DRM_ERROR("Failed to allocate seqno page\n");
|
2016-04-25 19:32:13 +07:00
|
|
|
ret = PTR_ERR(engine->scratch.obj);
|
|
|
|
engine->scratch.obj = NULL;
|
2010-12-15 16:56:50 +07:00
|
|
|
goto err;
|
|
|
|
}
|
2011-04-04 15:44:39 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
ret = i915_gem_object_set_cache_level(engine->scratch.obj,
|
|
|
|
I915_CACHE_LLC);
|
2014-02-14 20:01:13 +07:00
|
|
|
if (ret)
|
|
|
|
goto err_unref;
|
2010-12-15 16:56:50 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
|
2010-12-15 16:56:50 +07:00
|
|
|
if (ret)
|
|
|
|
goto err_unref;
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
|
|
|
|
engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
|
|
|
|
if (engine->scratch.cpu_page == NULL) {
|
2013-05-28 16:51:44 +07:00
|
|
|
ret = -ENOMEM;
|
2010-12-15 16:56:50 +07:00
|
|
|
goto err_unpin;
|
2013-05-28 16:51:44 +07:00
|
|
|
}
|
2010-12-15 16:56:50 +07:00
|
|
|
|
2013-02-13 03:01:38 +07:00
|
|
|
DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->name, engine->scratch.gtt_offset);
|
2010-12-15 16:56:50 +07:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_unpin:
|
2016-03-16 18:00:37 +07:00
|
|
|
i915_gem_object_ggtt_unpin(engine->scratch.obj);
|
2010-12-15 16:56:50 +07:00
|
|
|
err_unref:
|
2016-03-16 18:00:37 +07:00
|
|
|
drm_gem_object_unreference(&engine->scratch.obj->base);
|
2010-12-15 16:56:50 +07:00
|
|
|
err:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-05-29 23:43:54 +07:00
|
|
|
static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
|
2014-08-26 20:44:50 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2016-05-06 21:40:21 +07:00
|
|
|
struct i915_workarounds *w = &req->i915->workarounds;
|
|
|
|
int ret, i;
|
2014-08-26 20:44:51 +07:00
|
|
|
|
2015-10-07 18:44:01 +07:00
|
|
|
if (w->count == 0)
|
2014-10-07 21:21:26 +07:00
|
|
|
return 0;
|
2014-08-26 20:44:51 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->gpu_caches_dirty = true;
|
2015-05-29 23:43:55 +07:00
|
|
|
ret = intel_ring_flush_all_caches(req);
|
2014-10-07 21:21:26 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2014-08-26 20:44:51 +07:00
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, (w->count * 2 + 2));
|
2014-10-07 21:21:26 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
|
2014-10-07 21:21:26 +07:00
|
|
|
for (i = 0; i < w->count; i++) {
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit_reg(engine, w->reg[i].addr);
|
|
|
|
intel_ring_emit(engine, w->reg[i].value);
|
2014-10-07 21:21:26 +07:00
|
|
|
}
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, MI_NOOP);
|
2014-10-07 21:21:26 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_advance(engine);
|
2014-10-07 21:21:26 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->gpu_caches_dirty = true;
|
2015-05-29 23:43:55 +07:00
|
|
|
ret = intel_ring_flush_all_caches(req);
|
2014-10-07 21:21:26 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2014-08-26 20:44:51 +07:00
|
|
|
|
2014-10-07 21:21:26 +07:00
|
|
|
DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
|
2014-08-26 20:44:51 +07:00
|
|
|
|
2014-10-07 21:21:26 +07:00
|
|
|
return 0;
|
2014-08-26 20:44:50 +07:00
|
|
|
}
|
|
|
|
|
2015-05-29 23:43:44 +07:00
|
|
|
static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
|
2014-12-02 22:19:07 +07:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2015-05-29 23:43:54 +07:00
|
|
|
ret = intel_ring_workarounds_emit(req);
|
2014-12-02 22:19:07 +07:00
|
|
|
if (ret != 0)
|
|
|
|
return ret;
|
|
|
|
|
2015-05-29 23:43:45 +07:00
|
|
|
ret = i915_gem_render_state_init(req);
|
2014-12-02 22:19:07 +07:00
|
|
|
if (ret)
|
2016-01-29 23:49:05 +07:00
|
|
|
return ret;
|
2014-12-02 22:19:07 +07:00
|
|
|
|
2016-01-29 23:49:05 +07:00
|
|
|
return 0;
|
2014-12-02 22:19:07 +07:00
|
|
|
}
|
|
|
|
|
2014-10-07 21:21:26 +07:00
|
|
|
static int wa_add(struct drm_i915_private *dev_priv,
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t addr,
|
|
|
|
const u32 mask, const u32 val)
|
2014-10-07 21:21:26 +07:00
|
|
|
{
|
|
|
|
const u32 idx = dev_priv->workarounds.count;
|
|
|
|
|
|
|
|
if (WARN_ON(idx >= I915_MAX_WA_REGS))
|
|
|
|
return -ENOSPC;
|
|
|
|
|
|
|
|
dev_priv->workarounds.reg[idx].addr = addr;
|
|
|
|
dev_priv->workarounds.reg[idx].value = val;
|
|
|
|
dev_priv->workarounds.reg[idx].mask = mask;
|
|
|
|
|
|
|
|
dev_priv->workarounds.count++;
|
|
|
|
|
|
|
|
return 0;
|
2014-08-26 20:44:50 +07:00
|
|
|
}
|
|
|
|
|
2015-08-11 21:44:31 +07:00
|
|
|
#define WA_REG(addr, mask, val) do { \
|
2014-12-09 00:35:37 +07:00
|
|
|
const int r = wa_add(dev_priv, (addr), (mask), (val)); \
|
2014-10-07 21:21:26 +07:00
|
|
|
if (r) \
|
|
|
|
return r; \
|
2015-08-11 21:44:31 +07:00
|
|
|
} while (0)
|
2014-10-07 21:21:26 +07:00
|
|
|
|
|
|
|
#define WA_SET_BIT_MASKED(addr, mask) \
|
2014-12-09 00:35:38 +07:00
|
|
|
WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
|
2014-10-07 21:21:26 +07:00
|
|
|
|
|
|
|
#define WA_CLR_BIT_MASKED(addr, mask) \
|
2014-12-09 00:35:38 +07:00
|
|
|
WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
|
2014-10-07 21:21:26 +07:00
|
|
|
|
2014-12-09 00:33:51 +07:00
|
|
|
#define WA_SET_FIELD_MASKED(addr, mask, value) \
|
2014-12-09 00:35:37 +07:00
|
|
|
WA_REG(addr, mask, _MASKED_FIELD(mask, value))
|
2014-10-07 21:21:26 +07:00
|
|
|
|
2014-12-09 00:35:37 +07:00
|
|
|
#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
|
|
|
|
#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
|
2014-10-07 21:21:26 +07:00
|
|
|
|
2014-12-09 00:35:37 +07:00
|
|
|
#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
|
2014-10-07 21:21:26 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
|
|
|
|
i915_reg_t reg)
|
2016-01-22 04:43:47 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-01-22 04:43:47 +07:00
|
|
|
struct i915_workarounds *wa = &dev_priv->workarounds;
|
2016-03-16 18:00:37 +07:00
|
|
|
const uint32_t index = wa->hw_whitelist_count[engine->id];
|
2016-01-22 04:43:47 +07:00
|
|
|
|
|
|
|
if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
|
2016-01-22 04:43:47 +07:00
|
|
|
i915_mmio_reg_offset(reg));
|
2016-03-16 18:00:37 +07:00
|
|
|
wa->hw_whitelist_count[engine->id]++;
|
2016-01-22 04:43:47 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static int gen8_init_workarounds(struct intel_engine_cs *engine)
|
2015-09-25 23:40:37 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2015-09-25 23:40:38 +07:00
|
|
|
|
|
|
|
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
|
2015-09-25 23:40:37 +07:00
|
|
|
|
2015-09-25 23:40:39 +07:00
|
|
|
/* WaDisableAsyncFlipPerfMode:bdw,chv */
|
|
|
|
WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
|
|
|
|
|
2015-09-25 23:40:40 +07:00
|
|
|
/* WaDisablePartialInstShootdown:bdw,chv */
|
|
|
|
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
|
|
|
|
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
|
|
|
|
|
2015-09-25 23:40:45 +07:00
|
|
|
/* Use Force Non-Coherent whenever executing a 3D context. This is a
|
|
|
|
* workaround for for a possible hang in the unlikely event a TLB
|
|
|
|
* invalidation occurs during a PSD flush.
|
|
|
|
*/
|
|
|
|
/* WaForceEnableNonCoherent:bdw,chv */
|
2015-09-25 23:40:46 +07:00
|
|
|
/* WaHdcDisableFetchWhenMasked:bdw,chv */
|
2015-09-25 23:40:45 +07:00
|
|
|
WA_SET_BIT_MASKED(HDC_CHICKEN0,
|
2015-09-25 23:40:46 +07:00
|
|
|
HDC_DONOT_FETCH_MEM_WHEN_MASKED |
|
2015-09-25 23:40:45 +07:00
|
|
|
HDC_FORCE_NON_COHERENT);
|
|
|
|
|
2015-09-25 23:40:42 +07:00
|
|
|
/* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
|
|
|
|
* "The Hierarchical Z RAW Stall Optimization allows non-overlapping
|
|
|
|
* polygons in the same 8x4 pixel/sample area to be processed without
|
|
|
|
* stalling waiting for the earlier ones to write to Hierarchical Z
|
|
|
|
* buffer."
|
|
|
|
*
|
|
|
|
* This optimization is off by default for BDW and CHV; turn it on.
|
|
|
|
*/
|
|
|
|
WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
|
|
|
|
|
2015-09-25 23:40:43 +07:00
|
|
|
/* Wa4x4STCOptimizationDisable:bdw,chv */
|
|
|
|
WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
|
|
|
|
|
2015-09-25 23:40:44 +07:00
|
|
|
/*
|
|
|
|
* BSpec recommends 8x4 when MSAA is used,
|
|
|
|
* however in practice 16x4 seems fastest.
|
|
|
|
*
|
|
|
|
* Note that PS/WM thread counts depend on the WIZ hashing
|
|
|
|
* disable bit, which we don't touch here, but it's good
|
|
|
|
* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
|
|
|
|
*/
|
|
|
|
WA_SET_FIELD_MASKED(GEN7_GT_MODE,
|
|
|
|
GEN6_WIZ_HASHING_MASK,
|
|
|
|
GEN6_WIZ_HASHING_16x4);
|
|
|
|
|
2015-09-25 23:40:37 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static int bdw_init_workarounds(struct intel_engine_cs *engine)
|
2014-08-26 20:44:50 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2015-09-25 23:40:37 +07:00
|
|
|
int ret;
|
2014-08-26 20:44:50 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
ret = gen8_init_workarounds(engine);
|
2015-09-25 23:40:37 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2014-10-09 21:11:47 +07:00
|
|
|
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
|
2015-09-25 23:40:40 +07:00
|
|
|
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
|
2014-08-26 20:44:50 +07:00
|
|
|
|
2014-10-09 21:11:47 +07:00
|
|
|
/* WaDisableDopClockGating:bdw */
|
2014-10-07 21:21:26 +07:00
|
|
|
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
|
|
|
|
DOP_CLOCK_GATING_DISABLE);
|
2014-08-26 20:44:50 +07:00
|
|
|
|
2014-10-07 21:21:26 +07:00
|
|
|
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
|
|
|
|
GEN8_SAMPLER_POWER_BYPASS_DIS);
|
2014-08-26 20:44:50 +07:00
|
|
|
|
2014-10-07 21:21:26 +07:00
|
|
|
WA_SET_BIT_MASKED(HDC_CHICKEN0,
|
2015-02-10 17:31:00 +07:00
|
|
|
/* WaForceContextSaveRestoreNonCoherent:bdw */
|
|
|
|
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
|
|
|
|
/* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
|
2016-05-06 21:40:21 +07:00
|
|
|
(IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
|
2014-08-26 20:44:50 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static int chv_init_workarounds(struct intel_engine_cs *engine)
|
2014-08-27 21:33:12 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2015-09-25 23:40:37 +07:00
|
|
|
int ret;
|
2014-08-27 21:33:12 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
ret = gen8_init_workarounds(engine);
|
2015-09-25 23:40:37 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2014-08-27 21:33:12 +07:00
|
|
|
/* WaDisableThreadStallDopClockGating:chv */
|
2015-09-25 23:40:40 +07:00
|
|
|
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
|
2014-08-27 21:33:12 +07:00
|
|
|
|
2015-01-11 09:02:22 +07:00
|
|
|
/* Improve HiZ throughput on CHV. */
|
|
|
|
WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
|
|
|
|
|
2014-10-07 21:21:26 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static int gen9_init_workarounds(struct intel_engine_cs *engine)
|
2015-02-05 17:47:16 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-01-22 04:43:48 +07:00
|
|
|
int ret;
|
2015-02-05 17:47:18 +07:00
|
|
|
|
2016-06-13 18:15:01 +07:00
|
|
|
/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
|
|
|
|
I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
|
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
|
2015-10-12 17:20:59 +07:00
|
|
|
I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
|
|
|
|
GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
|
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
/* WaDisableKillLogic:bxt,skl,kbl */
|
2015-10-12 17:20:59 +07:00
|
|
|
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
|
|
|
|
ECOCHK_DIS_TLB);
|
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
|
|
|
|
/* WaDisablePartialInstShootdown:skl,bxt,kbl */
|
2015-02-05 17:47:18 +07:00
|
|
|
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
|
2016-03-16 23:13:46 +07:00
|
|
|
FLOW_CONTROL_ENABLE |
|
2015-02-05 17:47:18 +07:00
|
|
|
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
|
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
/* Syncing dependencies between camera and graphics:skl,bxt,kbl */
|
2015-02-05 17:47:20 +07:00
|
|
|
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
|
|
|
|
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
|
|
|
|
|
2015-10-20 19:22:02 +07:00
|
|
|
/* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
|
|
|
|
IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
|
2015-02-12 01:21:44 +07:00
|
|
|
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
|
|
|
|
GEN9_DG_MIRROR_FIX_ENABLE);
|
2015-02-05 17:47:19 +07:00
|
|
|
|
2015-10-20 19:22:02 +07:00
|
|
|
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
|
|
|
|
IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
|
2015-02-10 02:33:11 +07:00
|
|
|
WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
|
|
|
|
GEN9_RHWO_OPTIMIZATION_DISABLE);
|
2015-07-14 21:01:30 +07:00
|
|
|
/*
|
|
|
|
* WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
|
|
|
|
* but we do that in per ctx batchbuffer as there is an issue
|
|
|
|
* with this register not getting restored on ctx restore
|
|
|
|
*/
|
2015-02-10 02:33:11 +07:00
|
|
|
}
|
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
|
|
|
|
/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
|
2016-04-19 21:45:52 +07:00
|
|
|
WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
|
|
|
|
GEN9_ENABLE_YV12_BUGFIX |
|
|
|
|
GEN9_ENABLE_GPGPU_PREEMPTION);
|
2015-02-05 17:47:22 +07:00
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
/* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
|
|
|
|
/* WaDisablePartialResolveInVc:skl,bxt,kbl */
|
2015-09-25 20:33:37 +07:00
|
|
|
WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
|
|
|
|
GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
|
2015-02-10 02:33:17 +07:00
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
/* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
|
2015-02-10 02:33:21 +07:00
|
|
|
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
|
|
|
|
GEN9_CCS_TLB_PREFETCH_ENABLE);
|
|
|
|
|
2015-05-19 19:04:59 +07:00
|
|
|
/* WaDisableMaskBasedCammingInRCC:skl,bxt */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
|
|
|
|
IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
|
2015-03-11 15:54:53 +07:00
|
|
|
WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
|
|
|
|
PIXEL_MASK_CAMMING_DISABLE);
|
|
|
|
|
2016-06-07 21:18:57 +07:00
|
|
|
/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
|
|
|
|
WA_SET_BIT_MASKED(HDC_CHICKEN0,
|
|
|
|
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
|
|
|
|
HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
|
2015-05-19 21:05:42 +07:00
|
|
|
|
2016-06-07 21:18:58 +07:00
|
|
|
/* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
|
|
|
|
* both tied to WaForceContextSaveRestoreNonCoherent
|
|
|
|
* in some hsds for skl. We keep the tie for all gen9. The
|
|
|
|
* documentation is a bit hazy and so we want to get common behaviour,
|
|
|
|
* even though there is no clear evidence we would need both on kbl/bxt.
|
|
|
|
* This area has been source of system hangs so we play it safe
|
|
|
|
* and mimic the skl regardless of what bspec says.
|
|
|
|
*
|
|
|
|
* Use Force Non-Coherent whenever executing a 3D context. This
|
|
|
|
* is a workaround for a possible hang in the unlikely event
|
|
|
|
* a TLB invalidation occurs during a PSD flush.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* WaForceEnableNonCoherent:skl,bxt,kbl */
|
|
|
|
WA_SET_BIT_MASKED(HDC_CHICKEN0,
|
|
|
|
HDC_FORCE_NON_COHERENT);
|
|
|
|
|
|
|
|
/* WaDisableHDCInvalidation:skl,bxt,kbl */
|
|
|
|
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
|
|
|
|
BDW_DISABLE_HDC_INVALIDATION);
|
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
|
|
|
|
if (IS_SKYLAKE(dev_priv) ||
|
|
|
|
IS_KABYLAKE(dev_priv) ||
|
|
|
|
IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
|
2015-09-08 16:31:48 +07:00
|
|
|
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
|
|
|
|
GEN8_SAMPLER_POWER_BYPASS_DIS);
|
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
|
2015-09-08 16:31:52 +07:00
|
|
|
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
|
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
/* WaOCLCoherentLineFlush:skl,bxt,kbl */
|
2016-01-22 04:43:54 +07:00
|
|
|
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
|
|
|
|
GEN8_LQSC_FLUSH_COHERENT_LINES));
|
|
|
|
|
2016-06-06 15:52:49 +07:00
|
|
|
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
|
|
|
|
ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
|
2016-03-16 18:00:37 +07:00
|
|
|
ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
|
2016-01-22 04:43:48 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
|
2016-03-16 18:00:37 +07:00
|
|
|
ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
|
2016-01-22 04:43:49 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2015-02-05 17:47:16 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
|
2015-02-15 01:30:29 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2015-02-15 01:30:29 +07:00
|
|
|
u8 vals[3] = { 0, 0, 0 };
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
|
|
u8 ss;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Only consider slices where one, and only one, subslice has 7
|
|
|
|
* EUs
|
|
|
|
*/
|
2015-12-06 17:26:30 +07:00
|
|
|
if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
|
2015-02-15 01:30:29 +07:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* subslice_7eu[i] != 0 (because of the check above) and
|
|
|
|
* ss_max == 4 (maximum number of subslices possible per slice)
|
|
|
|
*
|
|
|
|
* -> 0 <= ss <= 3;
|
|
|
|
*/
|
|
|
|
ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
|
|
|
|
vals[i] = 3 - ss;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Tune IZ hashing. See intel_device_info_runtime_init() */
|
|
|
|
WA_SET_FIELD_MASKED(GEN7_GT_MODE,
|
|
|
|
GEN9_IZ_HASHING_MASK(2) |
|
|
|
|
GEN9_IZ_HASHING_MASK(1) |
|
|
|
|
GEN9_IZ_HASHING_MASK(0),
|
|
|
|
GEN9_IZ_HASHING(2, vals[2]) |
|
|
|
|
GEN9_IZ_HASHING(1, vals[1]) |
|
|
|
|
GEN9_IZ_HASHING(0, vals[0]));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static int skl_init_workarounds(struct intel_engine_cs *engine)
|
2015-02-10 02:33:15 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2015-09-25 20:33:35 +07:00
|
|
|
int ret;
|
2015-02-10 02:33:16 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
ret = gen9_init_workarounds(engine);
|
2015-09-25 20:33:35 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2015-02-10 02:33:15 +07:00
|
|
|
|
2016-01-22 04:43:53 +07:00
|
|
|
/*
|
|
|
|
* Actual WA is to disable percontext preemption granularity control
|
|
|
|
* until D0 which is the default case so this is equivalent to
|
|
|
|
* !WaDisablePerCtxtPreemptionGranularityControl:skl
|
|
|
|
*/
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
|
2016-01-22 04:43:53 +07:00
|
|
|
I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
|
|
|
|
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
|
|
|
|
}
|
|
|
|
|
2016-06-07 21:19:14 +07:00
|
|
|
if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) {
|
2015-10-12 17:20:59 +07:00
|
|
|
/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
|
|
|
|
I915_WRITE(FF_SLICE_CS_CHICKEN2,
|
|
|
|
_MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
|
|
|
|
* involving this register should also be added to WA batch as required.
|
|
|
|
*/
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
|
2015-10-12 17:20:59 +07:00
|
|
|
/* WaDisableLSQCROPERFforOCL:skl */
|
|
|
|
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
|
|
|
|
GEN8_LQSC_RO_PERF_DIS);
|
|
|
|
|
|
|
|
/* WaEnableGapsTsvCreditFix:skl */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
|
2015-10-12 17:20:59 +07:00
|
|
|
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
|
|
|
|
GEN9_GAPS_TSV_CREDIT_DISABLE));
|
|
|
|
}
|
|
|
|
|
2015-02-10 02:33:16 +07:00
|
|
|
/* WaDisablePowerCompilerClockGating:skl */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
|
2015-02-10 02:33:16 +07:00
|
|
|
WA_SET_BIT_MASKED(HIZ_CHICKEN,
|
|
|
|
BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
|
|
|
|
|
2015-10-20 19:22:02 +07:00
|
|
|
/* WaBarrierPerformanceFixDisable:skl */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
|
2015-06-02 19:37:35 +07:00
|
|
|
WA_SET_BIT_MASKED(HDC_CHICKEN0,
|
|
|
|
HDC_FENCE_DEST_SLM_DISABLE |
|
|
|
|
HDC_BARRIER_PERFORMANCE_DISABLE);
|
|
|
|
|
2015-08-06 20:51:00 +07:00
|
|
|
/* WaDisableSbeCacheDispatchPortSharing:skl */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
|
2015-08-06 20:51:00 +07:00
|
|
|
WA_SET_BIT_MASKED(
|
|
|
|
GEN7_HALF_SLICE_CHICKEN1,
|
|
|
|
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
|
|
|
|
|
2016-06-07 21:18:53 +07:00
|
|
|
/* WaDisableGafsUnitClkGating:skl */
|
|
|
|
WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
|
|
|
|
|
2016-01-22 04:43:52 +07:00
|
|
|
/* WaDisableLSQCROPERFforOCL:skl */
|
2016-03-16 18:00:37 +07:00
|
|
|
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
|
2016-01-22 04:43:52 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
return skl_tune_iz_hashing(engine);
|
2014-10-07 21:21:26 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static int bxt_init_workarounds(struct intel_engine_cs *engine)
|
2015-03-17 16:39:38 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2015-09-25 20:33:35 +07:00
|
|
|
int ret;
|
2015-04-10 19:12:24 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
ret = gen9_init_workarounds(engine);
|
2015-09-25 20:33:35 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2015-03-17 16:39:38 +07:00
|
|
|
|
2015-10-12 17:20:59 +07:00
|
|
|
/* WaStoreMultiplePTEenable:bxt */
|
|
|
|
/* This is a requirement according to Hardware specification */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
|
2015-10-12 17:20:59 +07:00
|
|
|
I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
|
|
|
|
|
|
|
|
/* WaSetClckGatingDisableMedia:bxt */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
|
2015-10-12 17:20:59 +07:00
|
|
|
I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
|
|
|
|
~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
|
|
|
|
}
|
|
|
|
|
2015-04-10 19:12:24 +07:00
|
|
|
/* WaDisableThreadStallDopClockGating:bxt */
|
|
|
|
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
|
|
|
|
STALL_DOP_GATING_DISABLE);
|
|
|
|
|
2016-06-03 17:16:10 +07:00
|
|
|
/* WaDisablePooledEuLoadBalancingFix:bxt */
|
|
|
|
if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
|
|
|
|
WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
|
|
|
|
GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
|
|
|
|
}
|
|
|
|
|
2015-04-10 19:12:25 +07:00
|
|
|
/* WaDisableSbeCacheDispatchPortSharing:bxt */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
|
2015-04-10 19:12:25 +07:00
|
|
|
WA_SET_BIT_MASKED(
|
|
|
|
GEN7_HALF_SLICE_CHICKEN1,
|
|
|
|
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
|
|
|
|
}
|
|
|
|
|
2016-01-22 04:43:50 +07:00
|
|
|
/* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
|
|
|
|
/* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
|
|
|
|
/* WaDisableObjectLevelPreemtionForInstanceId:bxt */
|
2016-01-22 04:43:51 +07:00
|
|
|
/* WaDisableLSQCROPERFforOCL:bxt */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
|
2016-03-16 18:00:37 +07:00
|
|
|
ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
|
2016-01-22 04:43:50 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2016-01-22 04:43:51 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
|
2016-01-22 04:43:51 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2016-01-22 04:43:50 +07:00
|
|
|
}
|
|
|
|
|
2016-04-22 15:46:01 +07:00
|
|
|
/* WaProgramL3SqcReg1DefaultForPerf:bxt */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
|
2016-05-03 19:54:20 +07:00
|
|
|
I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
|
|
|
|
L3_HIGH_PRIO_CREDITS(2));
|
2016-04-22 15:46:01 +07:00
|
|
|
|
2016-06-07 21:19:07 +07:00
|
|
|
/* WaInsertDummyPushConstPs:bxt */
|
|
|
|
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
|
|
|
|
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
|
|
|
|
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
|
|
|
|
|
2015-03-17 16:39:38 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
static int kbl_init_workarounds(struct intel_engine_cs *engine)
|
|
|
|
{
|
2016-06-07 21:18:59 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-06-07 21:18:54 +07:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = gen9_init_workarounds(engine);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-06-07 21:18:59 +07:00
|
|
|
/* WaEnableGapsTsvCreditFix:kbl */
|
|
|
|
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
|
|
|
|
GEN9_GAPS_TSV_CREDIT_DISABLE));
|
|
|
|
|
2016-06-07 21:19:06 +07:00
|
|
|
/* WaDisableDynamicCreditSharing:kbl */
|
|
|
|
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
|
|
|
|
WA_SET_BIT(GAMT_CHKN_BIT_REG,
|
|
|
|
GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
|
|
|
|
|
2016-06-07 21:19:00 +07:00
|
|
|
/* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
|
|
|
|
if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
|
|
|
|
WA_SET_BIT_MASKED(HDC_CHICKEN0,
|
|
|
|
HDC_FENCE_DEST_SLM_DISABLE);
|
|
|
|
|
2016-06-07 21:19:03 +07:00
|
|
|
/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
|
|
|
|
* involving this register should also be added to WA batch as required.
|
|
|
|
*/
|
|
|
|
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
|
|
|
|
/* WaDisableLSQCROPERFforOCL:kbl */
|
|
|
|
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
|
|
|
|
GEN8_LQSC_RO_PERF_DIS);
|
|
|
|
|
2016-06-07 21:19:07 +07:00
|
|
|
/* WaInsertDummyPushConstPs:kbl */
|
|
|
|
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
|
|
|
|
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
|
|
|
|
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
|
|
|
|
|
2016-06-07 21:19:11 +07:00
|
|
|
/* WaDisableGafsUnitClkGating:kbl */
|
|
|
|
WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
|
|
|
|
|
2016-06-07 21:19:12 +07:00
|
|
|
/* WaDisableSbeCacheDispatchPortSharing:kbl */
|
|
|
|
WA_SET_BIT_MASKED(
|
|
|
|
GEN7_HALF_SLICE_CHICKEN1,
|
|
|
|
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
|
|
|
|
|
2016-06-07 21:19:03 +07:00
|
|
|
/* WaDisableLSQCROPERFforOCL:kbl */
|
|
|
|
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
int init_workarounds_ring(struct intel_engine_cs *engine)
|
2014-10-07 21:21:26 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2014-10-07 21:21:26 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
WARN_ON(engine->id != RCS);
|
2014-10-07 21:21:26 +07:00
|
|
|
|
|
|
|
dev_priv->workarounds.count = 0;
|
2016-01-22 04:43:47 +07:00
|
|
|
dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
|
2014-10-07 21:21:26 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_BROADWELL(dev_priv))
|
2016-03-16 18:00:37 +07:00
|
|
|
return bdw_init_workarounds(engine);
|
2014-10-07 21:21:26 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_CHERRYVIEW(dev_priv))
|
2016-03-16 18:00:37 +07:00
|
|
|
return chv_init_workarounds(engine);
|
2014-08-27 21:33:12 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_SKYLAKE(dev_priv))
|
2016-03-16 18:00:37 +07:00
|
|
|
return skl_init_workarounds(engine);
|
2015-03-17 16:39:38 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_BROXTON(dev_priv))
|
2016-03-16 18:00:37 +07:00
|
|
|
return bxt_init_workarounds(engine);
|
2015-02-05 17:47:16 +07:00
|
|
|
|
2016-06-07 21:18:54 +07:00
|
|
|
if (IS_KABYLAKE(dev_priv))
|
|
|
|
return kbl_init_workarounds(engine);
|
|
|
|
|
2014-08-27 21:33:12 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static int init_render_ring(struct intel_engine_cs *engine)
|
2010-05-21 08:08:55 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-03-16 18:00:37 +07:00
|
|
|
int ret = init_ring_common(engine);
|
2014-06-20 00:07:15 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-08-30 15:12:42 +07:00
|
|
|
|
2014-03-25 19:31:50 +07:00
|
|
|
/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
|
2016-05-10 16:57:08 +07:00
|
|
|
if (IS_GEN(dev_priv, 4, 6))
|
2012-04-24 19:04:12 +07:00
|
|
|
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
|
2013-01-20 23:11:20 +07:00
|
|
|
|
|
|
|
/* We need to disable the AsyncFlip performance optimisations in order
|
|
|
|
* to use MI_WAIT_FOR_EVENT within the CS. It should already be
|
|
|
|
* programmed to '1' on all products.
|
2013-05-04 00:48:11 +07:00
|
|
|
*
|
2015-06-02 19:37:37 +07:00
|
|
|
* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
|
2013-01-20 23:11:20 +07:00
|
|
|
*/
|
2016-05-10 16:57:08 +07:00
|
|
|
if (IS_GEN(dev_priv, 6, 7))
|
2013-01-20 23:11:20 +07:00
|
|
|
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
|
|
|
|
|
2013-01-20 23:33:32 +07:00
|
|
|
/* Required for the hardware to program scanline values for waiting */
|
2014-03-25 00:30:04 +07:00
|
|
|
/* WaEnableFlushTlbInvalidationMode:snb */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_GEN6(dev_priv))
|
2013-01-20 23:33:32 +07:00
|
|
|
I915_WRITE(GFX_MODE,
|
2014-03-22 00:18:54 +07:00
|
|
|
_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
|
2013-01-20 23:33:32 +07:00
|
|
|
|
2014-03-25 00:30:04 +07:00
|
|
|
/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_GEN7(dev_priv))
|
2013-01-20 23:11:20 +07:00
|
|
|
I915_WRITE(GFX_MODE_GEN7,
|
2014-03-25 00:30:04 +07:00
|
|
|
_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
|
2013-01-20 23:11:20 +07:00
|
|
|
_MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
|
2010-10-27 18:18:21 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_GEN6(dev_priv)) {
|
2012-04-28 02:44:41 +07:00
|
|
|
/* From the Sandybridge PRM, volume 1 part 3, page 24:
|
|
|
|
* "If this bit is set, STCunit will have LRA as replacement
|
|
|
|
* policy. [...] This bit must be reset. LRA replacement
|
|
|
|
* policy is not supported."
|
|
|
|
*/
|
|
|
|
I915_WRITE(CACHE_MODE_0,
|
2012-05-08 18:39:59 +07:00
|
|
|
_MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
|
2011-12-13 10:21:58 +07:00
|
|
|
}
|
|
|
|
|
2016-05-10 16:57:08 +07:00
|
|
|
if (IS_GEN(dev_priv, 6, 7))
|
2012-04-24 19:04:12 +07:00
|
|
|
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
|
2011-12-13 10:21:58 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (HAS_L3_DPF(dev_priv))
|
|
|
|
I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
|
2012-05-26 06:56:23 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
return init_workarounds_ring(engine);
|
2010-05-21 08:08:55 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static void render_ring_cleanup(struct intel_engine_cs *engine)
|
2010-12-15 16:56:50 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2014-06-30 23:53:37 +07:00
|
|
|
|
|
|
|
if (dev_priv->semaphore_obj) {
|
|
|
|
i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
|
|
|
|
drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
|
|
|
|
dev_priv->semaphore_obj = NULL;
|
|
|
|
}
|
2012-12-17 22:21:27 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
intel_fini_pipe_control(engine);
|
2010-12-15 16:56:50 +07:00
|
|
|
}
|
|
|
|
|
2015-05-29 23:44:05 +07:00
|
|
|
static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
|
2014-06-30 23:53:37 +07:00
|
|
|
unsigned int num_dwords)
|
|
|
|
{
|
|
|
|
#define MBOX_UPDATE_DWORDS 8
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *signaller = signaller_req->engine;
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = signaller_req->i915;
|
2014-06-30 23:53:37 +07:00
|
|
|
struct intel_engine_cs *waiter;
|
2016-03-24 01:19:53 +07:00
|
|
|
enum intel_engine_id id;
|
|
|
|
int ret, num_rings;
|
2014-06-30 23:53:37 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
|
2014-06-30 23:53:37 +07:00
|
|
|
num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
|
|
|
|
#undef MBOX_UPDATE_DWORDS
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(signaller_req, num_dwords);
|
2014-06-30 23:53:37 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-24 01:19:53 +07:00
|
|
|
for_each_engine_id(waiter, dev_priv, id) {
|
2014-11-25 01:49:29 +07:00
|
|
|
u32 seqno;
|
2016-03-24 01:19:53 +07:00
|
|
|
u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
|
2014-06-30 23:53:37 +07:00
|
|
|
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
|
|
|
|
continue;
|
|
|
|
|
2015-05-29 23:44:05 +07:00
|
|
|
seqno = i915_gem_request_get_seqno(signaller_req);
|
2014-06-30 23:53:37 +07:00
|
|
|
intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
|
|
|
|
intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
|
|
|
|
PIPE_CONTROL_QW_WRITE |
|
2016-04-29 19:18:24 +07:00
|
|
|
PIPE_CONTROL_CS_STALL);
|
2014-06-30 23:53:37 +07:00
|
|
|
intel_ring_emit(signaller, lower_32_bits(gtt_offset));
|
|
|
|
intel_ring_emit(signaller, upper_32_bits(gtt_offset));
|
2014-11-25 01:49:29 +07:00
|
|
|
intel_ring_emit(signaller, seqno);
|
2014-06-30 23:53:37 +07:00
|
|
|
intel_ring_emit(signaller, 0);
|
|
|
|
intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
|
2016-04-29 19:18:23 +07:00
|
|
|
MI_SEMAPHORE_TARGET(waiter->hw_id));
|
2014-06-30 23:53:37 +07:00
|
|
|
intel_ring_emit(signaller, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-05-29 23:44:05 +07:00
|
|
|
static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
|
2014-06-30 23:53:37 +07:00
|
|
|
unsigned int num_dwords)
|
|
|
|
{
|
|
|
|
#define MBOX_UPDATE_DWORDS 6
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *signaller = signaller_req->engine;
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = signaller_req->i915;
|
2014-06-30 23:53:37 +07:00
|
|
|
struct intel_engine_cs *waiter;
|
2016-03-24 01:19:53 +07:00
|
|
|
enum intel_engine_id id;
|
|
|
|
int ret, num_rings;
|
2014-06-30 23:53:37 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
|
2014-06-30 23:53:37 +07:00
|
|
|
num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
|
|
|
|
#undef MBOX_UPDATE_DWORDS
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(signaller_req, num_dwords);
|
2014-06-30 23:53:37 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-24 01:19:53 +07:00
|
|
|
for_each_engine_id(waiter, dev_priv, id) {
|
2014-11-25 01:49:29 +07:00
|
|
|
u32 seqno;
|
2016-03-24 01:19:53 +07:00
|
|
|
u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
|
2014-06-30 23:53:37 +07:00
|
|
|
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
|
|
|
|
continue;
|
|
|
|
|
2015-05-29 23:44:05 +07:00
|
|
|
seqno = i915_gem_request_get_seqno(signaller_req);
|
2014-06-30 23:53:37 +07:00
|
|
|
intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
|
|
|
|
MI_FLUSH_DW_OP_STOREDW);
|
|
|
|
intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
|
|
|
|
MI_FLUSH_DW_USE_GTT);
|
|
|
|
intel_ring_emit(signaller, upper_32_bits(gtt_offset));
|
2014-11-25 01:49:29 +07:00
|
|
|
intel_ring_emit(signaller, seqno);
|
2014-06-30 23:53:37 +07:00
|
|
|
intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
|
2016-04-29 19:18:23 +07:00
|
|
|
MI_SEMAPHORE_TARGET(waiter->hw_id));
|
2014-06-30 23:53:37 +07:00
|
|
|
intel_ring_emit(signaller, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-05-29 23:44:05 +07:00
|
|
|
static int gen6_signal(struct drm_i915_gem_request *signaller_req,
|
2014-04-30 04:52:30 +07:00
|
|
|
unsigned int num_dwords)
|
2010-12-04 18:30:53 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *signaller = signaller_req->engine;
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = signaller_req->i915;
|
2014-05-22 20:13:33 +07:00
|
|
|
struct intel_engine_cs *useless;
|
2016-03-24 01:19:53 +07:00
|
|
|
enum intel_engine_id id;
|
|
|
|
int ret, num_rings;
|
2014-04-30 04:52:29 +07:00
|
|
|
|
2014-06-30 23:53:35 +07:00
|
|
|
#define MBOX_UPDATE_DWORDS 3
|
2016-05-06 21:40:21 +07:00
|
|
|
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
|
2014-06-30 23:53:35 +07:00
|
|
|
num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
|
|
|
|
#undef MBOX_UPDATE_DWORDS
|
2014-04-30 04:52:30 +07:00
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(signaller_req, num_dwords);
|
2014-04-30 04:52:30 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-24 01:19:53 +07:00
|
|
|
for_each_engine_id(useless, dev_priv, id) {
|
|
|
|
i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
|
|
|
|
if (i915_mmio_reg_valid(mbox_reg)) {
|
2015-05-29 23:44:05 +07:00
|
|
|
u32 seqno = i915_gem_request_get_seqno(signaller_req);
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
|
2014-04-30 04:52:29 +07:00
|
|
|
intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
|
2015-11-05 04:20:07 +07:00
|
|
|
intel_ring_emit_reg(signaller, mbox_reg);
|
2014-11-25 01:49:29 +07:00
|
|
|
intel_ring_emit(signaller, seqno);
|
2014-04-30 04:52:29 +07:00
|
|
|
}
|
|
|
|
}
|
2014-04-30 04:52:30 +07:00
|
|
|
|
2014-06-30 23:53:35 +07:00
|
|
|
/* If num_dwords was rounded, make sure the tail pointer is correct */
|
|
|
|
if (num_rings % 2 == 0)
|
|
|
|
intel_ring_emit(signaller, MI_NOOP);
|
|
|
|
|
2014-04-30 04:52:30 +07:00
|
|
|
return 0;
|
2010-12-04 18:30:53 +07:00
|
|
|
}
|
|
|
|
|
2011-09-15 10:32:47 +07:00
|
|
|
/**
|
|
|
|
* gen6_add_request - Update the semaphore mailbox registers
|
2015-05-29 23:44:00 +07:00
|
|
|
*
|
|
|
|
* @request - request to write to the ring
|
2011-09-15 10:32:47 +07:00
|
|
|
*
|
|
|
|
* Update the mailbox registers in the *other* rings with the current seqno.
|
|
|
|
* This acts like a signal in the canonical semaphore.
|
|
|
|
*/
|
2010-12-04 18:30:53 +07:00
|
|
|
static int
|
2015-05-29 23:44:00 +07:00
|
|
|
gen6_add_request(struct drm_i915_gem_request *req)
|
2010-12-04 18:30:53 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2014-04-30 04:52:30 +07:00
|
|
|
int ret;
|
2013-12-17 11:50:38 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
if (engine->semaphore.signal)
|
|
|
|
ret = engine->semaphore.signal(req, 4);
|
2014-06-30 23:53:36 +07:00
|
|
|
else
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 4);
|
2014-06-30 23:53:36 +07:00
|
|
|
|
2010-12-04 18:30:53 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
|
|
|
|
intel_ring_emit(engine,
|
|
|
|
I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
|
|
|
|
intel_ring_emit(engine, i915_gem_request_get_seqno(req));
|
|
|
|
intel_ring_emit(engine, MI_USER_INTERRUPT);
|
|
|
|
__intel_ring_advance(engine);
|
2010-12-04 18:30:53 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-04-29 19:18:21 +07:00
|
|
|
static int
|
|
|
|
gen8_render_add_request(struct drm_i915_gem_request *req)
|
|
|
|
{
|
|
|
|
struct intel_engine_cs *engine = req->engine;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (engine->semaphore.signal)
|
|
|
|
ret = engine->semaphore.signal(req, 8);
|
|
|
|
else
|
|
|
|
ret = intel_ring_begin(req, 8);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
|
|
|
|
intel_ring_emit(engine, (PIPE_CONTROL_GLOBAL_GTT_IVB |
|
|
|
|
PIPE_CONTROL_CS_STALL |
|
|
|
|
PIPE_CONTROL_QW_WRITE));
|
|
|
|
intel_ring_emit(engine, intel_hws_seqno_address(req->engine));
|
|
|
|
intel_ring_emit(engine, 0);
|
|
|
|
intel_ring_emit(engine, i915_gem_request_get_seqno(req));
|
|
|
|
/* We're thrashing one dword of HWS. */
|
|
|
|
intel_ring_emit(engine, 0);
|
|
|
|
intel_ring_emit(engine, MI_USER_INTERRUPT);
|
|
|
|
intel_ring_emit(engine, MI_NOOP);
|
|
|
|
__intel_ring_advance(engine);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
|
2012-12-10 20:41:48 +07:00
|
|
|
u32 seqno)
|
|
|
|
{
|
|
|
|
return dev_priv->last_seqno < seqno;
|
|
|
|
}
|
|
|
|
|
2011-09-15 10:32:47 +07:00
|
|
|
/**
|
|
|
|
* intel_ring_sync - sync the waiter to the signaller on seqno
|
|
|
|
*
|
|
|
|
* @waiter - ring that is waiting
|
|
|
|
* @signaller - ring which has, or will signal
|
|
|
|
* @seqno - seqno which the waiter will block on
|
|
|
|
*/
|
2014-06-30 23:53:38 +07:00
|
|
|
|
|
|
|
static int
|
2015-05-29 23:44:04 +07:00
|
|
|
gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
|
2014-06-30 23:53:38 +07:00
|
|
|
struct intel_engine_cs *signaller,
|
|
|
|
u32 seqno)
|
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *waiter = waiter_req->engine;
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = waiter_req->i915;
|
2016-04-29 19:18:25 +07:00
|
|
|
struct i915_hw_ppgtt *ppgtt;
|
2014-06-30 23:53:38 +07:00
|
|
|
int ret;
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(waiter_req, 4);
|
2014-06-30 23:53:38 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
|
|
|
|
MI_SEMAPHORE_GLOBAL_GTT |
|
|
|
|
MI_SEMAPHORE_SAD_GTE_SDD);
|
|
|
|
intel_ring_emit(waiter, seqno);
|
|
|
|
intel_ring_emit(waiter,
|
|
|
|
lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
|
|
|
|
intel_ring_emit(waiter,
|
|
|
|
upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
|
|
|
|
intel_ring_advance(waiter);
|
2016-04-29 19:18:25 +07:00
|
|
|
|
|
|
|
/* When the !RCS engines idle waiting upon a semaphore, they lose their
|
|
|
|
* pagetables and we must reload them before executing the batch.
|
|
|
|
* We do this on the i915_switch_context() following the wait and
|
|
|
|
* before the dispatch.
|
|
|
|
*/
|
|
|
|
ppgtt = waiter_req->ctx->ppgtt;
|
|
|
|
if (ppgtt && waiter_req->engine->id != RCS)
|
|
|
|
ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine);
|
2014-06-30 23:53:38 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-09-15 10:32:47 +07:00
|
|
|
static int
|
2015-05-29 23:44:04 +07:00
|
|
|
gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
|
2014-05-22 20:13:33 +07:00
|
|
|
struct intel_engine_cs *signaller,
|
2012-04-12 03:12:52 +07:00
|
|
|
u32 seqno)
|
2010-12-04 18:30:53 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *waiter = waiter_req->engine;
|
2011-09-15 10:32:47 +07:00
|
|
|
u32 dw1 = MI_SEMAPHORE_MBOX |
|
|
|
|
MI_SEMAPHORE_COMPARE |
|
|
|
|
MI_SEMAPHORE_REGISTER;
|
2014-04-30 04:52:28 +07:00
|
|
|
u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
|
|
|
|
int ret;
|
2010-12-04 18:30:53 +07:00
|
|
|
|
2012-04-12 01:18:21 +07:00
|
|
|
/* Throughout all of the GEM code, seqno passed implies our current
|
|
|
|
* seqno is >= the last seqno executed. However for hardware the
|
|
|
|
* comparison is strictly greater than.
|
|
|
|
*/
|
|
|
|
seqno -= 1;
|
|
|
|
|
2014-04-30 04:52:28 +07:00
|
|
|
WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
|
2012-04-12 03:12:52 +07:00
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(waiter_req, 4);
|
2010-12-04 18:30:53 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2012-12-10 20:41:48 +07:00
|
|
|
/* If seqno wrap happened, omit the wait with no-ops */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
|
2014-04-30 04:52:28 +07:00
|
|
|
intel_ring_emit(waiter, dw1 | wait_mbox);
|
2012-12-10 20:41:48 +07:00
|
|
|
intel_ring_emit(waiter, seqno);
|
|
|
|
intel_ring_emit(waiter, 0);
|
|
|
|
intel_ring_emit(waiter, MI_NOOP);
|
|
|
|
} else {
|
|
|
|
intel_ring_emit(waiter, MI_NOOP);
|
|
|
|
intel_ring_emit(waiter, MI_NOOP);
|
|
|
|
intel_ring_emit(waiter, MI_NOOP);
|
|
|
|
intel_ring_emit(waiter, MI_NOOP);
|
|
|
|
}
|
2011-09-15 10:32:47 +07:00
|
|
|
intel_ring_advance(waiter);
|
2010-12-04 18:30:53 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-12-15 16:56:50 +07:00
|
|
|
#define PIPE_CONTROL_FLUSH(ring__, addr__) \
|
|
|
|
do { \
|
2011-10-12 04:41:08 +07:00
|
|
|
intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
|
|
|
|
PIPE_CONTROL_DEPTH_STALL); \
|
2010-12-15 16:56:50 +07:00
|
|
|
intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
|
|
|
|
intel_ring_emit(ring__, 0); \
|
|
|
|
intel_ring_emit(ring__, 0); \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
static int
|
2015-05-29 23:44:00 +07:00
|
|
|
pc_render_add_request(struct drm_i915_gem_request *req)
|
2010-12-15 16:56:50 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2016-03-16 18:00:36 +07:00
|
|
|
u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
|
2010-12-15 16:56:50 +07:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
|
|
|
|
* incoherent with writes to memory, i.e. completely fubar,
|
|
|
|
* so we need to use PIPE_NOTIFY instead.
|
|
|
|
*
|
|
|
|
* However, we also need to workaround the qword write
|
|
|
|
* incoherence by flushing the 6 PIPE_NOTIFY buffers out to
|
|
|
|
* memory before requesting an interrupt.
|
|
|
|
*/
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 32);
|
2010-12-15 16:56:50 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine,
|
|
|
|
GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
|
2011-10-12 04:41:09 +07:00
|
|
|
PIPE_CONTROL_WRITE_FLUSH |
|
|
|
|
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine,
|
|
|
|
engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
|
|
|
|
intel_ring_emit(engine, i915_gem_request_get_seqno(req));
|
|
|
|
intel_ring_emit(engine, 0);
|
|
|
|
PIPE_CONTROL_FLUSH(engine, scratch_addr);
|
2014-04-09 15:19:40 +07:00
|
|
|
scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
|
2016-03-16 18:00:36 +07:00
|
|
|
PIPE_CONTROL_FLUSH(engine, scratch_addr);
|
2014-04-09 15:19:40 +07:00
|
|
|
scratch_addr += 2 * CACHELINE_BYTES;
|
2016-03-16 18:00:36 +07:00
|
|
|
PIPE_CONTROL_FLUSH(engine, scratch_addr);
|
2014-04-09 15:19:40 +07:00
|
|
|
scratch_addr += 2 * CACHELINE_BYTES;
|
2016-03-16 18:00:36 +07:00
|
|
|
PIPE_CONTROL_FLUSH(engine, scratch_addr);
|
2014-04-09 15:19:40 +07:00
|
|
|
scratch_addr += 2 * CACHELINE_BYTES;
|
2016-03-16 18:00:36 +07:00
|
|
|
PIPE_CONTROL_FLUSH(engine, scratch_addr);
|
2014-04-09 15:19:40 +07:00
|
|
|
scratch_addr += 2 * CACHELINE_BYTES;
|
2016-03-16 18:00:36 +07:00
|
|
|
PIPE_CONTROL_FLUSH(engine, scratch_addr);
|
2012-02-15 18:25:36 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine,
|
|
|
|
GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
|
2011-10-12 04:41:09 +07:00
|
|
|
PIPE_CONTROL_WRITE_FLUSH |
|
|
|
|
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
|
2010-12-15 16:56:50 +07:00
|
|
|
PIPE_CONTROL_NOTIFY);
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine,
|
|
|
|
engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
|
|
|
|
intel_ring_emit(engine, i915_gem_request_get_seqno(req));
|
|
|
|
intel_ring_emit(engine, 0);
|
|
|
|
__intel_ring_advance(engine);
|
2010-12-15 16:56:50 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-04-09 16:57:54 +07:00
|
|
|
static void
|
|
|
|
gen6_seqno_barrier(struct intel_engine_cs *engine)
|
2012-12-14 22:01:25 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-04-27 15:02:01 +07:00
|
|
|
|
2012-12-14 22:01:25 +07:00
|
|
|
/* Workaround to force correct ordering between irq and seqno writes on
|
|
|
|
* ivb (and maybe also on snb) by reading from a CS register (like
|
2016-04-09 16:57:53 +07:00
|
|
|
* ACTHD) before reading the status page.
|
|
|
|
*
|
|
|
|
* Note that this effectively stalls the read by the time it takes to
|
|
|
|
* do a memory transaction, which more or less ensures that the write
|
|
|
|
* from the GPU has sufficient time to invalidate the CPU cacheline.
|
|
|
|
* Alternatively we could delay the interrupt from the CS ring to give
|
|
|
|
* the write time to land, but that would incur a delay after every
|
|
|
|
* batch i.e. much more frequent than a delay when waiting for the
|
|
|
|
* interrupt (with the same net latency).
|
2016-04-27 15:02:01 +07:00
|
|
|
*
|
|
|
|
* Also note that to prevent whole machine hangs on gen7, we have to
|
|
|
|
* take the spinlock to guard against concurrent cacheline access.
|
2016-04-09 16:57:53 +07:00
|
|
|
*/
|
2016-04-27 15:02:01 +07:00
|
|
|
spin_lock_irq(&dev_priv->uncore.lock);
|
2016-04-09 16:57:54 +07:00
|
|
|
POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
|
2016-04-27 15:02:01 +07:00
|
|
|
spin_unlock_irq(&dev_priv->uncore.lock);
|
2012-12-14 22:01:25 +07:00
|
|
|
}
|
|
|
|
|
2010-05-21 08:08:55 +07:00
|
|
|
static u32
|
2016-04-09 16:57:54 +07:00
|
|
|
ring_get_seqno(struct intel_engine_cs *engine)
|
2010-05-21 08:08:55 +07:00
|
|
|
{
|
2016-03-16 18:00:37 +07:00
|
|
|
return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
|
2010-12-04 18:30:53 +07:00
|
|
|
}
|
|
|
|
|
2012-12-19 16:13:05 +07:00
|
|
|
static void
|
2016-03-16 18:00:37 +07:00
|
|
|
ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
|
2012-12-19 16:13:05 +07:00
|
|
|
{
|
2016-03-16 18:00:37 +07:00
|
|
|
intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
|
2012-12-19 16:13:05 +07:00
|
|
|
}
|
|
|
|
|
2010-12-15 16:56:50 +07:00
|
|
|
static u32
|
2016-04-09 16:57:54 +07:00
|
|
|
pc_render_get_seqno(struct intel_engine_cs *engine)
|
2010-12-15 16:56:50 +07:00
|
|
|
{
|
2016-03-16 18:00:37 +07:00
|
|
|
return engine->scratch.cpu_page[0];
|
2010-12-15 16:56:50 +07:00
|
|
|
}
|
|
|
|
|
2012-12-19 16:13:05 +07:00
|
|
|
static void
|
2016-03-16 18:00:37 +07:00
|
|
|
pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
|
2012-12-19 16:13:05 +07:00
|
|
|
{
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->scratch.cpu_page[0] = seqno;
|
2012-12-19 16:13:05 +07:00
|
|
|
}
|
|
|
|
|
2012-04-12 03:12:54 +07:00
|
|
|
static bool
|
2016-03-16 18:00:37 +07:00
|
|
|
gen5_ring_get_irq(struct intel_engine_cs *engine)
|
2012-04-12 03:12:54 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2012-04-25 03:48:47 +07:00
|
|
|
unsigned long flags;
|
2012-04-12 03:12:54 +07:00
|
|
|
|
2014-09-15 16:38:57 +07:00
|
|
|
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
|
2012-04-12 03:12:54 +07:00
|
|
|
return false;
|
|
|
|
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
2016-03-16 18:00:37 +07:00
|
|
|
if (engine->irq_refcount++ == 0)
|
|
|
|
gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
2012-04-12 03:12:54 +07:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-03-16 18:00:37 +07:00
|
|
|
gen5_ring_put_irq(struct intel_engine_cs *engine)
|
2012-04-12 03:12:54 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2012-04-25 03:48:47 +07:00
|
|
|
unsigned long flags;
|
2012-04-12 03:12:54 +07:00
|
|
|
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
2016-03-16 18:00:37 +07:00
|
|
|
if (--engine->irq_refcount == 0)
|
|
|
|
gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
2012-04-12 03:12:54 +07:00
|
|
|
}
|
|
|
|
|
2010-12-13 23:54:50 +07:00
|
|
|
static bool
|
2016-03-16 18:00:37 +07:00
|
|
|
i9xx_ring_get_irq(struct intel_engine_cs *engine)
|
2010-05-22 03:26:39 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2012-04-25 03:48:47 +07:00
|
|
|
unsigned long flags;
|
2010-05-22 03:26:39 +07:00
|
|
|
|
2014-09-15 16:38:57 +07:00
|
|
|
if (!intel_irqs_enabled(dev_priv))
|
2010-12-13 23:54:50 +07:00
|
|
|
return false;
|
|
|
|
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
2016-03-16 18:00:37 +07:00
|
|
|
if (engine->irq_refcount++ == 0) {
|
|
|
|
dev_priv->irq_mask &= ~engine->irq_enable_mask;
|
2012-04-12 03:12:59 +07:00
|
|
|
I915_WRITE(IMR, dev_priv->irq_mask);
|
|
|
|
POSTING_READ(IMR);
|
|
|
|
}
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
2010-12-13 23:54:50 +07:00
|
|
|
|
|
|
|
return true;
|
2010-05-22 03:26:39 +07:00
|
|
|
}
|
|
|
|
|
2010-05-21 08:08:55 +07:00
|
|
|
static void
|
2016-03-16 18:00:37 +07:00
|
|
|
i9xx_ring_put_irq(struct intel_engine_cs *engine)
|
2010-05-22 03:26:39 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2012-04-25 03:48:47 +07:00
|
|
|
unsigned long flags;
|
2010-05-22 03:26:39 +07:00
|
|
|
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
2016-03-16 18:00:37 +07:00
|
|
|
if (--engine->irq_refcount == 0) {
|
|
|
|
dev_priv->irq_mask |= engine->irq_enable_mask;
|
2012-04-12 03:12:59 +07:00
|
|
|
I915_WRITE(IMR, dev_priv->irq_mask);
|
|
|
|
POSTING_READ(IMR);
|
|
|
|
}
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
2010-05-22 03:26:39 +07:00
|
|
|
}
|
|
|
|
|
2012-04-23 03:13:57 +07:00
|
|
|
static bool
|
2016-03-16 18:00:37 +07:00
|
|
|
i8xx_ring_get_irq(struct intel_engine_cs *engine)
|
2012-04-23 03:13:57 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2012-04-25 03:48:47 +07:00
|
|
|
unsigned long flags;
|
2012-04-23 03:13:57 +07:00
|
|
|
|
2014-09-15 16:38:57 +07:00
|
|
|
if (!intel_irqs_enabled(dev_priv))
|
2012-04-23 03:13:57 +07:00
|
|
|
return false;
|
|
|
|
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
2016-03-16 18:00:37 +07:00
|
|
|
if (engine->irq_refcount++ == 0) {
|
|
|
|
dev_priv->irq_mask &= ~engine->irq_enable_mask;
|
2012-04-23 03:13:57 +07:00
|
|
|
I915_WRITE16(IMR, dev_priv->irq_mask);
|
|
|
|
POSTING_READ16(IMR);
|
|
|
|
}
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
2012-04-23 03:13:57 +07:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-03-16 18:00:37 +07:00
|
|
|
i8xx_ring_put_irq(struct intel_engine_cs *engine)
|
2012-04-23 03:13:57 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2012-04-25 03:48:47 +07:00
|
|
|
unsigned long flags;
|
2012-04-23 03:13:57 +07:00
|
|
|
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
2016-03-16 18:00:37 +07:00
|
|
|
if (--engine->irq_refcount == 0) {
|
|
|
|
dev_priv->irq_mask |= engine->irq_enable_mask;
|
2012-04-23 03:13:57 +07:00
|
|
|
I915_WRITE16(IMR, dev_priv->irq_mask);
|
|
|
|
POSTING_READ16(IMR);
|
|
|
|
}
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
2012-04-23 03:13:57 +07:00
|
|
|
}
|
|
|
|
|
2011-01-05 00:34:02 +07:00
|
|
|
static int
|
2015-05-29 23:43:57 +07:00
|
|
|
bsd_ring_flush(struct drm_i915_gem_request *req,
|
2010-10-27 18:18:21 +07:00
|
|
|
u32 invalidate_domains,
|
|
|
|
u32 flush_domains)
|
2010-05-21 08:08:57 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2011-01-05 00:34:02 +07:00
|
|
|
int ret;
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 2);
|
2011-01-05 00:34:02 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, MI_FLUSH);
|
|
|
|
intel_ring_emit(engine, MI_NOOP);
|
|
|
|
intel_ring_advance(engine);
|
2011-01-05 00:34:02 +07:00
|
|
|
return 0;
|
2010-05-21 08:08:57 +07:00
|
|
|
}
|
|
|
|
|
2010-10-27 22:11:02 +07:00
|
|
|
static int
|
2015-05-29 23:44:00 +07:00
|
|
|
i9xx_add_request(struct drm_i915_gem_request *req)
|
2010-05-21 08:08:57 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2010-10-27 22:11:02 +07:00
|
|
|
int ret;
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 4);
|
2010-10-27 22:11:02 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-08-07 17:01:22 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
|
|
|
|
intel_ring_emit(engine,
|
|
|
|
I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
|
|
|
|
intel_ring_emit(engine, i915_gem_request_get_seqno(req));
|
|
|
|
intel_ring_emit(engine, MI_USER_INTERRUPT);
|
|
|
|
__intel_ring_advance(engine);
|
2010-05-21 08:08:57 +07:00
|
|
|
|
2010-10-27 22:11:02 +07:00
|
|
|
return 0;
|
2010-05-21 08:08:57 +07:00
|
|
|
}
|
|
|
|
|
2011-01-05 00:35:21 +07:00
|
|
|
static bool
|
2016-03-16 18:00:37 +07:00
|
|
|
gen6_ring_get_irq(struct intel_engine_cs *engine)
|
2011-01-05 00:35:21 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2012-04-25 03:48:47 +07:00
|
|
|
unsigned long flags;
|
2011-01-05 00:35:21 +07:00
|
|
|
|
2014-09-15 16:38:57 +07:00
|
|
|
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
|
|
|
|
return false;
|
2011-01-05 00:35:21 +07:00
|
|
|
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
2016-03-16 18:00:37 +07:00
|
|
|
if (engine->irq_refcount++ == 0) {
|
2016-05-06 21:40:21 +07:00
|
|
|
if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE_IMR(engine,
|
|
|
|
~(engine->irq_enable_mask |
|
2016-05-06 21:40:21 +07:00
|
|
|
GT_PARITY_ERROR(dev_priv)));
|
2012-05-26 06:56:23 +07:00
|
|
|
else
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
|
|
|
|
gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
|
2011-01-05 00:35:21 +07:00
|
|
|
}
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
2011-01-05 00:35:21 +07:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-03-16 18:00:37 +07:00
|
|
|
gen6_ring_put_irq(struct intel_engine_cs *engine)
|
2011-01-05 00:35:21 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2012-04-25 03:48:47 +07:00
|
|
|
unsigned long flags;
|
2011-01-05 00:35:21 +07:00
|
|
|
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
2016-03-16 18:00:37 +07:00
|
|
|
if (--engine->irq_refcount == 0) {
|
2016-05-06 21:40:21 +07:00
|
|
|
if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
|
|
|
|
I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
|
2012-05-26 06:56:23 +07:00
|
|
|
else
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE_IMR(engine, ~0);
|
|
|
|
gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
|
2010-12-04 18:30:53 +07:00
|
|
|
}
|
2012-04-25 03:48:47 +07:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
2010-05-21 08:08:57 +07:00
|
|
|
}
|
|
|
|
|
2013-05-29 09:22:30 +07:00
|
|
|
static bool
|
2016-03-16 18:00:37 +07:00
|
|
|
hsw_vebox_get_irq(struct intel_engine_cs *engine)
|
2013-05-29 09:22:30 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2013-05-29 09:22:30 +07:00
|
|
|
unsigned long flags;
|
|
|
|
|
2014-09-15 16:38:57 +07:00
|
|
|
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
|
2013-05-29 09:22:30 +07:00
|
|
|
return false;
|
|
|
|
|
2013-07-05 04:35:28 +07:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
2016-03-16 18:00:37 +07:00
|
|
|
if (engine->irq_refcount++ == 0) {
|
|
|
|
I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
|
|
|
|
gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
|
2013-05-29 09:22:30 +07:00
|
|
|
}
|
2013-07-05 04:35:28 +07:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
2013-05-29 09:22:30 +07:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-03-16 18:00:37 +07:00
|
|
|
hsw_vebox_put_irq(struct intel_engine_cs *engine)
|
2013-05-29 09:22:30 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2013-05-29 09:22:30 +07:00
|
|
|
unsigned long flags;
|
|
|
|
|
2013-07-05 04:35:28 +07:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
2016-03-16 18:00:37 +07:00
|
|
|
if (--engine->irq_refcount == 0) {
|
|
|
|
I915_WRITE_IMR(engine, ~0);
|
|
|
|
gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
|
2013-05-29 09:22:30 +07:00
|
|
|
}
|
2013-07-05 04:35:28 +07:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
2013-05-29 09:22:30 +07:00
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
static bool
|
2016-03-16 18:00:37 +07:00
|
|
|
gen8_ring_get_irq(struct intel_engine_cs *engine)
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
unsigned long flags;
|
|
|
|
|
2014-09-15 16:38:57 +07:00
|
|
|
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
return false;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
2016-03-16 18:00:37 +07:00
|
|
|
if (engine->irq_refcount++ == 0) {
|
2016-05-06 21:40:21 +07:00
|
|
|
if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE_IMR(engine,
|
|
|
|
~(engine->irq_enable_mask |
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
|
|
|
|
} else {
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
}
|
2016-03-16 18:00:37 +07:00
|
|
|
POSTING_READ(RING_IMR(engine->mmio_base));
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-03-16 18:00:37 +07:00
|
|
|
gen8_ring_put_irq(struct intel_engine_cs *engine)
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
2016-03-16 18:00:37 +07:00
|
|
|
if (--engine->irq_refcount == 0) {
|
2016-05-06 21:40:21 +07:00
|
|
|
if (HAS_L3_DPF(dev_priv) && engine->id == RCS) {
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE_IMR(engine,
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
|
|
|
|
} else {
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE_IMR(engine, ~0);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
}
|
2016-03-16 18:00:37 +07:00
|
|
|
POSTING_READ(RING_IMR(engine->mmio_base));
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
|
|
|
}
|
|
|
|
|
2010-05-21 08:08:57 +07:00
|
|
|
static int
|
2015-05-29 23:44:02 +07:00
|
|
|
i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
|
2014-04-29 09:29:25 +07:00
|
|
|
u64 offset, u32 length,
|
2015-02-13 18:48:10 +07:00
|
|
|
unsigned dispatch_flags)
|
2010-05-21 08:08:57 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2010-10-27 18:45:26 +07:00
|
|
|
int ret;
|
2010-10-27 18:18:21 +07:00
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 2);
|
2010-10-27 18:45:26 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine,
|
2012-04-17 22:38:12 +07:00
|
|
|
MI_BATCH_BUFFER_START |
|
|
|
|
MI_BATCH_GTT |
|
2015-02-13 18:48:10 +07:00
|
|
|
(dispatch_flags & I915_DISPATCH_SECURE ?
|
|
|
|
0 : MI_BATCH_NON_SECURE_I965));
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, offset);
|
|
|
|
intel_ring_advance(engine);
|
2010-10-27 18:18:21 +07:00
|
|
|
|
2010-05-21 08:08:57 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-12-17 22:21:27 +07:00
|
|
|
/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
|
|
|
|
#define I830_BATCH_LIMIT (256*1024)
|
drm/i915: Evict CS TLBs between batches
Running igt, I was encountering the invalid TLB bug on my 845g, despite
that it was using the CS workaround. Examining the w/a buffer in the
error state, showed that the copy from the user batch into the
workaround itself was suffering from the invalid TLB bug (the first
cacheline was broken with the first two words reversed). Time to try a
fresh approach. This extends the workaround to write into each page of
our scratch buffer in order to overflow the TLB and evict the invalid
entries. This could be refined to only do so after we update the GTT,
but for simplicity, we do it before each batch.
I suspect this supersedes our current workaround, but for safety keep
doing both.
v2: The magic number shall be 2.
This doesn't conclusively prove that it is the mythical TLB bug we've
been trying to workaround for so long, that it requires touching a number
of pages to prevent the corruption indicates to me that it is TLB
related, but the corruption (the reversed cacheline) is more subtle than
a TLB bug, where we would expect it to read the wrong page entirely.
Oh well, it prevents a reliable hang for me and so probably for others
as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-09-08 20:25:41 +07:00
|
|
|
#define I830_TLB_ENTRIES (2)
|
|
|
|
#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
|
2010-05-21 08:08:55 +07:00
|
|
|
static int
|
2015-05-29 23:44:02 +07:00
|
|
|
i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
|
2015-02-13 18:48:10 +07:00
|
|
|
u64 offset, u32 len,
|
|
|
|
unsigned dispatch_flags)
|
2010-05-22 03:26:39 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2016-03-16 18:00:36 +07:00
|
|
|
u32 cs_offset = engine->scratch.gtt_offset;
|
2010-11-30 21:10:25 +07:00
|
|
|
int ret;
|
2010-05-22 03:26:39 +07:00
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 6);
|
drm/i915: Evict CS TLBs between batches
Running igt, I was encountering the invalid TLB bug on my 845g, despite
that it was using the CS workaround. Examining the w/a buffer in the
error state, showed that the copy from the user batch into the
workaround itself was suffering from the invalid TLB bug (the first
cacheline was broken with the first two words reversed). Time to try a
fresh approach. This extends the workaround to write into each page of
our scratch buffer in order to overflow the TLB and evict the invalid
entries. This could be refined to only do so after we update the GTT,
but for simplicity, we do it before each batch.
I suspect this supersedes our current workaround, but for safety keep
doing both.
v2: The magic number shall be 2.
This doesn't conclusively prove that it is the mythical TLB bug we've
been trying to workaround for so long, that it requires touching a number
of pages to prevent the corruption indicates to me that it is TLB
related, but the corruption (the reversed cacheline) is more subtle than
a TLB bug, where we would expect it to read the wrong page entirely.
Oh well, it prevents a reliable hang for me and so probably for others
as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-09-08 20:25:41 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-05-22 03:26:39 +07:00
|
|
|
|
drm/i915: Evict CS TLBs between batches
Running igt, I was encountering the invalid TLB bug on my 845g, despite
that it was using the CS workaround. Examining the w/a buffer in the
error state, showed that the copy from the user batch into the
workaround itself was suffering from the invalid TLB bug (the first
cacheline was broken with the first two words reversed). Time to try a
fresh approach. This extends the workaround to write into each page of
our scratch buffer in order to overflow the TLB and evict the invalid
entries. This could be refined to only do so after we update the GTT,
but for simplicity, we do it before each batch.
I suspect this supersedes our current workaround, but for safety keep
doing both.
v2: The magic number shall be 2.
This doesn't conclusively prove that it is the mythical TLB bug we've
been trying to workaround for so long, that it requires touching a number
of pages to prevent the corruption indicates to me that it is TLB
related, but the corruption (the reversed cacheline) is more subtle than
a TLB bug, where we would expect it to read the wrong page entirely.
Oh well, it prevents a reliable hang for me and so probably for others
as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-09-08 20:25:41 +07:00
|
|
|
/* Evict the invalid PTE TLBs */
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
|
|
|
|
intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
|
|
|
|
intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
|
|
|
|
intel_ring_emit(engine, cs_offset);
|
|
|
|
intel_ring_emit(engine, 0xdeadbeef);
|
|
|
|
intel_ring_emit(engine, MI_NOOP);
|
|
|
|
intel_ring_advance(engine);
|
2012-12-17 22:21:27 +07:00
|
|
|
|
2015-02-13 18:48:10 +07:00
|
|
|
if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
|
2012-12-17 22:21:27 +07:00
|
|
|
if (len > I830_BATCH_LIMIT)
|
|
|
|
return -ENOSPC;
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 6 + 2);
|
2012-12-17 22:21:27 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
drm/i915: Evict CS TLBs between batches
Running igt, I was encountering the invalid TLB bug on my 845g, despite
that it was using the CS workaround. Examining the w/a buffer in the
error state, showed that the copy from the user batch into the
workaround itself was suffering from the invalid TLB bug (the first
cacheline was broken with the first two words reversed). Time to try a
fresh approach. This extends the workaround to write into each page of
our scratch buffer in order to overflow the TLB and evict the invalid
entries. This could be refined to only do so after we update the GTT,
but for simplicity, we do it before each batch.
I suspect this supersedes our current workaround, but for safety keep
doing both.
v2: The magic number shall be 2.
This doesn't conclusively prove that it is the mythical TLB bug we've
been trying to workaround for so long, that it requires touching a number
of pages to prevent the corruption indicates to me that it is TLB
related, but the corruption (the reversed cacheline) is more subtle than
a TLB bug, where we would expect it to read the wrong page entirely.
Oh well, it prevents a reliable hang for me and so probably for others
as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-09-08 20:25:41 +07:00
|
|
|
|
|
|
|
/* Blit the batch (which has now all relocs applied) to the
|
|
|
|
* stable batch scratch bo area (so that the CS never
|
|
|
|
* stumbles over its tlb invalidation bug) ...
|
|
|
|
*/
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
|
|
|
|
intel_ring_emit(engine,
|
|
|
|
BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
|
|
|
|
intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
|
|
|
|
intel_ring_emit(engine, cs_offset);
|
|
|
|
intel_ring_emit(engine, 4096);
|
|
|
|
intel_ring_emit(engine, offset);
|
|
|
|
|
|
|
|
intel_ring_emit(engine, MI_FLUSH);
|
|
|
|
intel_ring_emit(engine, MI_NOOP);
|
|
|
|
intel_ring_advance(engine);
|
2012-12-17 22:21:27 +07:00
|
|
|
|
|
|
|
/* ... and execute it. */
|
drm/i915: Evict CS TLBs between batches
Running igt, I was encountering the invalid TLB bug on my 845g, despite
that it was using the CS workaround. Examining the w/a buffer in the
error state, showed that the copy from the user batch into the
workaround itself was suffering from the invalid TLB bug (the first
cacheline was broken with the first two words reversed). Time to try a
fresh approach. This extends the workaround to write into each page of
our scratch buffer in order to overflow the TLB and evict the invalid
entries. This could be refined to only do so after we update the GTT,
but for simplicity, we do it before each batch.
I suspect this supersedes our current workaround, but for safety keep
doing both.
v2: The magic number shall be 2.
This doesn't conclusively prove that it is the mythical TLB bug we've
been trying to workaround for so long, that it requires touching a number
of pages to prevent the corruption indicates to me that it is TLB
related, but the corruption (the reversed cacheline) is more subtle than
a TLB bug, where we would expect it to read the wrong page entirely.
Oh well, it prevents a reliable hang for me and so probably for others
as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-09-08 20:25:41 +07:00
|
|
|
offset = cs_offset;
|
2012-12-17 22:21:27 +07:00
|
|
|
}
|
2010-10-27 18:45:26 +07:00
|
|
|
|
2015-12-14 23:23:49 +07:00
|
|
|
ret = intel_ring_begin(req, 2);
|
drm/i915: Evict CS TLBs between batches
Running igt, I was encountering the invalid TLB bug on my 845g, despite
that it was using the CS workaround. Examining the w/a buffer in the
error state, showed that the copy from the user batch into the
workaround itself was suffering from the invalid TLB bug (the first
cacheline was broken with the first two words reversed). Time to try a
fresh approach. This extends the workaround to write into each page of
our scratch buffer in order to overflow the TLB and evict the invalid
entries. This could be refined to only do so after we update the GTT,
but for simplicity, we do it before each batch.
I suspect this supersedes our current workaround, but for safety keep
doing both.
v2: The magic number shall be 2.
This doesn't conclusively prove that it is the mythical TLB bug we've
been trying to workaround for so long, that it requires touching a number
of pages to prevent the corruption indicates to me that it is TLB
related, but the corruption (the reversed cacheline) is more subtle than
a TLB bug, where we would expect it to read the wrong page entirely.
Oh well, it prevents a reliable hang for me and so probably for others
as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-09-08 20:25:41 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
|
|
|
|
intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
|
|
|
|
0 : MI_BATCH_NON_SECURE));
|
|
|
|
intel_ring_advance(engine);
|
drm/i915: Evict CS TLBs between batches
Running igt, I was encountering the invalid TLB bug on my 845g, despite
that it was using the CS workaround. Examining the w/a buffer in the
error state, showed that the copy from the user batch into the
workaround itself was suffering from the invalid TLB bug (the first
cacheline was broken with the first two words reversed). Time to try a
fresh approach. This extends the workaround to write into each page of
our scratch buffer in order to overflow the TLB and evict the invalid
entries. This could be refined to only do so after we update the GTT,
but for simplicity, we do it before each batch.
I suspect this supersedes our current workaround, but for safety keep
doing both.
v2: The magic number shall be 2.
This doesn't conclusively prove that it is the mythical TLB bug we've
been trying to workaround for so long, that it requires touching a number
of pages to prevent the corruption indicates to me that it is TLB
related, but the corruption (the reversed cacheline) is more subtle than
a TLB bug, where we would expect it to read the wrong page entirely.
Oh well, it prevents a reliable hang for me and so probably for others
as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-09-08 20:25:41 +07:00
|
|
|
|
2012-04-12 03:12:56 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2015-05-29 23:44:02 +07:00
|
|
|
i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
|
2014-04-29 09:29:25 +07:00
|
|
|
u64 offset, u32 len,
|
2015-02-13 18:48:10 +07:00
|
|
|
unsigned dispatch_flags)
|
2012-04-12 03:12:56 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2012-04-12 03:12:56 +07:00
|
|
|
int ret;
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 2);
|
2012-04-12 03:12:56 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
|
|
|
|
intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
|
|
|
|
0 : MI_BATCH_NON_SECURE));
|
|
|
|
intel_ring_advance(engine);
|
2010-05-22 03:26:39 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static void cleanup_phys_status_page(struct intel_engine_cs *engine)
|
2016-01-12 01:48:32 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-01-12 01:48:32 +07:00
|
|
|
|
|
|
|
if (!dev_priv->status_page_dmah)
|
|
|
|
return;
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah);
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->status_page.page_addr = NULL;
|
2016-01-12 01:48:32 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static void cleanup_status_page(struct intel_engine_cs *engine)
|
2010-05-22 03:26:39 +07:00
|
|
|
{
|
2010-11-09 02:18:58 +07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2010-05-22 03:26:39 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
obj = engine->status_page.obj;
|
2010-05-21 08:08:55 +07:00
|
|
|
if (obj == NULL)
|
2010-05-22 03:26:39 +07:00
|
|
|
return;
|
|
|
|
|
2012-06-01 21:20:22 +07:00
|
|
|
kunmap(sg_page(obj->pages->sgl));
|
2013-12-07 05:10:55 +07:00
|
|
|
i915_gem_object_ggtt_unpin(obj);
|
2010-11-09 02:18:58 +07:00
|
|
|
drm_gem_object_unreference(&obj->base);
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->status_page.obj = NULL;
|
2010-05-22 03:26:39 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static int init_status_page(struct intel_engine_cs *engine)
|
2010-05-22 03:26:39 +07:00
|
|
|
{
|
2016-03-16 18:00:37 +07:00
|
|
|
struct drm_i915_gem_object *obj = engine->status_page.obj;
|
2010-05-22 03:26:39 +07:00
|
|
|
|
2016-01-12 01:48:32 +07:00
|
|
|
if (obj == NULL) {
|
2014-07-04 04:33:03 +07:00
|
|
|
unsigned flags;
|
2014-04-09 15:19:41 +07:00
|
|
|
int ret;
|
2011-04-04 15:44:39 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
obj = i915_gem_object_create(engine->i915->dev, 4096);
|
2016-04-25 19:32:13 +07:00
|
|
|
if (IS_ERR(obj)) {
|
2014-04-09 15:19:41 +07:00
|
|
|
DRM_ERROR("Failed to allocate status page\n");
|
2016-04-25 19:32:13 +07:00
|
|
|
return PTR_ERR(obj);
|
2014-04-09 15:19:41 +07:00
|
|
|
}
|
2010-05-22 03:26:39 +07:00
|
|
|
|
2014-04-09 15:19:41 +07:00
|
|
|
ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
|
|
|
|
if (ret)
|
|
|
|
goto err_unref;
|
|
|
|
|
2014-07-04 04:33:03 +07:00
|
|
|
flags = 0;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (!HAS_LLC(engine->i915))
|
2014-07-04 04:33:03 +07:00
|
|
|
/* On g33, we cannot place HWS above 256MiB, so
|
|
|
|
* restrict its pinning to the low mappable arena.
|
|
|
|
* Though this restriction is not documented for
|
|
|
|
* gen4, gen5, or byt, they also behave similarly
|
|
|
|
* and hang if the HWS is placed at the top of the
|
|
|
|
* GTT. To generalise, it appears that all !llc
|
|
|
|
* platforms have issues with us placing the HWS
|
|
|
|
* above the mappable region (even though we never
|
|
|
|
* actualy map it).
|
|
|
|
*/
|
|
|
|
flags |= PIN_MAPPABLE;
|
|
|
|
ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
|
2014-04-09 15:19:41 +07:00
|
|
|
if (ret) {
|
|
|
|
err_unref:
|
|
|
|
drm_gem_object_unreference(&obj->base);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->status_page.obj = obj;
|
2014-04-09 15:19:41 +07:00
|
|
|
}
|
2010-05-22 03:26:39 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
|
|
|
|
engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
|
|
|
|
memset(engine->status_page.page_addr, 0, PAGE_SIZE);
|
2010-05-22 03:26:39 +07:00
|
|
|
|
2010-05-21 08:08:55 +07:00
|
|
|
DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->name, engine->status_page.gfx_addr);
|
2010-05-22 03:26:39 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static int init_phys_status_page(struct intel_engine_cs *engine)
|
2012-11-16 18:43:20 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2012-11-16 18:43:20 +07:00
|
|
|
|
|
|
|
if (!dev_priv->status_page_dmah) {
|
|
|
|
dev_priv->status_page_dmah =
|
2016-05-06 21:40:21 +07:00
|
|
|
drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE);
|
2012-11-16 18:43:20 +07:00
|
|
|
if (!dev_priv->status_page_dmah)
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
|
|
|
|
memset(engine->status_page.page_addr, 0, PAGE_SIZE);
|
2012-11-16 18:43:20 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-11-13 17:28:56 +07:00
|
|
|
void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
|
2014-07-03 22:28:02 +07:00
|
|
|
{
|
2016-04-28 15:56:40 +07:00
|
|
|
GEM_BUG_ON(ringbuf->vma == NULL);
|
|
|
|
GEM_BUG_ON(ringbuf->virtual_start == NULL);
|
|
|
|
|
2015-10-08 19:39:54 +07:00
|
|
|
if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
|
2016-04-08 18:11:11 +07:00
|
|
|
i915_gem_object_unpin_map(ringbuf->obj);
|
2015-10-08 19:39:54 +07:00
|
|
|
else
|
2016-04-28 15:56:40 +07:00
|
|
|
i915_vma_unpin_iomap(ringbuf->vma);
|
2016-04-12 20:46:16 +07:00
|
|
|
ringbuf->virtual_start = NULL;
|
2016-04-28 15:56:40 +07:00
|
|
|
|
2014-07-03 22:28:02 +07:00
|
|
|
i915_gem_object_ggtt_unpin(ringbuf->obj);
|
2016-04-28 15:56:40 +07:00
|
|
|
ringbuf->vma = NULL;
|
2014-11-13 17:28:56 +07:00
|
|
|
}
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
|
2014-11-13 17:28:56 +07:00
|
|
|
struct intel_ringbuffer *ringbuf)
|
|
|
|
{
|
|
|
|
struct drm_i915_gem_object *obj = ringbuf->obj;
|
2016-04-13 23:35:11 +07:00
|
|
|
/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
|
|
|
|
unsigned flags = PIN_OFFSET_BIAS | 4096;
|
2016-04-12 20:46:16 +07:00
|
|
|
void *addr;
|
2014-11-13 17:28:56 +07:00
|
|
|
int ret;
|
|
|
|
|
2015-10-08 19:39:54 +07:00
|
|
|
if (HAS_LLC(dev_priv) && !obj->stolen) {
|
2016-04-13 23:35:11 +07:00
|
|
|
ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
|
2015-10-08 19:39:54 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2014-11-13 17:28:56 +07:00
|
|
|
|
2015-10-08 19:39:54 +07:00
|
|
|
ret = i915_gem_object_set_to_cpu_domain(obj, true);
|
2016-04-08 18:11:10 +07:00
|
|
|
if (ret)
|
|
|
|
goto err_unpin;
|
2015-10-08 19:39:54 +07:00
|
|
|
|
2016-04-12 20:46:16 +07:00
|
|
|
addr = i915_gem_object_pin_map(obj);
|
|
|
|
if (IS_ERR(addr)) {
|
|
|
|
ret = PTR_ERR(addr);
|
2016-04-08 18:11:10 +07:00
|
|
|
goto err_unpin;
|
2015-10-08 19:39:54 +07:00
|
|
|
}
|
|
|
|
} else {
|
2016-04-13 23:35:11 +07:00
|
|
|
ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
|
|
|
|
flags | PIN_MAPPABLE);
|
2015-10-08 19:39:54 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2014-11-13 17:28:56 +07:00
|
|
|
|
2015-10-08 19:39:54 +07:00
|
|
|
ret = i915_gem_object_set_to_gtt_domain(obj, true);
|
2016-04-08 18:11:10 +07:00
|
|
|
if (ret)
|
|
|
|
goto err_unpin;
|
2015-10-08 19:39:54 +07:00
|
|
|
|
2016-01-27 22:43:49 +07:00
|
|
|
/* Access through the GTT requires the device to be awake. */
|
|
|
|
assert_rpm_wakelock_held(dev_priv);
|
|
|
|
|
2016-04-28 15:56:40 +07:00
|
|
|
addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj));
|
|
|
|
if (IS_ERR(addr)) {
|
|
|
|
ret = PTR_ERR(addr);
|
2016-04-08 18:11:10 +07:00
|
|
|
goto err_unpin;
|
2015-10-08 19:39:54 +07:00
|
|
|
}
|
2014-11-13 17:28:56 +07:00
|
|
|
}
|
|
|
|
|
2016-04-12 20:46:16 +07:00
|
|
|
ringbuf->virtual_start = addr;
|
2016-01-15 22:10:28 +07:00
|
|
|
ringbuf->vma = i915_gem_obj_to_ggtt(obj);
|
2014-11-13 17:28:56 +07:00
|
|
|
return 0;
|
2016-04-08 18:11:10 +07:00
|
|
|
|
|
|
|
err_unpin:
|
|
|
|
i915_gem_object_ggtt_unpin(obj);
|
|
|
|
return ret;
|
2014-11-13 17:28:56 +07:00
|
|
|
}
|
|
|
|
|
2015-09-03 19:01:39 +07:00
|
|
|
static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
|
2014-11-13 17:28:56 +07:00
|
|
|
{
|
2014-07-03 22:28:02 +07:00
|
|
|
drm_gem_object_unreference(&ringbuf->obj->base);
|
|
|
|
ringbuf->obj = NULL;
|
|
|
|
}
|
|
|
|
|
2015-09-03 19:01:39 +07:00
|
|
|
static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
|
|
|
|
struct intel_ringbuffer *ringbuf)
|
2010-05-22 03:26:39 +07:00
|
|
|
{
|
2010-11-09 02:18:58 +07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2010-05-22 03:26:39 +07:00
|
|
|
|
2012-11-15 18:32:28 +07:00
|
|
|
obj = NULL;
|
|
|
|
if (!HAS_LLC(dev))
|
2014-05-22 20:13:36 +07:00
|
|
|
obj = i915_gem_object_create_stolen(dev, ringbuf->size);
|
2012-11-15 18:32:28 +07:00
|
|
|
if (obj == NULL)
|
2016-04-23 01:14:32 +07:00
|
|
|
obj = i915_gem_object_create(dev, ringbuf->size);
|
2016-04-25 19:32:13 +07:00
|
|
|
if (IS_ERR(obj))
|
|
|
|
return PTR_ERR(obj);
|
2010-05-21 08:08:55 +07:00
|
|
|
|
2014-06-17 12:29:42 +07:00
|
|
|
/* mark ring buffers as read-only from GPU side by default */
|
|
|
|
obj->gt_ro = 1;
|
|
|
|
|
2014-05-22 20:13:36 +07:00
|
|
|
ringbuf->obj = obj;
|
2014-04-09 15:19:41 +07:00
|
|
|
|
2014-11-13 17:28:56 +07:00
|
|
|
return 0;
|
2014-04-09 15:19:41 +07:00
|
|
|
}
|
|
|
|
|
2015-09-03 19:01:39 +07:00
|
|
|
struct intel_ringbuffer *
|
|
|
|
intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
|
|
|
|
{
|
|
|
|
struct intel_ringbuffer *ring;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ring = kzalloc(sizeof(*ring), GFP_KERNEL);
|
2015-09-03 19:01:40 +07:00
|
|
|
if (ring == NULL) {
|
|
|
|
DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
|
|
|
|
engine->name);
|
2015-09-03 19:01:39 +07:00
|
|
|
return ERR_PTR(-ENOMEM);
|
2015-09-03 19:01:40 +07:00
|
|
|
}
|
2015-09-03 19:01:39 +07:00
|
|
|
|
2016-03-16 18:00:38 +07:00
|
|
|
ring->engine = engine;
|
2015-09-03 19:01:40 +07:00
|
|
|
list_add(&ring->link, &engine->buffers);
|
2015-09-03 19:01:39 +07:00
|
|
|
|
|
|
|
ring->size = size;
|
|
|
|
/* Workaround an erratum on the i830 which causes a hang if
|
|
|
|
* the TAIL pointer points to within the last 2 cachelines
|
|
|
|
* of the buffer.
|
|
|
|
*/
|
|
|
|
ring->effective_size = size;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_I830(engine->i915) || IS_845G(engine->i915))
|
2015-09-03 19:01:39 +07:00
|
|
|
ring->effective_size -= 2 * CACHELINE_BYTES;
|
|
|
|
|
|
|
|
ring->last_retired_head = -1;
|
|
|
|
intel_ring_update_space(ring);
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring);
|
2015-09-03 19:01:39 +07:00
|
|
|
if (ret) {
|
2015-09-03 19:01:40 +07:00
|
|
|
DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
|
|
|
|
engine->name, ret);
|
|
|
|
list_del(&ring->link);
|
2015-09-03 19:01:39 +07:00
|
|
|
kfree(ring);
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ring;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
intel_ringbuffer_free(struct intel_ringbuffer *ring)
|
|
|
|
{
|
|
|
|
intel_destroy_ringbuffer_obj(ring);
|
2015-09-03 19:01:40 +07:00
|
|
|
list_del(&ring->link);
|
2015-09-03 19:01:39 +07:00
|
|
|
kfree(ring);
|
|
|
|
}
|
|
|
|
|
2016-06-24 20:55:53 +07:00
|
|
|
static int intel_ring_context_pin(struct i915_gem_context *ctx,
|
|
|
|
struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
struct intel_context *ce = &ctx->engine[engine->id];
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
lockdep_assert_held(&ctx->i915->dev->struct_mutex);
|
|
|
|
|
|
|
|
if (ce->pin_count++)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (ce->state) {
|
|
|
|
ret = i915_gem_obj_ggtt_pin(ce->state, ctx->ggtt_alignment, 0);
|
|
|
|
if (ret)
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2016-06-24 20:55:54 +07:00
|
|
|
/* The kernel context is only used as a placeholder for flushing the
|
|
|
|
* active context. It is never used for submitting user rendering and
|
|
|
|
* as such never requires the golden render context, and so we can skip
|
|
|
|
* emitting it when we switch to the kernel context. This is required
|
|
|
|
* as during eviction we cannot allocate and pin the renderstate in
|
|
|
|
* order to initialise the context.
|
|
|
|
*/
|
|
|
|
if (ctx == ctx->i915->kernel_context)
|
|
|
|
ce->initialised = true;
|
|
|
|
|
2016-06-24 20:55:53 +07:00
|
|
|
i915_gem_context_reference(ctx);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
error:
|
|
|
|
ce->pin_count = 0;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_ring_context_unpin(struct i915_gem_context *ctx,
|
|
|
|
struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
struct intel_context *ce = &ctx->engine[engine->id];
|
|
|
|
|
|
|
|
lockdep_assert_held(&ctx->i915->dev->struct_mutex);
|
|
|
|
|
|
|
|
if (--ce->pin_count)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (ce->state)
|
|
|
|
i915_gem_object_ggtt_unpin(ce->state);
|
|
|
|
|
|
|
|
i915_gem_context_unreference(ctx);
|
|
|
|
}
|
|
|
|
|
2014-04-09 15:19:41 +07:00
|
|
|
static int intel_init_ring_buffer(struct drm_device *dev,
|
2016-03-16 18:00:37 +07:00
|
|
|
struct intel_engine_cs *engine)
|
2014-04-09 15:19:41 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2014-11-20 06:33:08 +07:00
|
|
|
struct intel_ringbuffer *ringbuf;
|
2014-04-09 15:19:41 +07:00
|
|
|
int ret;
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
WARN_ON(engine->buffer);
|
2014-11-20 06:33:08 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
engine->i915 = dev_priv;
|
2016-03-16 18:00:37 +07:00
|
|
|
INIT_LIST_HEAD(&engine->active_list);
|
|
|
|
INIT_LIST_HEAD(&engine->request_list);
|
|
|
|
INIT_LIST_HEAD(&engine->execlist_queue);
|
|
|
|
INIT_LIST_HEAD(&engine->buffers);
|
|
|
|
i915_gem_batch_pool_init(dev, &engine->batch_pool);
|
|
|
|
memset(engine->semaphore.sync_seqno, 0,
|
|
|
|
sizeof(engine->semaphore.sync_seqno));
|
2014-04-09 15:19:41 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
init_waitqueue_head(&engine->irq_queue);
|
2014-04-09 15:19:41 +07:00
|
|
|
|
2016-06-24 20:55:53 +07:00
|
|
|
/* We may need to do things with the shrinker which
|
|
|
|
* require us to immediately switch back to the default
|
|
|
|
* context. This can cause a problem as pinning the
|
|
|
|
* default context also requires GTT space which may not
|
|
|
|
* be available. To avoid this we always pin the default
|
|
|
|
* context.
|
|
|
|
*/
|
|
|
|
ret = intel_ring_context_pin(dev_priv->kernel_context, engine);
|
|
|
|
if (ret)
|
|
|
|
goto error;
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
|
2015-12-08 22:02:36 +07:00
|
|
|
if (IS_ERR(ringbuf)) {
|
|
|
|
ret = PTR_ERR(ringbuf);
|
|
|
|
goto error;
|
|
|
|
}
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->buffer = ringbuf;
|
2015-09-03 19:01:39 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (I915_NEED_GFX_HWS(dev_priv)) {
|
2016-03-16 18:00:37 +07:00
|
|
|
ret = init_status_page(engine);
|
2014-04-09 15:19:41 +07:00
|
|
|
if (ret)
|
2014-05-22 20:13:34 +07:00
|
|
|
goto error;
|
2014-04-09 15:19:41 +07:00
|
|
|
} else {
|
2016-03-16 18:00:37 +07:00
|
|
|
WARN_ON(engine->id != RCS);
|
|
|
|
ret = init_phys_status_page(engine);
|
2014-04-09 15:19:41 +07:00
|
|
|
if (ret)
|
2014-05-22 20:13:34 +07:00
|
|
|
goto error;
|
2014-04-09 15:19:41 +07:00
|
|
|
}
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
|
2014-11-20 06:33:08 +07:00
|
|
|
if (ret) {
|
|
|
|
DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->name, ret);
|
2014-11-20 06:33:08 +07:00
|
|
|
intel_destroy_ringbuffer_obj(ringbuf);
|
|
|
|
goto error;
|
2014-04-09 15:19:41 +07:00
|
|
|
}
|
2010-05-22 03:26:39 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
ret = i915_cmd_parser_init_ring(engine);
|
2014-05-11 04:10:43 +07:00
|
|
|
if (ret)
|
2014-05-22 20:13:34 +07:00
|
|
|
goto error;
|
|
|
|
|
|
|
|
return 0;
|
2014-02-19 01:15:46 +07:00
|
|
|
|
2014-05-22 20:13:34 +07:00
|
|
|
error:
|
2016-03-16 18:00:40 +07:00
|
|
|
intel_cleanup_engine(engine);
|
2014-05-22 20:13:34 +07:00
|
|
|
return ret;
|
2010-05-22 03:26:39 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:40 +07:00
|
|
|
void intel_cleanup_engine(struct intel_engine_cs *engine)
|
2010-05-22 03:26:39 +07:00
|
|
|
{
|
2014-10-31 19:00:26 +07:00
|
|
|
struct drm_i915_private *dev_priv;
|
2010-10-29 22:18:36 +07:00
|
|
|
|
2016-03-16 18:00:40 +07:00
|
|
|
if (!intel_engine_initialized(engine))
|
2010-05-22 03:26:39 +07:00
|
|
|
return;
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
dev_priv = engine->i915;
|
2014-10-31 19:00:26 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
if (engine->buffer) {
|
2016-03-16 18:00:40 +07:00
|
|
|
intel_stop_engine(engine);
|
2016-05-06 21:40:21 +07:00
|
|
|
WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
|
2010-10-29 22:18:36 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
intel_unpin_ringbuffer_obj(engine->buffer);
|
|
|
|
intel_ringbuffer_free(engine->buffer);
|
|
|
|
engine->buffer = NULL;
|
2015-12-08 22:02:36 +07:00
|
|
|
}
|
2010-10-27 18:18:21 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
if (engine->cleanup)
|
|
|
|
engine->cleanup(engine);
|
2010-11-02 15:31:01 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (I915_NEED_GFX_HWS(dev_priv)) {
|
2016-03-16 18:00:37 +07:00
|
|
|
cleanup_status_page(engine);
|
2016-01-12 01:48:32 +07:00
|
|
|
} else {
|
2016-03-16 18:00:37 +07:00
|
|
|
WARN_ON(engine->id != RCS);
|
|
|
|
cleanup_phys_status_page(engine);
|
2016-01-12 01:48:32 +07:00
|
|
|
}
|
2014-05-11 04:10:43 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
i915_cmd_parser_fini_ring(engine);
|
|
|
|
i915_gem_batch_pool_fini(&engine->batch_pool);
|
2016-06-24 20:55:53 +07:00
|
|
|
|
|
|
|
intel_ring_context_unpin(dev_priv->kernel_context, engine);
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
engine->i915 = NULL;
|
2010-05-22 03:26:39 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:39 +07:00
|
|
|
int intel_engine_idle(struct intel_engine_cs *engine)
|
2012-11-27 23:22:54 +07:00
|
|
|
{
|
2014-11-26 20:17:05 +07:00
|
|
|
struct drm_i915_gem_request *req;
|
2012-11-27 23:22:54 +07:00
|
|
|
|
|
|
|
/* Wait upon the last request to be completed */
|
2016-03-16 18:00:37 +07:00
|
|
|
if (list_empty(&engine->request_list))
|
2012-11-27 23:22:54 +07:00
|
|
|
return 0;
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
req = list_entry(engine->request_list.prev,
|
|
|
|
struct drm_i915_gem_request,
|
|
|
|
list);
|
2015-04-27 19:41:17 +07:00
|
|
|
|
|
|
|
/* Make sure we do not trigger any retires */
|
|
|
|
return __i915_wait_request(req,
|
2016-04-13 23:35:03 +07:00
|
|
|
req->i915->mm.interruptible,
|
2015-04-27 19:41:17 +07:00
|
|
|
NULL, NULL);
|
2012-11-27 23:22:54 +07:00
|
|
|
}
|
|
|
|
|
2015-03-19 19:30:08 +07:00
|
|
|
int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
|
2012-11-27 23:22:52 +07:00
|
|
|
{
|
2016-04-28 15:56:49 +07:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Flush enough space to reduce the likelihood of waiting after
|
|
|
|
* we start building the request - in which case we will just
|
|
|
|
* have to repeat work.
|
|
|
|
*/
|
2016-04-29 15:07:05 +07:00
|
|
|
request->reserved_space += LEGACY_REQUEST_SIZE;
|
2016-04-28 15:56:49 +07:00
|
|
|
|
2016-03-16 18:00:38 +07:00
|
|
|
request->ringbuf = request->engine->buffer;
|
2016-04-28 15:56:49 +07:00
|
|
|
|
|
|
|
ret = intel_ring_begin(request, 0);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-04-29 15:07:05 +07:00
|
|
|
request->reserved_space -= LEGACY_REQUEST_SIZE;
|
2016-04-28 15:56:49 +07:00
|
|
|
return 0;
|
2012-11-27 23:22:52 +07:00
|
|
|
}
|
|
|
|
|
2016-04-28 15:56:46 +07:00
|
|
|
static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
|
|
|
|
{
|
|
|
|
struct intel_ringbuffer *ringbuf = req->ringbuf;
|
|
|
|
struct intel_engine_cs *engine = req->engine;
|
|
|
|
struct drm_i915_gem_request *target;
|
|
|
|
|
|
|
|
intel_ring_update_space(ringbuf);
|
|
|
|
if (ringbuf->space >= bytes)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Space is reserved in the ringbuffer for finalising the request,
|
|
|
|
* as that cannot be allowed to fail. During request finalisation,
|
|
|
|
* reserved_space is set to 0 to stop the overallocation and the
|
|
|
|
* assumption is that then we never need to wait (which has the
|
|
|
|
* risk of failing with EINTR).
|
|
|
|
*
|
|
|
|
* See also i915_gem_request_alloc() and i915_add_request().
|
|
|
|
*/
|
2016-04-28 15:56:47 +07:00
|
|
|
GEM_BUG_ON(!req->reserved_space);
|
2016-04-28 15:56:46 +07:00
|
|
|
|
|
|
|
list_for_each_entry(target, &engine->request_list, list) {
|
|
|
|
unsigned space;
|
|
|
|
|
2015-06-30 18:40:55 +07:00
|
|
|
/*
|
2016-04-28 15:56:46 +07:00
|
|
|
* The request queue is per-engine, so can contain requests
|
|
|
|
* from multiple ringbuffers. Here, we must ignore any that
|
|
|
|
* aren't from the ringbuffer we're considering.
|
2015-06-30 18:40:55 +07:00
|
|
|
*/
|
2016-04-28 15:56:46 +07:00
|
|
|
if (target->ringbuf != ringbuf)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Would completion of this request free enough space? */
|
|
|
|
space = __intel_ring_space(target->postfix, ringbuf->tail,
|
|
|
|
ringbuf->size);
|
|
|
|
if (space >= bytes)
|
|
|
|
break;
|
2015-06-30 18:40:55 +07:00
|
|
|
}
|
drm/i915: Reserve ring buffer space for i915_add_request() commands
It is a bad idea for i915_add_request() to fail. The work will already have been
send to the ring and will be processed, but there will not be any tracking or
management of that work.
The only way the add request call can fail is if it can't write its epilogue
commands to the ring (cache flushing, seqno updates, interrupt signalling). The
reasons for that are mostly down to running out of ring buffer space and the
problems associated with trying to get some more. This patch prevents that
situation from happening in the first place.
When a request is created, it marks sufficient space as reserved for the
epilogue commands. Thus guaranteeing that by the time the epilogue is written,
there will be plenty of space for it. Note that a ring_begin() call is required
to actually reserve the space (and do any potential waiting). However, that is
not currently done at request creation time. This is because the ring_begin()
code can allocate a request. Hence calling begin() from the request allocation
code would lead to infinite recursion! Later patches in this series remove the
need for begin() to do the allocate. At that point, it becomes safe for the
allocate to call begin() and really reserve the space.
Until then, there is a potential for insufficient space to be available at the
point of calling i915_add_request(). However, that would only be in the case
where the request was created and immediately submitted without ever calling
ring_begin() and adding any work to that request. Which should never happen. And
even if it does, and if that request happens to fall down the tiny window of
opportunity for failing due to being out of ring space then does it really
matter because the request wasn't doing anything in the first place?
v2: Updated the 'reserved space too small' warning to include the offending
sizes. Added a 'cancel' operation to clean up when a request is abandoned. Added
re-initialisation of tracking state after a buffer wrap to keep the sanity
checks accurate.
v3: Incremented the reserved size to accommodate Ironlake (after finally
managing to run on an ILK system). Also fixed missing wrap code in LRC mode.
v4: Added extra comment and removed duplicate WARN (feedback from Tomas).
For: VIZ-5115
CC: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-18 19:10:09 +07:00
|
|
|
|
2016-04-28 15:56:46 +07:00
|
|
|
if (WARN_ON(&target->list == &engine->request_list))
|
|
|
|
return -ENOSPC;
|
|
|
|
|
|
|
|
return i915_wait_request(target);
|
drm/i915: Reserve ring buffer space for i915_add_request() commands
It is a bad idea for i915_add_request() to fail. The work will already have been
send to the ring and will be processed, but there will not be any tracking or
management of that work.
The only way the add request call can fail is if it can't write its epilogue
commands to the ring (cache flushing, seqno updates, interrupt signalling). The
reasons for that are mostly down to running out of ring buffer space and the
problems associated with trying to get some more. This patch prevents that
situation from happening in the first place.
When a request is created, it marks sufficient space as reserved for the
epilogue commands. Thus guaranteeing that by the time the epilogue is written,
there will be plenty of space for it. Note that a ring_begin() call is required
to actually reserve the space (and do any potential waiting). However, that is
not currently done at request creation time. This is because the ring_begin()
code can allocate a request. Hence calling begin() from the request allocation
code would lead to infinite recursion! Later patches in this series remove the
need for begin() to do the allocate. At that point, it becomes safe for the
allocate to call begin() and really reserve the space.
Until then, there is a potential for insufficient space to be available at the
point of calling i915_add_request(). However, that would only be in the case
where the request was created and immediately submitted without ever calling
ring_begin() and adding any work to that request. Which should never happen. And
even if it does, and if that request happens to fall down the tiny window of
opportunity for failing due to being out of ring space then does it really
matter because the request wasn't doing anything in the first place?
v2: Updated the 'reserved space too small' warning to include the offending
sizes. Added a 'cancel' operation to clean up when a request is abandoned. Added
re-initialisation of tracking state after a buffer wrap to keep the sanity
checks accurate.
v3: Incremented the reserved size to accommodate Ironlake (after finally
managing to run on an ILK system). Also fixed missing wrap code in LRC mode.
v4: Added extra comment and removed duplicate WARN (feedback from Tomas).
For: VIZ-5115
CC: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-18 19:10:09 +07:00
|
|
|
}
|
|
|
|
|
2016-04-28 15:56:46 +07:00
|
|
|
int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
|
2012-12-04 20:12:03 +07:00
|
|
|
{
|
2016-04-28 15:56:46 +07:00
|
|
|
struct intel_ringbuffer *ringbuf = req->ringbuf;
|
2015-06-30 18:40:55 +07:00
|
|
|
int remain_actual = ringbuf->size - ringbuf->tail;
|
2016-04-28 15:56:46 +07:00
|
|
|
int remain_usable = ringbuf->effective_size - ringbuf->tail;
|
|
|
|
int bytes = num_dwords * sizeof(u32);
|
|
|
|
int total_bytes, wait_bytes;
|
2015-06-30 18:40:55 +07:00
|
|
|
bool need_wrap = false;
|
drm/i915: Reserve ring buffer space for i915_add_request() commands
It is a bad idea for i915_add_request() to fail. The work will already have been
send to the ring and will be processed, but there will not be any tracking or
management of that work.
The only way the add request call can fail is if it can't write its epilogue
commands to the ring (cache flushing, seqno updates, interrupt signalling). The
reasons for that are mostly down to running out of ring buffer space and the
problems associated with trying to get some more. This patch prevents that
situation from happening in the first place.
When a request is created, it marks sufficient space as reserved for the
epilogue commands. Thus guaranteeing that by the time the epilogue is written,
there will be plenty of space for it. Note that a ring_begin() call is required
to actually reserve the space (and do any potential waiting). However, that is
not currently done at request creation time. This is because the ring_begin()
code can allocate a request. Hence calling begin() from the request allocation
code would lead to infinite recursion! Later patches in this series remove the
need for begin() to do the allocate. At that point, it becomes safe for the
allocate to call begin() and really reserve the space.
Until then, there is a potential for insufficient space to be available at the
point of calling i915_add_request(). However, that would only be in the case
where the request was created and immediately submitted without ever calling
ring_begin() and adding any work to that request. Which should never happen. And
even if it does, and if that request happens to fall down the tiny window of
opportunity for failing due to being out of ring space then does it really
matter because the request wasn't doing anything in the first place?
v2: Updated the 'reserved space too small' warning to include the offending
sizes. Added a 'cancel' operation to clean up when a request is abandoned. Added
re-initialisation of tracking state after a buffer wrap to keep the sanity
checks accurate.
v3: Incremented the reserved size to accommodate Ironlake (after finally
managing to run on an ILK system). Also fixed missing wrap code in LRC mode.
v4: Added extra comment and removed duplicate WARN (feedback from Tomas).
For: VIZ-5115
CC: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-18 19:10:09 +07:00
|
|
|
|
2016-04-28 15:56:47 +07:00
|
|
|
total_bytes = bytes + req->reserved_space;
|
drm/i915: Reserve ring buffer space for i915_add_request() commands
It is a bad idea for i915_add_request() to fail. The work will already have been
send to the ring and will be processed, but there will not be any tracking or
management of that work.
The only way the add request call can fail is if it can't write its epilogue
commands to the ring (cache flushing, seqno updates, interrupt signalling). The
reasons for that are mostly down to running out of ring buffer space and the
problems associated with trying to get some more. This patch prevents that
situation from happening in the first place.
When a request is created, it marks sufficient space as reserved for the
epilogue commands. Thus guaranteeing that by the time the epilogue is written,
there will be plenty of space for it. Note that a ring_begin() call is required
to actually reserve the space (and do any potential waiting). However, that is
not currently done at request creation time. This is because the ring_begin()
code can allocate a request. Hence calling begin() from the request allocation
code would lead to infinite recursion! Later patches in this series remove the
need for begin() to do the allocate. At that point, it becomes safe for the
allocate to call begin() and really reserve the space.
Until then, there is a potential for insufficient space to be available at the
point of calling i915_add_request(). However, that would only be in the case
where the request was created and immediately submitted without ever calling
ring_begin() and adding any work to that request. Which should never happen. And
even if it does, and if that request happens to fall down the tiny window of
opportunity for failing due to being out of ring space then does it really
matter because the request wasn't doing anything in the first place?
v2: Updated the 'reserved space too small' warning to include the offending
sizes. Added a 'cancel' operation to clean up when a request is abandoned. Added
re-initialisation of tracking state after a buffer wrap to keep the sanity
checks accurate.
v3: Incremented the reserved size to accommodate Ironlake (after finally
managing to run on an ILK system). Also fixed missing wrap code in LRC mode.
v4: Added extra comment and removed duplicate WARN (feedback from Tomas).
For: VIZ-5115
CC: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-18 19:10:09 +07:00
|
|
|
|
2015-06-30 18:40:55 +07:00
|
|
|
if (unlikely(bytes > remain_usable)) {
|
|
|
|
/*
|
|
|
|
* Not enough space for the basic request. So need to flush
|
|
|
|
* out the remainder and then wait for base + reserved.
|
|
|
|
*/
|
|
|
|
wait_bytes = remain_actual + total_bytes;
|
|
|
|
need_wrap = true;
|
2016-04-28 15:56:46 +07:00
|
|
|
} else if (unlikely(total_bytes > remain_usable)) {
|
|
|
|
/*
|
|
|
|
* The base request will fit but the reserved space
|
|
|
|
* falls off the end. So we don't need an immediate wrap
|
|
|
|
* and only need to effectively wait for the reserved
|
|
|
|
* size space from the start of ringbuffer.
|
|
|
|
*/
|
2016-04-28 15:56:47 +07:00
|
|
|
wait_bytes = remain_actual + req->reserved_space;
|
2015-06-30 18:40:55 +07:00
|
|
|
} else {
|
2016-04-28 15:56:46 +07:00
|
|
|
/* No wrapping required, just waiting. */
|
|
|
|
wait_bytes = total_bytes;
|
2012-12-04 20:12:03 +07:00
|
|
|
}
|
|
|
|
|
2016-04-28 15:56:46 +07:00
|
|
|
if (wait_bytes > ringbuf->space) {
|
|
|
|
int ret = wait_for_space(req, wait_bytes);
|
2012-12-04 20:12:03 +07:00
|
|
|
if (unlikely(ret))
|
|
|
|
return ret;
|
2015-06-30 18:40:55 +07:00
|
|
|
|
2016-04-28 15:56:46 +07:00
|
|
|
intel_ring_update_space(ringbuf);
|
2016-05-13 17:57:22 +07:00
|
|
|
if (unlikely(ringbuf->space < wait_bytes))
|
|
|
|
return -EAGAIN;
|
2012-12-04 20:12:03 +07:00
|
|
|
}
|
|
|
|
|
2016-04-28 15:56:46 +07:00
|
|
|
if (unlikely(need_wrap)) {
|
|
|
|
GEM_BUG_ON(remain_actual > ringbuf->space);
|
|
|
|
GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
|
2010-10-27 18:18:21 +07:00
|
|
|
|
2016-04-28 15:56:46 +07:00
|
|
|
/* Fill the tail with MI_NOOP */
|
|
|
|
memset(ringbuf->virtual_start + ringbuf->tail,
|
|
|
|
0, remain_actual);
|
|
|
|
ringbuf->tail = 0;
|
|
|
|
ringbuf->space -= remain_actual;
|
|
|
|
}
|
2014-01-02 21:32:35 +07:00
|
|
|
|
2016-04-28 15:56:46 +07:00
|
|
|
ringbuf->space -= bytes;
|
|
|
|
GEM_BUG_ON(ringbuf->space < 0);
|
2014-01-02 21:32:35 +07:00
|
|
|
return 0;
|
2010-05-21 08:08:55 +07:00
|
|
|
}
|
2010-10-27 18:18:21 +07:00
|
|
|
|
2014-02-12 00:52:05 +07:00
|
|
|
/* Align the ring tail to a cacheline boundary */
|
2015-05-29 23:44:06 +07:00
|
|
|
int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
|
2014-02-12 00:52:05 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2016-03-16 18:00:36 +07:00
|
|
|
int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
|
2014-02-12 00:52:05 +07:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (num_dwords == 0)
|
|
|
|
return 0;
|
|
|
|
|
2014-04-09 15:19:40 +07:00
|
|
|
num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, num_dwords);
|
2014-02-12 00:52:05 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
while (num_dwords--)
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, MI_NOOP);
|
2014-02-12 00:52:05 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_advance(engine);
|
2014-02-12 00:52:05 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
|
2012-12-04 20:12:04 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2012-12-04 20:12:04 +07:00
|
|
|
|
2016-04-07 13:29:13 +07:00
|
|
|
/* Our semaphore implementation is strictly monotonic (i.e. we proceed
|
|
|
|
* so long as the semaphore value in the register/page is greater
|
|
|
|
* than the sync value), so whenever we reset the seqno,
|
|
|
|
* so long as we reset the tracking semaphore value to 0, it will
|
|
|
|
* always be before the next request's seqno. If we don't reset
|
|
|
|
* the semaphore value, then when the seqno moves backwards all
|
|
|
|
* future waits will complete instantly (causing rendering corruption).
|
|
|
|
*/
|
2016-05-10 16:57:06 +07:00
|
|
|
if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
|
|
|
|
I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
|
2016-04-07 13:29:12 +07:00
|
|
|
if (HAS_VEBOX(dev_priv))
|
2016-03-16 18:00:37 +07:00
|
|
|
I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
|
2010-10-27 18:45:26 +07:00
|
|
|
}
|
2016-04-07 13:29:15 +07:00
|
|
|
if (dev_priv->semaphore_obj) {
|
|
|
|
struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
|
|
|
|
struct page *page = i915_gem_object_get_dirty_page(obj, 0);
|
|
|
|
void *semaphores = kmap(page);
|
|
|
|
memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
|
|
|
|
0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
|
|
|
|
kunmap(page);
|
|
|
|
}
|
2016-04-07 13:29:13 +07:00
|
|
|
memset(engine->semaphore.sync_seqno, 0,
|
|
|
|
sizeof(engine->semaphore.sync_seqno));
|
2010-08-04 21:18:13 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->set_seqno(engine, seqno);
|
2016-04-07 13:29:16 +07:00
|
|
|
engine->last_submitted_seqno = seqno;
|
2016-04-07 13:29:13 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->hangcheck.seqno = seqno;
|
2010-05-21 08:08:55 +07:00
|
|
|
}
|
2010-05-22 03:26:39 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
|
2010-10-22 23:02:41 +07:00
|
|
|
u32 value)
|
2010-09-19 20:40:43 +07:00
|
|
|
{
|
2016-05-06 21:40:21 +07:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2010-09-19 20:40:43 +07:00
|
|
|
|
2016-06-30 21:33:45 +07:00
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
|
|
|
|
2010-09-19 20:40:43 +07:00
|
|
|
/* Every tail move must follow the sequence below */
|
2012-07-05 23:14:01 +07:00
|
|
|
|
|
|
|
/* Disable notification that the ring is IDLE. The GT
|
|
|
|
* will then assume that it is busy and bring it out of rc6.
|
|
|
|
*/
|
2016-06-30 21:33:45 +07:00
|
|
|
I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
|
|
|
|
_MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
|
2012-07-05 23:14:01 +07:00
|
|
|
|
|
|
|
/* Clear the context id. Here be magic! */
|
2016-06-30 21:33:45 +07:00
|
|
|
I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
|
2011-08-17 02:34:10 +07:00
|
|
|
|
2012-07-05 23:14:01 +07:00
|
|
|
/* Wait for the ring not to be idle, i.e. for it to wake up. */
|
2016-06-30 21:33:45 +07:00
|
|
|
if (intel_wait_for_register_fw(dev_priv,
|
|
|
|
GEN6_BSD_SLEEP_PSMI_CONTROL,
|
|
|
|
GEN6_BSD_SLEEP_INDICATOR,
|
|
|
|
0,
|
|
|
|
50))
|
2012-07-05 23:14:01 +07:00
|
|
|
DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
|
2011-08-17 02:34:10 +07:00
|
|
|
|
2012-07-05 23:14:01 +07:00
|
|
|
/* Now that the ring is fully powered up, update the tail */
|
2016-06-30 21:33:45 +07:00
|
|
|
I915_WRITE_FW(RING_TAIL(engine->mmio_base), value);
|
|
|
|
POSTING_READ_FW(RING_TAIL(engine->mmio_base));
|
2012-07-05 23:14:01 +07:00
|
|
|
|
|
|
|
/* Let the ring send IDLE messages to the GT again,
|
|
|
|
* and so let it sleep to conserve power when idle.
|
|
|
|
*/
|
2016-06-30 21:33:45 +07:00
|
|
|
I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
|
|
|
|
_MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
|
|
|
|
|
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
2010-09-19 20:40:43 +07:00
|
|
|
}
|
|
|
|
|
2015-05-29 23:43:57 +07:00
|
|
|
static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
|
2013-05-29 09:22:21 +07:00
|
|
|
u32 invalidate, u32 flush)
|
2010-09-19 20:40:43 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2011-02-02 19:13:49 +07:00
|
|
|
uint32_t cmd;
|
2011-01-05 00:34:02 +07:00
|
|
|
int ret;
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 4);
|
2011-01-05 00:34:02 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2011-02-02 19:13:49 +07:00
|
|
|
cmd = MI_FLUSH_DW;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (INTEL_GEN(req->i915) >= 8)
|
2013-11-03 11:07:13 +07:00
|
|
|
cmd += 1;
|
2015-01-22 20:42:00 +07:00
|
|
|
|
|
|
|
/* We always require a command barrier so that subsequent
|
|
|
|
* commands, such as breadcrumb interrupts, are strictly ordered
|
|
|
|
* wrt the contents of the write cache being flushed to memory
|
|
|
|
* (and thus being coherent from the CPU).
|
|
|
|
*/
|
|
|
|
cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
|
|
|
|
|
2012-10-26 23:42:42 +07:00
|
|
|
/*
|
|
|
|
* Bspec vol 1c.5 - video engine command streamer:
|
|
|
|
* "If ENABLED, all TLBs will be invalidated once the flush
|
|
|
|
* operation is complete. This bit is only valid when the
|
|
|
|
* Post-Sync Operation field is a value of 1h or 3h."
|
|
|
|
*/
|
2011-02-02 19:13:49 +07:00
|
|
|
if (invalidate & I915_GEM_GPU_DOMAINS)
|
2015-01-22 20:42:00 +07:00
|
|
|
cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, cmd);
|
|
|
|
intel_ring_emit(engine,
|
|
|
|
I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
|
2016-05-06 21:40:21 +07:00
|
|
|
if (INTEL_GEN(req->i915) >= 8) {
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, 0); /* upper addr */
|
|
|
|
intel_ring_emit(engine, 0); /* value */
|
2013-11-03 11:07:13 +07:00
|
|
|
} else {
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, 0);
|
|
|
|
intel_ring_emit(engine, MI_NOOP);
|
2013-11-03 11:07:13 +07:00
|
|
|
}
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_advance(engine);
|
2011-01-05 00:34:02 +07:00
|
|
|
return 0;
|
2010-09-19 20:40:43 +07:00
|
|
|
}
|
|
|
|
|
2013-11-03 11:07:12 +07:00
|
|
|
static int
|
2015-05-29 23:44:02 +07:00
|
|
|
gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
|
2014-04-29 09:29:25 +07:00
|
|
|
u64 offset, u32 len,
|
2015-02-13 18:48:10 +07:00
|
|
|
unsigned dispatch_flags)
|
2013-11-03 11:07:12 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2016-03-16 18:00:36 +07:00
|
|
|
bool ppgtt = USES_PPGTT(engine->dev) &&
|
2015-02-13 18:48:10 +07:00
|
|
|
!(dispatch_flags & I915_DISPATCH_SECURE);
|
2013-11-03 11:07:12 +07:00
|
|
|
int ret;
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 4);
|
2013-11-03 11:07:12 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* FIXME(BDW): Address space and security selectors. */
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
|
2015-06-16 17:39:40 +07:00
|
|
|
(dispatch_flags & I915_DISPATCH_RS ?
|
|
|
|
MI_BATCH_RESOURCE_STREAMER : 0));
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, lower_32_bits(offset));
|
|
|
|
intel_ring_emit(engine, upper_32_bits(offset));
|
|
|
|
intel_ring_emit(engine, MI_NOOP);
|
|
|
|
intel_ring_advance(engine);
|
2013-11-03 11:07:12 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-17 18:09:54 +07:00
|
|
|
static int
|
2015-05-29 23:44:02 +07:00
|
|
|
hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
|
2015-02-13 18:48:10 +07:00
|
|
|
u64 offset, u32 len,
|
|
|
|
unsigned dispatch_flags)
|
2012-10-17 18:09:54 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2012-10-17 18:09:54 +07:00
|
|
|
int ret;
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 2);
|
2012-10-17 18:09:54 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine,
|
2014-09-10 18:18:27 +07:00
|
|
|
MI_BATCH_BUFFER_START |
|
2015-02-13 18:48:10 +07:00
|
|
|
(dispatch_flags & I915_DISPATCH_SECURE ?
|
2015-06-16 17:39:40 +07:00
|
|
|
0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
|
|
|
|
(dispatch_flags & I915_DISPATCH_RS ?
|
|
|
|
MI_BATCH_RESOURCE_STREAMER : 0));
|
2012-10-17 18:09:54 +07:00
|
|
|
/* bit0-7 is the length on GEN6+ */
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, offset);
|
|
|
|
intel_ring_advance(engine);
|
2012-10-17 18:09:54 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-09-19 20:40:43 +07:00
|
|
|
static int
|
2015-05-29 23:44:02 +07:00
|
|
|
gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
|
2014-04-29 09:29:25 +07:00
|
|
|
u64 offset, u32 len,
|
2015-02-13 18:48:10 +07:00
|
|
|
unsigned dispatch_flags)
|
2010-09-19 20:40:43 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2011-08-17 02:34:10 +07:00
|
|
|
int ret;
|
2010-09-19 23:53:44 +07:00
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 2);
|
2011-08-17 02:34:10 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-10-27 18:45:26 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine,
|
2012-10-17 18:09:54 +07:00
|
|
|
MI_BATCH_BUFFER_START |
|
2015-02-13 18:48:10 +07:00
|
|
|
(dispatch_flags & I915_DISPATCH_SECURE ?
|
|
|
|
0 : MI_BATCH_NON_SECURE_I965));
|
2011-08-17 02:34:10 +07:00
|
|
|
/* bit0-7 is the length on GEN6+ */
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, offset);
|
|
|
|
intel_ring_advance(engine);
|
2010-09-19 23:53:44 +07:00
|
|
|
|
2011-08-17 02:34:10 +07:00
|
|
|
return 0;
|
2010-09-19 20:40:43 +07:00
|
|
|
}
|
|
|
|
|
2010-10-19 17:19:32 +07:00
|
|
|
/* Blitter support (SandyBridge+) */
|
|
|
|
|
2015-05-29 23:43:57 +07:00
|
|
|
static int gen6_ring_flush(struct drm_i915_gem_request *req,
|
2013-05-29 09:22:21 +07:00
|
|
|
u32 invalidate, u32 flush)
|
2010-11-02 15:31:01 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2011-02-02 19:13:49 +07:00
|
|
|
uint32_t cmd;
|
2011-01-05 00:34:02 +07:00
|
|
|
int ret;
|
|
|
|
|
2015-05-29 23:44:07 +07:00
|
|
|
ret = intel_ring_begin(req, 4);
|
2011-01-05 00:34:02 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2011-02-02 19:13:49 +07:00
|
|
|
cmd = MI_FLUSH_DW;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (INTEL_GEN(req->i915) >= 8)
|
2013-11-03 11:07:13 +07:00
|
|
|
cmd += 1;
|
2015-01-22 20:42:00 +07:00
|
|
|
|
|
|
|
/* We always require a command barrier so that subsequent
|
|
|
|
* commands, such as breadcrumb interrupts, are strictly ordered
|
|
|
|
* wrt the contents of the write cache being flushed to memory
|
|
|
|
* (and thus being coherent from the CPU).
|
|
|
|
*/
|
|
|
|
cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
|
|
|
|
|
2012-10-26 23:42:42 +07:00
|
|
|
/*
|
|
|
|
* Bspec vol 1c.3 - blitter engine command streamer:
|
|
|
|
* "If ENABLED, all TLBs will be invalidated once the flush
|
|
|
|
* operation is complete. This bit is only valid when the
|
|
|
|
* Post-Sync Operation field is a value of 1h or 3h."
|
|
|
|
*/
|
2011-02-02 19:13:49 +07:00
|
|
|
if (invalidate & I915_GEM_DOMAIN_RENDER)
|
2015-01-22 20:42:00 +07:00
|
|
|
cmd |= MI_INVALIDATE_TLB;
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, cmd);
|
|
|
|
intel_ring_emit(engine,
|
|
|
|
I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
|
2016-05-06 21:40:21 +07:00
|
|
|
if (INTEL_GEN(req->i915) >= 8) {
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, 0); /* upper addr */
|
|
|
|
intel_ring_emit(engine, 0); /* value */
|
2013-11-03 11:07:13 +07:00
|
|
|
} else {
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_emit(engine, 0);
|
|
|
|
intel_ring_emit(engine, MI_NOOP);
|
2013-11-03 11:07:13 +07:00
|
|
|
}
|
2016-03-16 18:00:36 +07:00
|
|
|
intel_ring_advance(engine);
|
2013-06-07 02:58:16 +07:00
|
|
|
|
2011-01-05 00:34:02 +07:00
|
|
|
return 0;
|
2010-11-02 15:31:01 +07:00
|
|
|
}
|
|
|
|
|
2016-06-29 22:09:20 +07:00
|
|
|
static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
engine->write_tail = ring_write_tail;
|
2016-06-29 22:09:21 +07:00
|
|
|
|
2016-06-29 22:09:22 +07:00
|
|
|
if (INTEL_GEN(dev_priv) >= 6) {
|
2016-06-29 22:09:21 +07:00
|
|
|
engine->add_request = gen6_add_request;
|
2016-06-29 22:09:22 +07:00
|
|
|
engine->irq_seqno_barrier = gen6_seqno_barrier;
|
|
|
|
} else {
|
2016-06-29 22:09:21 +07:00
|
|
|
engine->add_request = i9xx_add_request;
|
2016-06-29 22:09:22 +07:00
|
|
|
}
|
2016-06-29 22:09:23 +07:00
|
|
|
|
|
|
|
if (INTEL_GEN(dev_priv) >= 8) {
|
|
|
|
engine->irq_get = gen8_ring_get_irq;
|
|
|
|
engine->irq_put = gen8_ring_put_irq;
|
|
|
|
} else if (INTEL_GEN(dev_priv) >= 6) {
|
|
|
|
engine->irq_get = gen6_ring_get_irq;
|
|
|
|
engine->irq_put = gen6_ring_put_irq;
|
|
|
|
} else if (INTEL_GEN(dev_priv) >= 5) {
|
|
|
|
engine->irq_get = gen5_ring_get_irq;
|
|
|
|
engine->irq_put = gen5_ring_put_irq;
|
|
|
|
} else if (INTEL_GEN(dev_priv) >= 3) {
|
|
|
|
engine->irq_get = i9xx_ring_get_irq;
|
|
|
|
engine->irq_put = i9xx_ring_put_irq;
|
|
|
|
} else {
|
|
|
|
engine->irq_get = i8xx_ring_get_irq;
|
|
|
|
engine->irq_put = i8xx_ring_put_irq;
|
|
|
|
}
|
2016-06-29 22:09:20 +07:00
|
|
|
}
|
|
|
|
|
2010-09-16 09:43:11 +07:00
|
|
|
int intel_init_render_ring_buffer(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 18:27:19 +07:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = &dev_priv->engine[RCS];
|
2014-06-30 23:53:37 +07:00
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
int ret;
|
2010-09-16 09:43:11 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->name = "render ring";
|
|
|
|
engine->id = RCS;
|
|
|
|
engine->exec_id = I915_EXEC_RENDER;
|
2016-04-29 19:18:23 +07:00
|
|
|
engine->hw_id = 0;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->mmio_base = RENDER_RING_BASE;
|
2012-04-12 03:12:48 +07:00
|
|
|
|
2016-06-29 22:09:20 +07:00
|
|
|
intel_ring_default_vfuncs(dev_priv, engine);
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8) {
|
|
|
|
if (i915_semaphore_is_enabled(dev_priv)) {
|
2016-04-23 01:14:32 +07:00
|
|
|
obj = i915_gem_object_create(dev, 4096);
|
2016-04-25 19:32:13 +07:00
|
|
|
if (IS_ERR(obj)) {
|
2014-06-30 23:53:37 +07:00
|
|
|
DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
|
|
|
|
i915.semaphores = 0;
|
|
|
|
} else {
|
|
|
|
i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
|
|
|
|
ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
|
|
|
|
if (ret != 0) {
|
|
|
|
drm_gem_object_unreference(&obj->base);
|
|
|
|
DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
|
|
|
|
i915.semaphores = 0;
|
|
|
|
} else
|
|
|
|
dev_priv->semaphore_obj = obj;
|
|
|
|
}
|
|
|
|
}
|
2014-10-07 21:21:26 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->init_context = intel_rcs_ctx_init;
|
2016-04-29 19:18:21 +07:00
|
|
|
engine->add_request = gen8_render_add_request;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->flush = gen8_render_ring_flush;
|
|
|
|
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
|
2016-04-09 16:57:54 +07:00
|
|
|
engine->get_seqno = ring_get_seqno;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->set_seqno = ring_set_seqno;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (i915_semaphore_is_enabled(dev_priv)) {
|
2014-06-30 23:53:37 +07:00
|
|
|
WARN_ON(!dev_priv->semaphore_obj);
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->semaphore.sync_to = gen8_ring_sync;
|
|
|
|
engine->semaphore.signal = gen8_rcs_signal;
|
|
|
|
GEN8_RING_SEMAPHORE_INIT(engine);
|
2014-06-30 23:53:36 +07:00
|
|
|
}
|
2016-05-06 21:40:21 +07:00
|
|
|
} else if (INTEL_GEN(dev_priv) >= 6) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->init_context = intel_rcs_ctx_init;
|
|
|
|
engine->flush = gen7_render_ring_flush;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_GEN6(dev_priv))
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->flush = gen6_render_ring_flush;
|
|
|
|
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
|
2016-04-09 16:57:54 +07:00
|
|
|
engine->get_seqno = ring_get_seqno;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->set_seqno = ring_set_seqno;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (i915_semaphore_is_enabled(dev_priv)) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->semaphore.sync_to = gen6_ring_sync;
|
|
|
|
engine->semaphore.signal = gen6_signal;
|
2014-06-30 23:53:36 +07:00
|
|
|
/*
|
|
|
|
* The current semaphore is only applied on pre-gen8
|
|
|
|
* platform. And there is no VCS2 ring on the pre-gen8
|
|
|
|
* platform. So the semaphore between RCS and VCS2 is
|
|
|
|
* initialized as INVALID. Gen8 will initialize the
|
|
|
|
* sema between VCS2 and RCS later.
|
|
|
|
*/
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
|
|
|
|
engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
|
|
|
|
engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
|
|
|
|
engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
|
|
|
|
engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
|
|
|
|
engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
|
|
|
|
engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
|
|
|
|
engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
|
|
|
|
engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
|
|
|
|
engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
|
2014-06-30 23:53:36 +07:00
|
|
|
}
|
2016-05-06 21:40:21 +07:00
|
|
|
} else if (IS_GEN5(dev_priv)) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->add_request = pc_render_add_request;
|
|
|
|
engine->flush = gen4_render_ring_flush;
|
|
|
|
engine->get_seqno = pc_render_get_seqno;
|
|
|
|
engine->set_seqno = pc_render_set_seqno;
|
|
|
|
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
|
2013-05-29 09:22:29 +07:00
|
|
|
GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
|
2012-04-12 03:12:48 +07:00
|
|
|
} else {
|
2016-05-06 21:40:21 +07:00
|
|
|
if (INTEL_GEN(dev_priv) < 4)
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->flush = gen2_render_ring_flush;
|
2012-04-18 17:12:11 +07:00
|
|
|
else
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->flush = gen4_render_ring_flush;
|
|
|
|
engine->get_seqno = ring_get_seqno;
|
|
|
|
engine->set_seqno = ring_set_seqno;
|
|
|
|
engine->irq_enable_mask = I915_USER_INTERRUPT;
|
2010-12-04 18:30:53 +07:00
|
|
|
}
|
2014-06-30 23:53:36 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_HASWELL(dev_priv))
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
|
2016-05-06 21:40:21 +07:00
|
|
|
else if (IS_GEN8(dev_priv))
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
|
2016-05-06 21:40:21 +07:00
|
|
|
else if (INTEL_GEN(dev_priv) >= 6)
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
|
2016-05-06 21:40:21 +07:00
|
|
|
else if (INTEL_GEN(dev_priv) >= 4)
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->dispatch_execbuffer = i965_dispatch_execbuffer;
|
2016-05-06 21:40:21 +07:00
|
|
|
else if (IS_I830(dev_priv) || IS_845G(dev_priv))
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->dispatch_execbuffer = i830_dispatch_execbuffer;
|
2012-04-12 03:12:56 +07:00
|
|
|
else
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->dispatch_execbuffer = i915_dispatch_execbuffer;
|
|
|
|
engine->init_hw = init_render_ring;
|
|
|
|
engine->cleanup = render_ring_cleanup;
|
2012-04-12 03:12:48 +07:00
|
|
|
|
2012-12-17 22:21:27 +07:00
|
|
|
/* Workaround batchbuffer to combat CS tlb bug. */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (HAS_BROKEN_CS_TLB(dev_priv)) {
|
2016-04-23 01:14:32 +07:00
|
|
|
obj = i915_gem_object_create(dev, I830_WA_SIZE);
|
2016-04-25 19:32:13 +07:00
|
|
|
if (IS_ERR(obj)) {
|
2012-12-17 22:21:27 +07:00
|
|
|
DRM_ERROR("Failed to allocate batch bo\n");
|
2016-04-25 19:32:13 +07:00
|
|
|
return PTR_ERR(obj);
|
2012-12-17 22:21:27 +07:00
|
|
|
}
|
|
|
|
|
2014-02-14 20:01:14 +07:00
|
|
|
ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
|
2012-12-17 22:21:27 +07:00
|
|
|
if (ret != 0) {
|
|
|
|
drm_gem_object_unreference(&obj->base);
|
|
|
|
DRM_ERROR("Failed to ping batch bo\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->scratch.obj = obj;
|
|
|
|
engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
|
2012-12-17 22:21:27 +07:00
|
|
|
}
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
ret = intel_init_ring_buffer(dev, engine);
|
2014-11-20 06:33:06 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (INTEL_GEN(dev_priv) >= 5) {
|
2016-03-16 18:00:36 +07:00
|
|
|
ret = intel_init_pipe_control(engine);
|
2014-11-20 06:33:06 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2010-09-16 09:43:11 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
int intel_init_bsd_ring_buffer(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 18:27:19 +07:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = &dev_priv->engine[VCS];
|
2010-09-16 09:43:11 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->name = "bsd ring";
|
|
|
|
engine->id = VCS;
|
|
|
|
engine->exec_id = I915_EXEC_BSD;
|
2016-04-29 19:18:23 +07:00
|
|
|
engine->hw_id = 1;
|
2012-04-12 03:12:49 +07:00
|
|
|
|
2016-06-29 22:09:20 +07:00
|
|
|
intel_ring_default_vfuncs(dev_priv, engine);
|
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (INTEL_GEN(dev_priv) >= 6) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->mmio_base = GEN6_BSD_RING_BASE;
|
2012-04-12 03:12:55 +07:00
|
|
|
/* gen6 bsd needs a special wa for tail updates */
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_GEN6(dev_priv))
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->write_tail = gen6_bsd_ring_write_tail;
|
|
|
|
engine->flush = gen6_bsd_ring_flush;
|
2016-04-09 16:57:54 +07:00
|
|
|
engine->get_seqno = ring_get_seqno;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->set_seqno = ring_set_seqno;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->irq_enable_mask =
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->dispatch_execbuffer =
|
2013-11-03 11:07:12 +07:00
|
|
|
gen8_ring_dispatch_execbuffer;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (i915_semaphore_is_enabled(dev_priv)) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->semaphore.sync_to = gen8_ring_sync;
|
|
|
|
engine->semaphore.signal = gen8_xcs_signal;
|
|
|
|
GEN8_RING_SEMAPHORE_INIT(engine);
|
2014-06-30 23:53:36 +07:00
|
|
|
}
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
} else {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
|
|
|
|
engine->dispatch_execbuffer =
|
2013-11-03 11:07:12 +07:00
|
|
|
gen6_ring_dispatch_execbuffer;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (i915_semaphore_is_enabled(dev_priv)) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->semaphore.sync_to = gen6_ring_sync;
|
|
|
|
engine->semaphore.signal = gen6_signal;
|
|
|
|
engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
|
|
|
|
engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
|
|
|
|
engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
|
|
|
|
engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
|
|
|
|
engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
|
|
|
|
engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
|
|
|
|
engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
|
|
|
|
engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
|
|
|
|
engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
|
|
|
|
engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
|
2014-06-30 23:53:36 +07:00
|
|
|
}
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
}
|
2012-04-12 03:12:49 +07:00
|
|
|
} else {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->mmio_base = BSD_RING_BASE;
|
|
|
|
engine->flush = bsd_ring_flush;
|
|
|
|
engine->get_seqno = ring_get_seqno;
|
|
|
|
engine->set_seqno = ring_set_seqno;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (IS_GEN5(dev_priv)) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
|
2012-04-12 03:12:54 +07:00
|
|
|
} else {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
|
2012-04-12 03:12:54 +07:00
|
|
|
}
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->dispatch_execbuffer = i965_dispatch_execbuffer;
|
2012-04-12 03:12:49 +07:00
|
|
|
}
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->init_hw = init_ring_common;
|
2012-04-12 03:12:49 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
return intel_init_ring_buffer(dev, engine);
|
2010-09-16 09:43:11 +07:00
|
|
|
}
|
2010-10-19 17:19:32 +07:00
|
|
|
|
2014-04-17 09:37:37 +07:00
|
|
|
/**
|
2015-01-29 21:13:40 +07:00
|
|
|
* Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
|
2014-04-17 09:37:37 +07:00
|
|
|
*/
|
|
|
|
int intel_init_bsd2_ring_buffer(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
|
2016-03-16 18:00:36 +07:00
|
|
|
|
|
|
|
engine->name = "bsd2 ring";
|
|
|
|
engine->id = VCS2;
|
|
|
|
engine->exec_id = I915_EXEC_BSD;
|
2016-04-29 19:18:23 +07:00
|
|
|
engine->hw_id = 4;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->mmio_base = GEN8_BSD2_RING_BASE;
|
2016-06-29 22:09:20 +07:00
|
|
|
|
|
|
|
intel_ring_default_vfuncs(dev_priv, engine);
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->flush = gen6_bsd_ring_flush;
|
2016-04-09 16:57:54 +07:00
|
|
|
engine->get_seqno = ring_get_seqno;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->set_seqno = ring_set_seqno;
|
|
|
|
engine->irq_enable_mask =
|
2014-04-17 09:37:37 +07:00
|
|
|
GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->dispatch_execbuffer =
|
2014-04-17 09:37:37 +07:00
|
|
|
gen8_ring_dispatch_execbuffer;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (i915_semaphore_is_enabled(dev_priv)) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->semaphore.sync_to = gen8_ring_sync;
|
|
|
|
engine->semaphore.signal = gen8_xcs_signal;
|
|
|
|
GEN8_RING_SEMAPHORE_INIT(engine);
|
2014-06-30 23:53:37 +07:00
|
|
|
}
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->init_hw = init_ring_common;
|
2014-04-17 09:37:37 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
return intel_init_ring_buffer(dev, engine);
|
2014-04-17 09:37:37 +07:00
|
|
|
}
|
|
|
|
|
2010-10-19 17:19:32 +07:00
|
|
|
int intel_init_blt_ring_buffer(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 18:27:19 +07:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = &dev_priv->engine[BCS];
|
2016-03-16 18:00:36 +07:00
|
|
|
|
|
|
|
engine->name = "blitter ring";
|
|
|
|
engine->id = BCS;
|
|
|
|
engine->exec_id = I915_EXEC_BLT;
|
2016-04-29 19:18:23 +07:00
|
|
|
engine->hw_id = 2;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->mmio_base = BLT_RING_BASE;
|
2016-06-29 22:09:20 +07:00
|
|
|
|
|
|
|
intel_ring_default_vfuncs(dev_priv, engine);
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->flush = gen6_ring_flush;
|
2016-04-09 16:57:54 +07:00
|
|
|
engine->get_seqno = ring_get_seqno;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->set_seqno = ring_set_seqno;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->irq_enable_mask =
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (i915_semaphore_is_enabled(dev_priv)) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->semaphore.sync_to = gen8_ring_sync;
|
|
|
|
engine->semaphore.signal = gen8_xcs_signal;
|
|
|
|
GEN8_RING_SEMAPHORE_INIT(engine);
|
2014-06-30 23:53:36 +07:00
|
|
|
}
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
} else {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
|
|
|
|
engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (i915_semaphore_is_enabled(dev_priv)) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->semaphore.signal = gen6_signal;
|
|
|
|
engine->semaphore.sync_to = gen6_ring_sync;
|
2014-06-30 23:53:36 +07:00
|
|
|
/*
|
|
|
|
* The current semaphore is only applied on pre-gen8
|
|
|
|
* platform. And there is no VCS2 ring on the pre-gen8
|
|
|
|
* platform. So the semaphore between BCS and VCS2 is
|
|
|
|
* initialized as INVALID. Gen8 will initialize the
|
|
|
|
* sema between BCS and VCS2 later.
|
|
|
|
*/
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
|
|
|
|
engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
|
|
|
|
engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
|
|
|
|
engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
|
|
|
|
engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
|
|
|
|
engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
|
|
|
|
engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
|
|
|
|
engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
|
|
|
|
engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
|
|
|
|
engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
|
2014-06-30 23:53:36 +07:00
|
|
|
}
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
}
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->init_hw = init_ring_common;
|
2010-10-19 17:19:32 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
return intel_init_ring_buffer(dev, engine);
|
2010-10-19 17:19:32 +07:00
|
|
|
}
|
2012-07-20 18:41:08 +07:00
|
|
|
|
2013-05-29 09:22:23 +07:00
|
|
|
int intel_init_vebox_ring_buffer(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 18:27:19 +07:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = &dev_priv->engine[VECS];
|
2013-05-29 09:22:23 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->name = "video enhancement ring";
|
|
|
|
engine->id = VECS;
|
|
|
|
engine->exec_id = I915_EXEC_VEBOX;
|
2016-04-29 19:18:23 +07:00
|
|
|
engine->hw_id = 3;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->mmio_base = VEBOX_RING_BASE;
|
2016-06-29 22:09:20 +07:00
|
|
|
|
|
|
|
intel_ring_default_vfuncs(dev_priv, engine);
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->flush = gen6_ring_flush;
|
2016-04-09 16:57:54 +07:00
|
|
|
engine->get_seqno = ring_get_seqno;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->set_seqno = ring_set_seqno;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
|
2016-05-06 21:40:21 +07:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->irq_enable_mask =
|
2013-11-08 12:40:39 +07:00
|
|
|
GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (i915_semaphore_is_enabled(dev_priv)) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->semaphore.sync_to = gen8_ring_sync;
|
|
|
|
engine->semaphore.signal = gen8_xcs_signal;
|
|
|
|
GEN8_RING_SEMAPHORE_INIT(engine);
|
2014-06-30 23:53:36 +07:00
|
|
|
}
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
} else {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
|
|
|
|
engine->irq_get = hsw_vebox_get_irq;
|
|
|
|
engine->irq_put = hsw_vebox_put_irq;
|
|
|
|
engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
|
2016-05-06 21:40:21 +07:00
|
|
|
if (i915_semaphore_is_enabled(dev_priv)) {
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->semaphore.sync_to = gen6_ring_sync;
|
|
|
|
engine->semaphore.signal = gen6_signal;
|
|
|
|
engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
|
|
|
|
engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
|
|
|
|
engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
|
|
|
|
engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
|
|
|
|
engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
|
|
|
|
engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
|
|
|
|
engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
|
|
|
|
engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
|
|
|
|
engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
|
|
|
|
engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
|
2014-06-30 23:53:36 +07:00
|
|
|
}
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 11:07:09 +07:00
|
|
|
}
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->init_hw = init_ring_common;
|
2013-05-29 09:22:23 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
return intel_init_ring_buffer(dev, engine);
|
2013-05-29 09:22:23 +07:00
|
|
|
}
|
|
|
|
|
2012-07-20 18:41:08 +07:00
|
|
|
int
|
2015-05-29 23:43:55 +07:00
|
|
|
intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
|
2012-07-20 18:41:08 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2012-07-20 18:41:08 +07:00
|
|
|
int ret;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
if (!engine->gpu_caches_dirty)
|
2012-07-20 18:41:08 +07:00
|
|
|
return 0;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
|
2012-07-20 18:41:08 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2015-05-29 23:43:57 +07:00
|
|
|
trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
|
2012-07-20 18:41:08 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->gpu_caches_dirty = false;
|
2012-07-20 18:41:08 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
2015-05-29 23:43:53 +07:00
|
|
|
intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
|
2012-07-20 18:41:08 +07:00
|
|
|
{
|
2016-03-16 18:00:38 +07:00
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2012-07-20 18:41:08 +07:00
|
|
|
uint32_t flush_domains;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
flush_domains = 0;
|
2016-03-16 18:00:36 +07:00
|
|
|
if (engine->gpu_caches_dirty)
|
2012-07-20 18:41:08 +07:00
|
|
|
flush_domains = I915_GEM_GPU_DOMAINS;
|
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
|
2012-07-20 18:41:08 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2015-05-29 23:43:57 +07:00
|
|
|
trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
|
2012-07-20 18:41:08 +07:00
|
|
|
|
2016-03-16 18:00:36 +07:00
|
|
|
engine->gpu_caches_dirty = false;
|
2012-07-20 18:41:08 +07:00
|
|
|
return 0;
|
|
|
|
}
|
2014-04-09 15:19:41 +07:00
|
|
|
|
|
|
|
void
|
2016-03-16 18:00:40 +07:00
|
|
|
intel_stop_engine(struct intel_engine_cs *engine)
|
2014-04-09 15:19:41 +07:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2016-03-16 18:00:40 +07:00
|
|
|
if (!intel_engine_initialized(engine))
|
2014-04-09 15:19:41 +07:00
|
|
|
return;
|
|
|
|
|
2016-03-16 18:00:39 +07:00
|
|
|
ret = intel_engine_idle(engine);
|
drm/i915: Prevent leaking of -EIO from i915_wait_request()
Reporting -EIO from i915_wait_request() has proven very troublematic
over the years, with numerous hard-to-reproduce bugs cropping up in the
corner case of where a reset occurs and the code wasn't expecting such
an error.
If the we reset the GPU or have detected a hang and wish to reset the
GPU, the request is forcibly complete and the wait broken. Currently, we
report either -EAGAIN or -EIO in order for the caller to retreat and
restart the wait (if appropriate) after dropping and then reacquiring
the struct_mutex (essential to allow the GPU reset to proceed). However,
if we take the view that the request is complete (no further work will
be done on it by the GPU because it is dead and soon to be reset), then
we can proceed with the task at hand and then drop the struct_mutex
allowing the reset to occur. This transfers the burden of checking
whether it is safe to proceed to the caller, which in all but one
instance it is safe - completely eliminating the source of all spurious
-EIO.
Of note, we only have two API entry points where we expect that
userspace can observe an EIO. First is when submitting an execbuf, if
the GPU is terminally wedged, then the operation cannot succeed and an
-EIO is reported. Secondly, existing userspace uses the throttle ioctl
to detect an already wedged GPU before starting using HW acceleration
(or to confirm that the GPU is wedged after an error condition). So if
the GPU is wedged when the user calls throttle, also report -EIO.
v2: Split more carefully the change to i915_wait_request() and assorted
ABI from the reset handling.
v3: Add a couple of WARN_ON(EIO) to the interruptible modesetting code
so that we don't start to leak EIO there in future (and break our hang
resistant modesetting).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1460565315-7748-9-git-send-email-chris@chris-wilson.co.uk
Link: http://patchwork.freedesktop.org/patch/msgid/1460565315-7748-1-git-send-email-chris@chris-wilson.co.uk
2016-04-13 23:35:08 +07:00
|
|
|
if (ret)
|
2014-04-09 15:19:41 +07:00
|
|
|
DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
|
2016-03-16 18:00:37 +07:00
|
|
|
engine->name, ret);
|
2014-04-09 15:19:41 +07:00
|
|
|
|
2016-03-16 18:00:37 +07:00
|
|
|
stop_ring(engine);
|
2014-04-09 15:19:41 +07:00
|
|
|
}
|