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drm/i915/skl: Add GEN8_L3SQCREG4 to HW whitelist

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Required for WaDisableLSQCROPERFforOCL:skl

This register is added to HW whitelist to support WA required for future
enabling of pre-emptive command execution, WA implementation will be in
userspace and it cannot program this register if it is not on HW whitelist.

v2: explain purpose of changes (Chris)

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-7-git-send-email-arun.siluvery@linux.intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Arun Siluvery 2016-01-21 21:43:52 +00:00 committed by Daniel Vetter
parent a786d53a2c
commit 6107497eee
1 changed files with 5 additions and 0 deletions
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5
drivers/gpu/drm/i915/intel_ringbuffer.c
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@ -1098,6 +1098,11 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
/* WaDisableLSQCROPERFforOCL:skl */
ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4);
if (ret)
return ret;
return skl_tune_iz_hashing(ring);
}