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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/i915: i8xx interrupt handler
gen2 hardware has some significant differences from the other interrupt routines that were glossed over and then forgotten about in the transition to KMS. Such as - 16bit IIR - PendingFlip status bit This patch reintroduces a handler specifically for gen2 for the purpose of handling pageflips correctly, simplifying code in the process. v2: Also fixup ring get/put irq to only access 16bit registers (Daniel) Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=24202 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41793 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: use posting_read16 in intel_ringbuffer.c and kill _driver from the function names.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Chris Wilson
Daniel Vetter
parent
1869b620d2
commit
c2798b19ba
@ -2446,6 +2446,152 @@ static void i915_driver_irq_uninstall(struct drm_device * dev)
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I915_WRITE(IIR, I915_READ(IIR));
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}
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static void i8xx_irq_preinstall(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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int pipe;
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atomic_set(&dev_priv->irq_received, 0);
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for_each_pipe(pipe)
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I915_WRITE(PIPESTAT(pipe), 0);
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I915_WRITE16(IMR, 0xffff);
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I915_WRITE16(IER, 0x0);
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POSTING_READ16(IER);
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}
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static int i8xx_irq_postinstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
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dev_priv->pipestat[0] = 0;
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dev_priv->pipestat[1] = 0;
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I915_WRITE16(EMR,
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~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
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/* Unmask the interrupts that we always want on. */
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dev_priv->irq_mask =
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~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
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I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
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I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
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I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
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I915_WRITE16(IMR, dev_priv->irq_mask);
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I915_WRITE16(IER,
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I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
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I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
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I915_USER_INTERRUPT);
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POSTING_READ16(IER);
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return 0;
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}
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static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
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{
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struct drm_device *dev = (struct drm_device *) arg;
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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struct drm_i915_master_private *master_priv;
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u16 iir, new_iir;
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u32 pipe_stats[2];
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unsigned long irqflags;
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int irq_received;
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int pipe;
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u16 flip_mask =
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I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
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I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
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atomic_inc(&dev_priv->irq_received);
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iir = I915_READ16(IIR);
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if (iir == 0)
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return IRQ_NONE;
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while (iir & ~flip_mask) {
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/* Can't rely on pipestat interrupt bit in iir as it might
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* have been cleared after the pipestat interrupt was received.
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* It doesn't set the bit in iir again, but it still produces
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* interrupts (for non-MSI).
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*/
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
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i915_handle_error(dev, false);
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for_each_pipe(pipe) {
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int reg = PIPESTAT(pipe);
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pipe_stats[pipe] = I915_READ(reg);
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/*
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* Clear the PIPE*STAT regs before the IIR
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*/
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if (pipe_stats[pipe] & 0x8000ffff) {
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if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
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DRM_DEBUG_DRIVER("pipe %c underrun\n",
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pipe_name(pipe));
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I915_WRITE(reg, pipe_stats[pipe]);
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irq_received = 1;
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}
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}
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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I915_WRITE16(IIR, iir & ~flip_mask);
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new_iir = I915_READ16(IIR); /* Flush posted writes */
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if (dev->primary->master) {
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master_priv = dev->primary->master->driver_priv;
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if (master_priv->sarea_priv)
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master_priv->sarea_priv->last_dispatch =
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READ_BREADCRUMB(dev_priv);
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}
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if (iir & I915_USER_INTERRUPT)
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notify_ring(dev, &dev_priv->ring[RCS]);
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if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
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drm_handle_vblank(dev, 0)) {
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if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
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intel_prepare_page_flip(dev, 0);
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intel_finish_page_flip(dev, 0);
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flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
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}
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}
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if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
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drm_handle_vblank(dev, 1)) {
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if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
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intel_prepare_page_flip(dev, 1);
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intel_finish_page_flip(dev, 1);
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flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
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}
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}
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iir = new_iir;
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}
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return IRQ_HANDLED;
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}
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static void i8xx_irq_uninstall(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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int pipe;
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dev_priv->vblank_pipe = 0;
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for_each_pipe(pipe) {
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/* Clear enable bits; then clear status bits */
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I915_WRITE(PIPESTAT(pipe), 0);
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I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
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}
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I915_WRITE16(IMR, 0xffff);
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I915_WRITE16(IER, 0x0);
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I915_WRITE16(IIR, I915_READ16(IIR));
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}
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void intel_irq_init(struct drm_device *dev)
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{
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dev->driver->get_vblank_counter = i915_get_vblank_counter;
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@ -2485,10 +2631,17 @@ void intel_irq_init(struct drm_device *dev)
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dev->driver->enable_vblank = ironlake_enable_vblank;
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dev->driver->disable_vblank = ironlake_disable_vblank;
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} else {
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dev->driver->irq_preinstall = i915_driver_irq_preinstall;
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dev->driver->irq_postinstall = i915_driver_irq_postinstall;
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dev->driver->irq_uninstall = i915_driver_irq_uninstall;
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dev->driver->irq_handler = i915_driver_irq_handler;
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if (INTEL_INFO(dev)->gen == 2) {
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dev->driver->irq_preinstall = i8xx_irq_preinstall;
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dev->driver->irq_postinstall = i8xx_irq_postinstall;
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dev->driver->irq_handler = i8xx_irq_handler;
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dev->driver->irq_uninstall = i8xx_irq_uninstall;
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} else {
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dev->driver->irq_preinstall = i915_driver_irq_preinstall;
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dev->driver->irq_postinstall = i915_driver_irq_postinstall;
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dev->driver->irq_uninstall = i915_driver_irq_uninstall;
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dev->driver->irq_handler = i915_driver_irq_handler;
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}
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dev->driver->enable_vblank = i915_enable_vblank;
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dev->driver->disable_vblank = i915_disable_vblank;
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}
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@ -678,6 +678,41 @@ i9xx_ring_put_irq(struct intel_ring_buffer *ring)
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spin_unlock(&ring->irq_lock);
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}
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static bool
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i8xx_ring_get_irq(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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if (!dev->irq_enabled)
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return false;
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spin_lock(&ring->irq_lock);
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if (ring->irq_refcount++ == 0) {
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dev_priv->irq_mask &= ~ring->irq_enable_mask;
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I915_WRITE16(IMR, dev_priv->irq_mask);
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POSTING_READ16(IMR);
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}
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spin_unlock(&ring->irq_lock);
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return true;
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}
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static void
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i8xx_ring_put_irq(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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spin_lock(&ring->irq_lock);
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if (--ring->irq_refcount == 0) {
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dev_priv->irq_mask |= ring->irq_enable_mask;
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I915_WRITE16(IMR, dev_priv->irq_mask);
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POSTING_READ16(IMR);
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}
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spin_unlock(&ring->irq_lock);
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}
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void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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@ -1310,8 +1345,13 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
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else
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ring->flush = gen4_render_ring_flush;
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ring->get_seqno = ring_get_seqno;
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ring->irq_get = i9xx_ring_get_irq;
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ring->irq_put = i9xx_ring_put_irq;
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if (IS_GEN2(dev)) {
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ring->irq_get = i8xx_ring_get_irq;
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ring->irq_put = i8xx_ring_put_irq;
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} else {
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ring->irq_get = i9xx_ring_get_irq;
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ring->irq_put = i9xx_ring_put_irq;
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}
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ring->irq_enable_mask = I915_USER_INTERRUPT;
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}
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ring->write_tail = ring_write_tail;
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@ -1358,8 +1398,13 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
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else
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ring->flush = gen4_render_ring_flush;
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ring->get_seqno = ring_get_seqno;
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ring->irq_get = i9xx_ring_get_irq;
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ring->irq_put = i9xx_ring_put_irq;
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if (IS_GEN2(dev)) {
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ring->irq_get = i8xx_ring_get_irq;
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ring->irq_put = i8xx_ring_put_irq;
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} else {
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ring->irq_get = i9xx_ring_get_irq;
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ring->irq_put = i9xx_ring_put_irq;
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}
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ring->irq_enable_mask = I915_USER_INTERRUPT;
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ring->write_tail = ring_write_tail;
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if (INTEL_INFO(dev)->gen >= 4)
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