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drm/i915/gen8: Add gen8_init_workarounds for common WA

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WA in this function should be ordered based on register address.
The following order is suggested (Ville),

instpm
mi_mode
row chicken
half slice chicken
common slice chicken
hdc chicken
cache_mode_0
cache_mode_1
gt_mode

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Arun Siluvery 2015-09-25 17:40:37 +01:00 committed by Daniel Vetter
parent 010e9f5fad
commit e9a64adaec
1 changed files with 16 additions and 0 deletions
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16
drivers/gpu/drm/i915/intel_ringbuffer.c
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@ -800,11 +800,22 @@ static int wa_add(struct drm_i915_private *dev_priv,
#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
static int gen8_init_workarounds(struct intel_engine_cs *ring)
{
return 0;
}
static int bdw_init_workarounds(struct intel_engine_cs *ring)
{
int ret;
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
ret = gen8_init_workarounds(ring);
if (ret)
return ret;
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
/* WaDisableAsyncFlipPerfMode:bdw */
@ -868,9 +879,14 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
static int chv_init_workarounds(struct intel_engine_cs *ring)
{
int ret;
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
ret = gen8_init_workarounds(ring);
if (ret)
return ret;
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
/* WaDisableAsyncFlipPerfMode:chv */