The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch>
Acked-by: Hans de Goede <hdegoede@redhat.com>
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
The A80 Optimus Board is was launched with the Allwinner A80 SoC.
It was jointly developed by Allwinner and Merrii.
This board has a UART port, a JTAG connector, USB host ports, a USB
3.0 OTG connector, an HDMI output, a micro SD slot, 8G NAND flash,
4G DRAM, a camera sensor interface, a WiFi/BT combo chip, a headphone
jack, IR receiver, and additional GPIO headers.
This patch adds only basic support.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Andreas Färber <afaerber@suse.de>
The Allwinner A80 is a new multi-purpose SoC with 4 Cortex-A7 and
4 Cortex-A15 cores in a big.LITTLE architecture, and a 64-core
PowerVR G6230 GPU.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Andreas Färber <afaerber@suse.de>
This adds support for the Olimex A20-OLinuXino-Lime2
https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXIno-LIME2
Differences to previous Lime boards are 1GB RAM and gigabit ethernet
Signed-off-by: Iain Paton <ipaton0@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Mele M3 is yet another Allwinnner based Android top set box from Mele.
It uses a housing similar to the A2000, but without the USM sata storage slot
at the top.
It features an A20 SoC, 1G RAM, 4G eMMC (unique for Allwinner devices),
100Mbit ethernet, HDMI out, 3 USB A receptacles, VGA, and A/V OUT connections.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Banana Pi is an A20 based development board using Raspberry Pi compatible
IO headers. It comes with 1 GB RAM, 1 Gb ethernet, 2x USB host, sata, hdmi
and stereo audio out + various expenansion headers:
http://www.lemaker.org/
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The uart3_pins_a multiplexes the uart3 pins to port G, add a pinctrl entry
for mapping them to port H (as used on the Bananapi).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The PCI/MSI irq chip callbacks mask/unmask_msi_irq have been renamed
to pci_msi_mask/unmask_irq to mark them PCI specific. Rename all usage
sites. The conversion helper functions are kept around to avoid
conflicts in next and will be removed after merging into mainline.
Coccinelle assisted conversion. No functional change.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Chris Metcalf <cmetcalf@tilera.com>
Cc: x86@kernel.org
Cc: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Simon Horman <horms@verge.net.au>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Yijing Wang <wangyijing@huawei.com>
Rename write_msi_msg() to pci_write_msi_msg() to mark it as PCI
specific.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Yingjoe Chen <yingjoe.chen@mediatek.com>
Cc: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
All chips of i.mx6 can be powered off by programming SNVS.
For example :
On i.mx6q-sabresd board, PMIC_ON_REQ connect with external
pmic ON/OFF pin, that will cause the whole PMIC powered off
except VSNVS. And system can restart once PMIC_ON_REQ goes
high by push POWRER key.
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add structure of USB supply logic. The USB hosts power enable
regulator is needed to control VBUS supply on the Colibri carrier
board.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add CAN support for Phytec phyFLEX-i.MX6 (PFL-A-02 and PBA-B-01).
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add PCIe support for Phytec phyFLEX-i.MX6 (PFL-A-02 and PBA-B-01).
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The PMIC interrupt was changed from modul revision 1 to 2. Revision 1 was
declared as a prototype and is not in series by any customers.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The nand is on the module (PFL-A-02) and not on the baseboard (PBA-B-01).
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
ST-M41T0M6 is available on Colibri carrier boards.
Hence enable M41T0M6 RTC.
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds links to the on-chip SRAM and reset controller nodes
and switches the interrupts. Make the BIT processor interrupt, which exists on
all variants, the first one. The JPEG unit interrupt, which does not exist on
i.MX27 and i.MX5 thus is an optional second interrupt.
Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to
load separate firmware images for some reason.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
imx6q-tbs2910 board uses sgtl5000 codec and the machine file (imx-sgtl5000)
already sets SSI in slave mode and codec in master mode, so there is no need
for having this property.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Soeren Moch <smoch@web.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Since restructuring of the device tree files, the USB misc/phy
nodes are disabled by default. Hence we need to enable those
explicitly when USB is used.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Use GPIO support by adding SD card detection configuration and
GPIO pinmux for Colibri's standard GPIO pins. Attach the GPIO
pins to the iomuxc node to get the GPIO pin settings applied.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Since pins and frequency are specific to module (pfla02), not base board
(pbab02), it is better to be initialized in corresponding dts file.
This patch fixes i2c2, i2c3 pin configuration which caused messages:
imx6q-pinctrl 20e0000.iomuxc: no groups defined in /soc/aips-bus@02000000/iomuxc@020e0000/i2c2grp
imx6q-pinctrl 20e0000.iomuxc: no groups defined in /soc/aips-bus@02000000/iomuxc@020e0000/i2c3grp
imx6q-pinctrl 20e0000.iomuxc: unable to find group for node i2c2grp
imx6q-pinctrl 20e0000.iomuxc: unable to find group for node i2c3grp
Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add Colibri VF50 device tree files vf500-colibri.dtsi and
vf500-colibri-eval-v3.dts, in line with the Colibri VF61 device tree
files. However, to minimize dupplication we also add vf-colibri.dtsi
and vf-colibri-eval-v3.dtsi which contain the common device tree
nodes.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This adds more generic base device trees for Vybrid SoCs. There
are three series of Vybrid SoC commonly available:
- VF3xx series: single core, Cortex-A5 without external memory
- VF5xx series: single core, Cortex-A5
- VF6xx series: dual core, Cortex-A5/Cortex-M4
The second digit represents the presents of a L2 cache (VFx1x).
The VF3xx series are not suitable for Linux especially since the
internal memory is quite small (1.5MiB).
The VF500 is essentially the base SoC, with only one core and
without L1 cache. The VF610 is a superset of the VF500, hence
vf500.dtsi is then included and enhanced by vf610.dtsi. There is
no board using VF510 or VF600 currently, but, if needed, they can
be added easily.
The Linux kernel can also run on the Cortex-M4 CPU of Vybrid
using !MMU support. This patchset creates a device tree structure
which allows to share peripherals nodes for a VF6xx Cortex-M4
device tree too. The two CPU types have different views of the
system: Foremost they are using different interrupt controllers,
but also the memory map is slightly different. The base device
tree vfxxx.dtsi allows to create SoC and board level device trees
supporting the Cortex-M4 while reusing the shared peripherals
nodes.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The clock controller module (CCM) has several clock inputs, which
are connected to external crystal oscillators. To reflect this,
assign these fixed clocks to the CCM node directly.
This especially resolves initialization order dependencies we had
with the earlier initialization code: When resolving of the fixed
clocks failed in clk-vf610, the code created fixed clocks with a
rate of 0.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The LS1021A TWR is a low cost, high-performance evaluation,
development and test platform supporting the LS1021A processor.
It is optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
For more detail information about the LS1021A TWR board, please
refer to LS1021A QorIQ Tower System Reference Manual.
Signed-off-by: Chao Fu <B44548@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The LS1021A QorIQ development system (QDS) is a high-performance
computing evaluation, development and test platform supporting
the LS1021A processor. The LS1021A QDS is optimized to support
the high-bandwidth DDR3LP/DDR4 memory and a full complement of
high-speed SerDes ports.
For more detail information about the LS1021AQDS, please refer to
the QorIQ LS1021A Development System Reference Manual.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Chao Fu <B44548@freescale.com>
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
On registration I2C bus drivers attemp to get ids from device tree
aliases, add a missing alias for I2C4 found on iMX6 DualLite/Solo.
Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
TBS2910 is a i.MX6Q based board. For additional details refer to
http://www.tbsdtv.com/products/tbs2910-matrix-arm-mini-pc.html
Signed-off-by: Soeren Moch <smoch@web.de>
Reviewed-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add enet2 support for imx6sx-sdb board, and add the "fsl,imx6q-fec"
compatible for fec2 node to be compatible with the old version.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add all required properties for the cpufreq-dt driver.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The Colibri standard defines four pins as PWM outputs, two of them (PWM
A and C) are routed to FTM instance 0 and the other two (PWM B and D)
are routed to FTM instance 1. Hence enable both FTM instances for the
Colibri module and mux the four pins accordingly.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add Global Timer support which is part of the private peripherals
of the Cortex-A5 processor. This Global Timer is compatible with the
Cortex-A9 implementation. It's a 64-bit timer and is clocked by the
peripheral clock, which is typically 133 or 166MHz on Vybrid.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
SSI block has 'ipg' clock for internal peripheral access and also 'baud' clock
for generating bit clock when SSI operates in master mode.
Add the extra 'baud' clock so that we can have SSI functional in master mode.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
SSI block has 'ipg' clock for internal peripheral access and also 'baud' clock
for generating bit clock when SSI operates in master mode.
Add the extra 'baud' clock so that we can have SSI functional in master mode.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The newly introduced LS1021A SoC selects CONFIG_SOC_FSL, which
is originally symbol used for the PowerPC based platforms
and guards lots of code that does not build on ARM.
This breaks allmodconfig, so let's remove it for now, until
either all those drivers are fixed or they use a dependency
on IMX instead.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
With the clock assignment device tree changes, the clocks get
initialized properly but the search for those clocks fails with
errors:
[ 0.000000] i.MX clk 4: register failed with -17
[ 0.000000] i.MX clk 5: register failed with -17
This is because the module can't find those clocks anymore, and
tries to initialize fixed clocks with the same name.
Get the clock modules input clocks from the assigned clocks by
default by using of_clk_get_by_name(). If this function returns
not a valid clock, fall back to the old behaviour and search the
input clock from the device tree's /clocks/$name node.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Freescale LS1021A SoCs deploy two cortex-A7 processors,
this adds bring-up support for the secondary core.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The LS1021A SoC is a dual-core Cortex-A7 based processor,
this adds the initial support for it.
Signed-off-by: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Instanciate device for the generic cpufreq-dt driver.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The ARM clock is a virtual clock feeding the ARM partition of
the SoC. It controls multiple other clocks to ensure the right
sequencing when cpufreq changes the CPU clock rate.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This implements a virtual clock used to abstract away
all the steps needed in order to change the ARM clock,
so we don't have to push all this clock handling into
the cpufreq driver.
While it will be used for i.MX53 at first it is generic
enough to be used on i.MX6 later on.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This is the bypass clock used to feed the ARM partition
while we reprogram PLL1 to another rate.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add the ARM Global Timer as clocksource/scheduler clock option and
use it as default scheduler clock. This leaves the PIT timer for
other users e.g. the secondary Cortex-M4 core. Also, the Global Timer
has double the precission (running at pheripheral clock compared to
IPG clock) and a 64-bit incrementing counter register. We still keep
the PIT timer as an secondary option in case the ARM Global Timer is
not available.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
For LPDDR2 platform, no need to enable weak2P5 in DSM mode,
it can be pulled down to save power(~0.65mW).
And per design team's recommendation, we should disconnect
VDDHIGH and SNVS in DSM mode on i.MX6SL.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3,
we used cpu type to decide how to do these settings in suspend
before which is NOT flexible, take i.MX6SL for example, although
it has LPDDR2 on EVK board, but users can also use DDR3 on other
boards, so it is better to read the DDR type from MMDC then decide
how to do related settings.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Stock firmware on rk3288 does not initizalize the CNTVOFF registers
of the architected timer correctly. This introduces issues with the
newly added SMP support for rk3288, resulting in rcu stalls due to
differing timer values per core.
There exist preliminary and tested patches for u-boot for this problem,
but there are a minority of boards using other bootloaders like coreboot.
There also is currently a second solution for miss-initialized architected
timers in the works:
- clocksource: arch_timer: Fix code to use physical timers when requested
- clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers
Therefore disable smp on rk3288 again till these are finalized, also
allowing coreboot-based boards to boot again.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
sclk_mfc is required for MFC device since commit
0c2272170d ("media: s5p-mfc: rename
special clock to sclk_mfc"), so add it to exynos4 dts.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This ensures the core and the audio subsystem clocks are configured
properly, as expected by the sound machine driver. These bits are
missing to obtain proper audio sample rates in kernel v3.17, where
audio support for Odroid X2/U3 was first added.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The HP Chromebook 11 uses an Atmel maXTouch as trackpad.
The keymap was found by trial-and-error.
Signed-off-by: Andreas Faerber <afaerber@suse.de>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Spotted in the Chrome OS 3.8 based device tree.
Needs CONFIG_SENSORS_LM90.
Signed-off-by: Andreas Faerber <afaerber@suse.de>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Reported-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Andreas Faerber <afaerber@suse.de>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds max77693-haptic node to support for haptic motor driver.
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch add PWM(Pulse Width Modulation) node and
handle to use pwm property.
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Specify the default mux and divider clocks in device tree
to ensure the FIMC devices on Trats, Trats2, Universal_c210
and Odroid X2/U3 boards are clocked from recommended clock
source and with maximum supported frequency.
For Trats2 also the MIPI-CSIS and the camera sensor clocks
are configured, the 'clock-frequency' property is deprecated
in favour of 'assigned-clock-rates' property.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Let's register restart handler from PMU driver for restart
functionality. So that we can remove restart hooks from
machine specific file, and thus moving ahead when PMU moved
to driver folder, this functionality can be reused for ARM64
based Exynos SoC's.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Let's register restart handler for Exynos5440 from it's clock driver
for restart functionality. So that we can cleanup restart hooks from
machine specific file.
CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
CC: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch enables support for TMU at Exynos4412 based Trats2 board.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The TMU device tree node definition for Exynos4x12 family of SoCs.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Synology DS414 is a 4-bay NAS powered by a Marvell Armada XP
(mv78230 dual-core @1.33Ghz). It is very similar on many aspects
to previous 4-bay synology models based on Marvell kirkwood SoC.
Here is a short summary of the device:
- 1GB RAM
- Boot on SPI flash (64Mbit Micron N25Q064)
- 2 GbE interfaces (Armada MAC connected to two Marvell 88E1512
PHY via RGMII)
- 1 front USB 2.0 ports (directly handled by the Armada 370)
- 2 rear USB 3.0 ports (handled by an EtronTech EJ168A XHCI
controller on the PCIe bus)
- 4 internal SATA ports handled by a Marvell 88SX7042 SATA-II
controller on the PCIe bus)
- Seiko S-35390A I2C RTC chip
- UART0 providing serial console
- UART1 used for poweroff (connected to a Microchip PIC16F883)
Additional note: the front LEDs the and the two fans are not directly
connected to the SoC and under its control. The former are presumably
driven by the SATA controller, the latter by the PIC.
[ jac: fixed up s/ge[01]_rgmii_pins/pmx_ge[01]_rgmii/ to match
armada-xp.dtsi ]
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/5b678d6d1f2f42f4bf0d087878b9d8024d463ea7.1416613429.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Synology DS213j is a 2-bay NAS powered by a Marvell Armada 370
(88F6710 @1.2Ghz). It is very similar on many aspects to previous
2-bay synology models based on Marvell kirkwood SoC. Here is a
short summary of the device:
- 512MB RAM
- boot on SPI flash (64Mbit Micron N25Q064)
- 1 GbE interface (Armada MAC connected to a Marvell 88E1512
PHY via SGMII)
- 2 rear USB 2.0 ports (directly handled by the Armada 370)
- 2 internal SATA ports handled by the Armada 370: 2 GPIO for
presence, 2 for powering them
- two front amber LED (disk1, disk2) controlled by the SoC
- Seiko S-35390A I2C RTC chip
- UART0 providing serial console
- UART1 used for poweroff (connected to a TI MSP430F2111)
- Fan handled via 4 GPIO (3 for speed, 1 for alarm)
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/20f1a03897df1d825b62abdd525e588a8e39b3ec.1416613429.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch defines common Armada XP pinctrl settings in armada-xp.dtsi
for the supported SPI interface (MPP36-39) and use it as default
for Armada XP spi interface. That being done, it removes the now
redundant definitions in armada-xp-axpwifiap.dts.
Note: this patch has the potential to break out-of-tree users w/o
specific pinctrl settings for their spi interfaces if the default
above does not match their config (i.e. if they do not use CS0).
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/d404b7abd80ee5a0fd8e8d3586d33cd37740d589.1416613429.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch defines common Armada XP pinctrl settings for uart2 and
uart3 interfaces (uart0 and uart1 rx/tx do not rely on MPP):
uart2: MPP42-43 as default
uart3: MPP44-45 as default
Suggested-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/fd51c080c7139a67ec01df8d797f1e88ce557796.1416613429.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch defines common Armada 370 pinctrl settings for uart0 and
uart1 interfaces:
uart0: MPP0-1 as default
uart1: MPP41-42 as default
Note: this patch has the potential to break out-of-tree users w/o
specific pinctrl settings for their uart interfaces if the default
above does not match their config.
Suggested-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/31412e57955c98bc9cc47b70726b5072af945cc3.1416613429.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch defines common Armada 370 pinctrl settings for spi0 and spi1
interfaces:
spi0: MPP33-36 as default, MPP32,63-65 as available alternate config
spi1: MPP49-52 as default
Currently, the Armada 370 DB .dts file has no explicit pinctrl info
for the spi0 interface used to access the flash on the board. The
patch fixes that by also adding explicit pinctrl info (MPP32,63-65)
for this SPI interface.
Note: this patch has the potential to break out-of-tree users w/o
specific pinctrl settings for their spi interfaces if the default
above does not match their config.
Suggested-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/1e812eb63b37718e273463e22e4d7512f8f0b624.1416613429.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
What was done by Sebastian in 264a05e19b ("ARM: mvebu: armada-xp:
Add node alias to pinctrl and add base address") and 01c434225e
("ARM: mvebu: armada-xp: Use pinctrl node alias") can also be done for
Armada 370, i.e.
- Rename Armada 370 pinctrl node to pin-ctrl with its address encoded
- Add a node alias to access the pinctrl node easily.
- use the newly available alias in existing Armada 370 .dts files
We can even go a bit further by putting the pinctrl node definition in
armada-370-xp.dtsi, with only its reg property defined. This allows us
to then also use the newly defined node alias in armada-xp.dtsi,
armada-370.dtsi.
Suggested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Suggested-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/b54eb45e5242728aace3ce8aef2eae4251f8dea3.1416613429.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that labels for uartX are available in Marvell Armada .dtsi files,
this patch replaces the "/soc/internal-regs/serial@12000" found in
armada-xp-lenovo-ix4-300d.dts file for stdout-path property by the more
concise &uart0.
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Suggested-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/d1a883510e01f7f212a385e826dccbef903fae42.1416613429.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds uartX labels for Armada SoC serial nodes. This is
a preliminary work to be able to easily reference the serial lines
in Device Tree files. One expected use is when providing stdout-path
property for barebox.
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/0683d1a823fe9b75849f3dafcf1cf6ee291cdca6.1416613429.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
As reported by Andrew, the vendor prefix for Seiko Instruments, Inc.
S-35390A I2C RTC chip in kirkwood-synology.dtsi has a typo (ssi
instead of sii). This patches fixes it.
Note: i2c devices ignore the optional vendor prefix, which explains
why it worked with the typo and also why there is no backward
compatibility issues with the fix.
Reported-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/0444140a267d982c3e5f5f2b7b5f2dc41d010e2a.1416613429.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Commit a095b1c78a ("ARM: mvebu: sort DT nodes by address")
missed placing the system-controller in the correct order.
Fixes: a095b1c78a ("ARM: mvebu: sort DT nodes by address")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/20141114204333.GS27002@pengutronix.de
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Conflicts:
drivers/net/ieee802154/fakehard.c
A bug fix went into 'net' for ieee802154/fakehard.c, which is removed
in 'net-next'.
Add build fix into the merge from Stephen Rothwell in openvswitch, the
logging macros take a new initial 'log' argument, a new call was added
in 'net' so when we merge that in here we have to explicitly add the
new 'log' arg to it else the build fails.
Signed-off-by: David S. Miller <davem@davemloft.net>
Since many (most?) mvebu platforms have NAND or SPI flashes, it makes
sense to have CONFIG_MTD_BLOCK=y in mvebu_v7_defconfig. The vast
majority of the other ARM defconfigs have it enabled, including
mvebu_v5_defconfig.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1415873489-22446-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In order to update MAC address entries in the ethernet nodes in Device Tree
both mainline U-Boot and Barebox bootloaders accept the same format of aliases,
which is 'ethernetX', where X stands for an interface number.
Other platforms in the mainline Linux, that comprise ethernet references in
'/aliases' node (like various flavours of imx or sunXi), follow the naming
scheme described above.
This commit ajusts ethernet aliases of Marvell Armada 38x SoC to be properly
recognized by bootloaders' MAC address fixup routines.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1415980652-7429-5-git-send-email-mw@semihalf.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
For proper operation of Armada 38x SDHCI controller proper 'clocks' property
is sufficient. Therefore it is not useful to keep an additional
'clock-frequency' property in SDHCI controller node of board-level Device Tree
file for Armada 385 DB.
This commit gets rid of useless 'clock-frequency' property.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1415980652-7429-4-git-send-email-mw@semihalf.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Marvell Armada 38x SoC's SDHCI interface is capable of using 1.8v voltage,
needed for driving "UHS-I" SD cards at their full speed. It is not, however,
possible on the DB board. Due to physical connectivity connector supply is tied
to 3v and any attempt of changing voltage in order to operate in the fastest UHS
modes fails.
This patch enables equivalent SDHCI quirk in order to adjust controller
operation to system capabilities.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1415980652-7429-3-git-send-email-mw@semihalf.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit enables user-space access to I2C bus using char device.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1415980652-7429-6-git-send-email-mw@semihalf.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In the recent update of mvebu_v7_defconfig a config that enables sdhci-pxav3
driver, that supports SDHCI interface of Armada 38x SoC, disappeared.
This commit enables CONFIG_MMC_SDHCI_PXAV3 back.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Fixes fc9fa8714a ("ARM: mvebu: update v7 defconfig with useful options")
Link: https://lkml.kernel.org/r/1415980652-7429-2-git-send-email-mw@semihalf.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit implements the CPU hotplug support for the Marvell Armada
38x platform. Similarly to what was done for the Armada XP, this
commit:
* Implements the ->cpu_die() function of SMP operations by calling
armada_38x_do_cpu_suspend() to enter the deep idle state for
CPUs going offline.
* Implements a dummy ->cpu_kill() function, simply needed for the
kernel to know we have CPU hotplug support.
* The mvebu_cortex_a9_boot_secondary() function makes sure to wake up
the CPU if waiting in deep idle state by sending an IPI before
deasserting the CPUs from reset. This is because
mvebu_cortex_a9_boot_secondary() is now used in two different
situations: for the initial boot of secondary CPUs (where CPU reset
deassert is used to wake up CPUs) and for CPU hotplug (where an IPI
is used to take CPU out of deep idle).
* At boot time, we exit from the idle state in the
->smp_secondary_init() hook.
This commit has been tested using CPU hotplug through sysfs
(/sys/devices/system/cpu/cpuX/online) and using kexec.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1414669184-16785-5-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
During the secondary startup the SCU was assumed to be in normal
mode. It is not always the case, and especially after a kexec. This
commit adds the needed sequence to put the SCU in normal mode.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1414669184-16785-4-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This will allow reusing the same function in the secondary_startup
for the Cortex A9 SoC.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1414669184-16785-3-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch removes the unneeded include of the armada-370-xp.h header.
It also moves some declarations from this file into more accurate
places.
Finally, it also adds a comment explaining that we can't remove yet the
smp field in the dt machine struct due to backward compatibly of the
device tree.
In a few releases, when the old device tree will be obsolete, we will be
able to remove the smp field and then the armada-370-xp.h header.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1414669184-16785-2-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The coherency.c top-level comment mentions that it supports the
coherency fabric for Armada 370 and XP, but it also supports the
coherency fabric on Armada 375 and 38x, so this commit updates the
comment accordingly.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This reverts commit 5ab5afd8ba ("ARM: mvebu: implement Armada 375
coherency workaround"), since we are removing the support for the very
early Z1 revision of the Armada 375 SoC.
This commit is an exact revert, with two exceptions:
- minor adaptations needed due to other changes that have taken place
in coherency.c since the original commit
- keep the definition of pr_fmt. This shouldn't originally have been
part of the Armada 375 Z1 workaround commit since it had nothing to
do with it.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Since commit b21dcafea3 ("arm: mvebu: remove dependency of SMP init
on static I/O mapping"), the COHERENCY_FABRIC_CFG_OFFSET register
offset definition is no longer used, so this commit removes it.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Enabling the hardware I/O coherency on Armada 370, Armada 375, Armada
38x and Armada XP requires a certain number of conditions:
- On Armada 370, the cache policy must be set to write-allocate.
- On Armada 375, 38x and XP, the cache policy must be set to
write-allocate, the pages must be mapped with the shareable
attribute, and the SMP bit must be set
Currently, on Armada XP, when CONFIG_SMP is enabled, those conditions
are met. However, when Armada XP is used in a !CONFIG_SMP kernel, none
of these conditions are met. With Armada 370, the situation is worse:
since the processor is single core, regardless of whether CONFIG_SMP
or !CONFIG_SMP is used, the cache policy will be set to write-back by
the kernel and not write-allocate.
Since solving this problem turns out to be quite complicated, and we
don't want to let users with a mainline kernel known to have
infrequent but existing data corruptions, this commit proposes to
simply disable hardware I/O coherency in situations where it is known
not to work.
And basically, the is_smp() function of the kernel tells us whether it
is OK to enable hardware I/O coherency or not, so this commit slightly
refactors the coherency_type() function to return
COHERENCY_FABRIC_TYPE_NONE when is_smp() is false, or the appropriate
type of the coherency fabric in the other case.
Thanks to this, the I/O coherency fabric will no longer be used at all
in !CONFIG_SMP configurations. It will continue to be used in
CONFIG_SMP configurations on Armada XP, Armada 375 and Armada 38x
(which are multiple cores processors), but will no longer be used on
Armada 370 (which is a single core processor).
In the process, it simplifies the implementation of the
coherency_type() function, and adds a missing call to of_node_put().
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Fixes: e60304f8cb ("arm: mvebu: Add hardware I/O Coherency support")
Cc: <stable@vger.kernel.org> # v3.8+
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The ll_add_cpu_to_smp_group(), ll_enable_coherency() and
ll_disable_coherency() are used on Armada XP to control the coherency
fabric. However, they make the assumption that the coherency fabric is
always available, which is currently a correct assumption but will no
longer be true with a followup commit that disables the usage of the
coherency fabric when the conditions are not met to use it.
Therefore, this commit modifies those functions so that they check the
return value of ll_get_coherency_base(), and if the return value is 0,
they simply return without configuring anything in the coherency
fabric.
The ll_get_coherency_base() function is also modified to properly
return 0 when the function is called with the MMU disabled. In this
case, it normally returns the physical address of the coherency
fabric, but we now check if the virtual address is 0, and if that's
case, return a physical address of 0 to indicate that the coherency
fabric is not enabled.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.8+
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds tscadc DT entries for am437x-gp-evm
and am43x-epos-evm.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add node for RTC.
Note that on dra7xx are no separate interrupts for alram
and timer unlike for SoCs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[nm@ti.com: update with rtc crossbar number]
Signed-off-by: Nishanth Menon <nm@ti.com>
[tony@atomide.com: updated comments]
Signed-off-by: Tony Lindgren <tony@atomide.com>
This adds support for the N900's battery to the
Nokia N900 DTS file.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The HDMI node does not have a power supply attached. As a result its
power regulator, VDAC, shuts off on boot and screen loses signal.
This attaches VDAC (vdda_hdmi_dac) to HDMI's vdda-supply.
Signed-off-by: Adam YH Lee <adam.yh.lee@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
If machine_desc.map_io is not set, devicemaps_init() in the common ARM
code will call debug_ll_io_init().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Since commit e409dfbfcc ("ASoC: dapm: Add a few supply widget sanity
checks") the following error is seen:
imx-wm8962 sound: wm8962 <-> 202c000.ssi mapping ok
imx-wm8962 sound: Connecting non-supply widget to supply widget is not supported (AMIC -> MICBIAS)
imx-wm8962 sound: ASoC: no dapm match for AMIC --> (null) --> MICBIAS
imx-wm8962 sound: ASoC: Failed to add route AMIC -> direct -> MICBIAS
Invert the route between the microphone and the bias in order to fix it.
While at it, align the audio routing with imx6sl-evk and imx6sx-sdb, which have
the same wm8962 circuitry.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Refactor mxc_iomux_mode():
- since it always returns 0 make it to return void
- remove unnecessary ret variable
- declare variables according to the kernel coding style
Signed-off-by: Dmitry Voytik <voytikd@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
ret variable is redundant. Call clk_pllv3_wait_lock() in the end
return.
Signed-off-by: Dmitry Voytik <voytikd@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
System restart mechanism has been changed with the introduction
of "kernel restart handler call chain support". The imx2 watchdog
based restart handler has been moved to the driver, and these
restart can be removed from the machine layer.
This patch cleans up the device tree version machine reset init with
mxc_arch_reset_init_dt and removes corresponding .restart handler,
for the .init_machine that can be handled by system default after
removing the mxc_arch_reset_init_dt, the .init_machine is also removed.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
imx6qdl-rex boards use sgtl5000 codec and the machine file (imx-sgtl5000)
already sets SSI in slave mode and codec in master mode, so there is no need
for having this property.
Cc: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
imx6qdl-gw5x boards use sgtl5000 codec and the machine file (imx-sgtl5000)
already sets SSI in slave mode and codec in master mode, so there is no need
for having this property.
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Use IMX6QDL_CLK_CKO definition instead of its hard coded clock number for better
readability.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This adds the NovaTech OrionLXm which is based on the AM335x SoC
http://www.novatechweb.com/substation-automation/orionlxm/
RAM: 512MiB
Flash: 4GB eMMC
Ethernet PHYs: 2x Micrel KSZ8041FTLI
USB ports are used internally by the expansion cards.
Internal micro SD slot is available.
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
- OMAP4/5: DSS hwmod cleanup patches from Tomi Valkeinen.
- DRA7xx: hwmod data support for UARTs 7 through 10.
- AM43xx: hwmod data support for the onboard ADC.
Basic build, boot, and PM test reports are here:
http://www.pwsan.com/omap/testlogs/omap-b-for-v3.19/20141121110550/
Note that I cannot test the DRA7xx or AM43xx patches, since I do not have
these boards.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUb48LAAoJEMePsQ0LvSpLiGoQAJvUltt1gZNMJ9gV0MWDnWKe
pexUhSDGdNZG20rKH3NXgdwbY3AycO77rZJh+Gcez9IoEWJU4SwAkgRUbgEIdprW
MDJ74WaRExg+j/FI6oHZ/mIKXS2GZlhu2eaeGB1bIEmDAmsxbaC5szISc3wygISp
7TJA/FDExDqzX4XY+ySC8gTf2iBqT5t4m78wbUo9onYVy7YVmIujDxfkYBnlXAXP
Jue1KVNVrzE6p05H7rDLyRezdpRKseZ0rsPN4aoRGmeJJl8mR85473o6QlYmnY+E
UCwoa36wVFnFYkUxP3qIEoXvnYA9cRL0l2zegAq0aYUKAgYHWt2eBRvCs90yehiq
v88GtQ1TS4mFjxbPLO1F9XWKoLu8N1v5g4xADE+kr64hwYHL0NLfBN3M4zyewlYE
NZ6c/zmYRFZ0CPFRBVzfcJ1PExB9XS8IDxjpvZaUNnb/AlcGw3mggUAN/qTYXBvZ
UIHEZUx2fxq30TkIPBI/BhBqRqxqMdIBjJhvsP0Kx3ZtivFnMIH/dPc8UdmVOqOv
d6BZYgLQMf0pgtuYOdP6FSYdfAbPfqKvAE4jfdxAld+LAmNtbURdKG5Xyl2N1lSq
ilWcRnsK6R2alxMi2xOXZhFWSP1cYHOmD1gsfLOZ0NieOHjoE6Zais/BFQu3N3xP
6O5w6cJRljIc5BlDG87A
=zeC6
-----END PGP SIGNATURE-----
Merge tag 'for-v3.19/omap-b2' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.19/soc
Several more OMAP patches targeted for v3.19. They include:
- OMAP4/5: DSS hwmod cleanup patches from Tomi Valkeinen.
- DRA7xx: hwmod data support for UARTs 7 through 10.
- AM43xx: hwmod data support for the onboard ADC.
Basic build, boot, and PM test reports are here:
http://www.pwsan.com/omap/testlogs/omap-b-for-v3.19/20141121110550/
Note that I cannot test the DRA7xx or AM43xx patches, since I do not have
these boards.
The omap2 camera driver has been deprecated for a year and is now
going to be removed. It is unmaintained and it uses an internal API
that has long since been superseded by a much better API. Worse, that
internal API has been abused by out-of-kernel trees (i.MX6).
In addition, Sakari stated that these drivers have never been in a
usable state in the mainline kernel due to missing platform data.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Acked-by: Sakari Ailus <sakari.ailus@iki.fi>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: David Cohen <dacohen@gmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
This patch adds hwmod support for ADC on AM43xx. Since clockdomain
and offsets of adc_tsc are different from AM33xx, ADC data has been
directly added to AM43xx hwmod file.
Signed-off-by: Vignesh R <vigneshr@ti.com>
[paul@pwsan.com: fixed spelling of "Anolog"; converted spaces to tabs]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
As the ARCH_AT91RM9200 is removed because being !DT, we use
the SOC_AT91RM9200 variant. This option can certainly be removed
once the ST driver is reworked a bit.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Second part of at91rm9200 legacy !DT removal. This is the core !DT support
removal for this Atmel SoC.
Note that from now on, the Kconfig.non_dt file and its specialized options are
completely removed.
Use the Device Tree for running this board with newer kernels.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Remove old board files that use at91rm9200 Atmel SoC. The
device tree is mature on this SoCs. It must be used now.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
There are no users of the struct hw_pci.add_bus() or .remove_bus() methods,
so remove the pointers from hw_pci. That makes pcibios_add_bus() and
pcibios_remove_bus() themselves superfluous, so remove them as well.
[bhelgaas: changelog]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Currently ARM associates an MSI controller with a PCI bus by defining
pcibios_add_bus() and using it to call a struct hw_pci.add_bus() method.
That method sets the struct pci_bus "msi" member. That's unwieldy and
unnecessarily couples MSI with the PCI enumeration code.
On ARM, all devices under the same PCI host bridge share an MSI controller,
so add an msi_controller pointer to the struct pci_sys_data and implement
pcibios_msi_controller() to retrieve it.
This is a step toward moving the msi_controller pointer into the generic
struct pci_host_bridge.
[bhelgaas: changelog, take pci_dev instead of pci_bus]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
According to the manuals I have, XScale auxiliary register should be
reached with opc_2 = 1 instead of crn = 1. cpu_xscale_proc_init
correctly uses c1, c0, 1 arguments, but cpu_xscale_do_suspend and
cpu_xscale_do_resume use c1, c1, 0. Correct suspend/resume functions to
also use c1, c0, 1.
The issue was primarily noticed thanks to qemu reporing "unsupported
instruction" on the pxa suspend path. Confirmed in PXA210/250 and PXA255
XScale Core manuals and in PXA270 and PXA320 Developers Guides.
Harware tested by me on tosa (pxa255). Robert confirmed on pxa270 board.
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: stable@vger.kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The ftrace assembly code doesn't need to live in entry-common.S and
be surrounded with #ifdef CONFIG_FUNCTION_TRACER. Instead, move it
to its own file and conditionally assemble it.
Tested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The generic dump_stack() code provides the facility to include the
machine name in the stack dump, which can be useful information. Add
a call to dump_stack_set_arch_desc() for the generic code to print
this information.
Tested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The "SMP: Total of %d processors activated." message which we print in
smp_cpus_done() provides no further information than the message in
genreic code in smp_announce(). Kill it.
Tested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Drop the "CPUn: Booted secondary processor" message from info to debug
level. We later print how many CPUs came online, so listing each one
is redundant, and when using hotplug, can be quite noisy.
Tested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
nwfpe's initialisation message is not a warning, it is purely
informational. Print it at the appropriate message level.
Tested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rather than open coding the printk_ratelimit() check with pr_warn(), use
pr_warn_ratelimited() instead.
Tested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Convert many (but not all) printk(KERN_* to pr_* to simplify the code.
We take the opportunity to join some printk lines together so we don't
split the message across several lines, and we also add a few levels
to some messages which were previously missing them.
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The memset function never had unwinding annotations added.
Currently, when accessing NULL pointer by memset occurs the
backtrace shown will stop at memset or some completely unrelated
function. Add unwinding annotations in hopes of getting a more
useful backtrace when accessing NULL pointer by memset, kprobe
or interrupt.
Signed-off-by: Lin Yongting <linyongting@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rather than unconditionally allocating a fresh ASID to an mm from an
older generation, attempt to re-use the old assignment where possible.
This can bring performance benefits on systems where the ASID is used to
tag things other than the TLB (e.g. branch prediction resources).
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Stephen Rothwell reports that commit 3f4c9f8f0a20 ("ARM: 8197/1:
vfp: Fix VFPv3 hwcap detection on CPUID based cpus") introduced a
variable unused warning.
arch/arm/vfp/vfpmodule.c: In function 'vfp_init':
arch/arm/vfp/vfpmodule.c:725:6: warning: unused variable 'mvfr0'
[-Wunused-variable]
u32 mvfr0;
Silence this warning by using IS_ENABLED instead of ifdefs.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The subarchitecture field in the fpsid register is 7 bits wide on
ARM CPUs using the CPUID identification scheme, spanning bits 22
to 16. The topmost bit is used to designate that the
subarchitecture designer is not ARM when it is set to 1. On
non-CPUID scheme CPUs the subarchitecture field is only 4 bits
wide and the higher bits are used to indicate no double precision
support (bit 20) and the FTSMX/FLDMX format (bits 21-22).
The VFP support code only looks at bits 19-16 to determine the
VFP version. On Qualcomm's processors (Krait and Scorpion) we
should see that we have HWCAP_VFPv3 but we don't because bit 22
is set to 1 to indicate that the subarchitecture is not
implemented by ARM and the rest of the bits are left as 0 because
this is the first subarchitecture that Qualcomm has designed.
Unfortunately we can't just widen the FPSID subarchitecture
bitmask to consider all the bits on a CPUID scheme because there
may be CPUs without the CPUID scheme that have VFP without double
precision support and then the version would be a very wrong and
large number. Instead, update the version detection logic to
consider if the CPU is using the CPUID scheme.
If the CPU is using CPUID scheme, use the MVFR registers to
determine what version of VFP is supported. We already do this
for VFPv4, so do something similar for VFPv3 and look for single
or double precision support in MVFR0. Otherwise fall back to
using FPSID to detect VFP support on non-CPUID scheme CPUs. We
know that VFPv3 is only present in CPUs that have support for the
CPUID scheme so this should be equivalent.
Tested-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Certain versions of the Krait processor don't report that they
support the fused multiply accumulate instruction via the MVFR1
register despite the fact that they actually do. Unfortunately we
use this register to identify support for VFPv4. Override the
hwcap on all Krait processors to indicate support for VFPv4 to
workaround this.
Tested-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The regulator framework has a set of helpers functions to be used when
the system is entering and leaving from suspend but these are not called
on Exynos platforms. This means that the .set_suspend_* function handlers
defined by regulator drivers are not called when the system is suspended.
Suggested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Use the MCPM layer to handle core suspend/resume on Exynos5420.
Also, restore the entry address setup code post-resume.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Adds initial PMU settings for exynos5420. This is required for
future S2R and Switching support.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch moves PMU specific definitions into a new file
as exynos-pmu.h.
This will help in reducing dependency of common.h in pmu.c.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch modifies Exynos Power Management Unit (PMU) initialization
implementation in following way:
- Added platform driver support for Exynos PMU IP.
- Added platform struct exynos_pmu_data to hold platform specific data.
- For each SoC's PMU support now we can add platform data and statically
bind PMU configuration and SoC specific initialization function.
- Separate each SoC's PMU initialization function and make it as part of
platform data.
- It also removes uses of soc_is_exynosXYZ().
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds support for Exynos4415 SoC. Exynos4415 is based on
the 32-bit RISC processor for Smartphone. Exynos4415 has Cortex A9
quad-cores and has a target speed of 1.6GHz and provides 8.5GB/s
memory bandwidth.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Commit 6e80e3d875 ("ARM: exynos_defconfig: Enable MAX77802")
enabled support for the max77802 regulators but the PMIC also
has a Real-Time-Clock (RTC) and 2-channel 32kHz clock outputs.
Enable the kernel config options to have the drivers for these
devices built-in since they are present in many Exynos boards.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
- Add DTS support for a new chip in the SOCFPGA family, the Arria 10.
- Enable watchdog node.
- Add SPI nodes.
- Add the OCRAM node.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJUbslHAAoJEBmUBAuBoyj0R0EP/2nF0rHzM7s9TivfLLnknwu5
UCPFkuB9DFsfBn6XauAjuioY2/K1yugU5Xh4IyKgXfOdUYDRxT18FzltJl8Tk25h
yx7tm5DlukQ68sdKgcSNMXgH1VNR0zV0k0P1PBjdB2W78DGpQTi5KUDb29a6wk7a
g7pYnhrzlKgLVfAazhxsD/N2o+ImxFvsVpdQBxi4/oR5zgYEoLbv6i4CKzPBrPv9
T/v4MP9E9p8tviSpuj99plMZN8w4uBQ7Clc1xCrh8y+KvKRjViFnUZPXFZHnPENs
XnqPuDyHvMxYEKQgrSDO5GQ4USUFM+TTSKGSobkCYYmaw53F+g6FxYTCDkubyCW/
v9OAH5t3lQf3P8SyHdZ2hhGH4EAoTzxC7uYJes/JdjxZgBHpfZv/bj3MGMI6r+w8
5rUF8ueipQjVOVJtr2YkkGM9U0CFw1dBGFBGk3eMrXPV418fcrIJZkRoDwdnvpQj
I8sG1rEoZHAbPOu2ejyxVAlvHF5uy7HAXpt3ktekJV70DtcNTUpREbMso7fksEzL
xufDmwe/BjUzJBFsVhZZLULUlHt1rZLYHXOn/NdfBEWluT4+uhc+1DcsCsc99Bhe
AIUMX+ngDpWZazxRGhzlOxdzi9dhuN1pFtJlXuj2wBhVNdivac4OjgBgFYWu9lpZ
cC/byWHasY2Kyyi1+tDd
=sh1R
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_updates_for_v3.19' of git://git.rocketboards.org/linux-socfpga-next into next/dt
Pull "SoCFPGA DTS updates for v3.19" from Dinh Nguyen:
- Add DTS support for a new chip in the SOCFPGA family, the Arria 10.
- Enable watchdog node.
- Add SPI nodes.
- Add the OCRAM node.
* tag 'socfpga_dts_updates_for_v3.19' of git://git.rocketboards.org/linux-socfpga-next:
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC
arm: dts: socfpga: enable watchdog for socfpga platform
arm: dts: socfpga: Add SPI nodes to SOCFPGA DT.
arm: dts: socfpga: Add OCRAM node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Add early debugging support using SCIF(A)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUboyIAAoJENfPZGlqN0++ACgQAIuqcxX1F5dayIeggtoFg4d9
dG/YrZTZDRi5AcpXLgoMvt05Q908dDexwTxqSRjjahAil3xVVksjjU57dtKeV1a1
YgsuXHn/7S3Ai97Fk+3KyOQ+SqJZpUATkjTNKpQDTYsdzHf6qSWgxOOXk1e76Ubi
DYQb3iNQUUtSrjK9KmiwQ/qdKdb+mkW7F4gprykYBsiNBxbwV8ynwFt8VOE1IjiQ
nevT28HTJMCyWjvQTLXD0kPodhD+Qx81wrer6zusZp/HEQprCap+QhaR6owGnCPX
AQXmvSl4QaA5CqA4QWPOEW38gNzOnMAu3CZUplTWmm1+kp0avNj0jms4UCa3ufwc
RkGmv/AUefbWxEE3ZDH21Cbem2vDN/Pk/cY/EcDweaAGBomPua4fH54YD3yzLoIL
omPsmx/dp6Dr3THoyGCXJbPGsVBJHqYT19PLsubMaG6FcC2KH4ootb5riX2rQzOa
ihkhaANOPgTALj13gNs1Gv0Fpl1h4Mp3O119ZTZSFz74RNS3qO4/B+/dpIBM3v+B
dJxuRsHWluRSMRRo4CTXtZP4WstABwZvEBFmGjPJSm6eP+UmBTdIsXS2C8Q22/Dy
AGKIhZBxt2wI+SzpLtgAD3i/3MzH3T3NXTMqpH8xrrP09ePwXGdOzP53q4A28OLX
1L+BZGFNaoV3TRDzbhAq
=O/9v
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc4-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Pull "Fourth Round of Renesas ARM Based SoC Updates for v3.19" from Simon Horman:
* Add early debugging support using SCIF(A)
* tag 'renesas-soc4-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Add early debugging support using SCIF(A)
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Add labels for LEDs on kzm9g-reference and koelsch
* Add Sound support to r8a7790/lager and r8a7791/koelsch
* Add IIC DMA nodes to r8a7790 and r8a7791
* Use SoC-specific IIC compatible properties on sh73a0 and r8a73a4
* Add SGX, MMP and VSP1 clocks to r8a7794
* Add USBDMAC{0,1} clocks to r8a7790 and r8a7791
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUbbZkAAoJENfPZGlqN0++A0gQAJ5bs24c0fRzIPXrkeIzY0aQ
262nBv175LG8wihixOAJB/jiTPSpaZavlR+iXYq2iU+IqkkwIzFtdNs4q/ZMdppW
J7LPUj0DwJe6+B8AYhSsSDDNW0P4avBXfU4rFXzLp2IkAqi/HdxJjB3/9C5Nzi7b
mpsTvz3x4iP2NZdEKIDGtMBwtjghsfKBRaLsgNow+JdxLDLuWKWjaR8PMxvF1LFa
Z/jz343PmFGCaWypq5HVyu+h3eNvh9HpOUleurGijXzoZl61U1SDceTygfbF+Ht2
nNq8gqynokYWfmDQa8HJlPEmeCFhDtBHc9NNPJBEOCv7pWWdsXgfEYW5OepH+xzp
FqfXM2DwKVMDcSL3LDwXYT1xZQfI8KUDg6ek5gXk8pDDpVhAb2ishEt+Vr3zEL+H
uro9wruHl8lYujq9P4Jmh9icl2fMx3hXIoq3PVkzOkmJhViwSm55pqlAAVN72d4u
xIthmwmvQ/zsvn5RwV3jmWUlwlYJmMz2gXqtsq+9NUy55yUMqjeSB9kchTzrM6SJ
CzfiCl5j2SC6jiCNGsiFjI603kdIKq0uvaLQStEAHoWJkuf+jEWmfjV9qPptE+sa
rPhIhWUXqs5Emw3DgQynIOy+szTWlg1hJl9MDF/SaeiyZ/dh/teqIoYhAjfqlCFS
7etGw24D7YujpG9jlfC4
=0cH9
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt2-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Pull "Second Round of Renesas ARM Based SoC DT Updates for v3.19" from Simon Horman:
* Add labels for LEDs on kzm9g-reference and koelsch
* Add Sound support to r8a7790/lager and r8a7791/koelsch
* Add IIC DMA nodes to r8a7790 and r8a7791
* Use SoC-specific IIC compatible properties on sh73a0 and r8a73a4
* Add SGX, MMP and VSP1 clocks to r8a7794
* Add USBDMAC{0,1} clocks to r8a7790 and r8a7791
* tag 'renesas-dt2-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (29 commits)
ARM: shmobile: r8a7791: add USBDMAC{0,1} clocks to device tree
ARM: shmobile: r8a7790: add USBDMAC{0,1} clocks to device tree
ARM: shmobile: r8a7794: Add MMP and VSP1 clocks to device tree
ARM: shmobile: r8a7794: Add SGX clock to device tree
ARM: shmobile: koelsch: add Volume Ramp usage on comment
ARM: shmobile: lager: add Volume Ramp usage on comment
ARM: shmobile: r8a7791: add DMA nodes for IIC
ARM: shmobile: r8a7790: add DMA nodes for IIC
ARM: shmobile: kzm9g-reference dts: Add labels for the LEDs
ARM: shmobile: koelsch dts: Add labels for the LEDs
ARM: shmobile: sh73a0 dtsi: Add SoC-specific IIC compatible properties
ARM: shmobile: r8a73a4 dtsi: Add SoC-specific IIC compatible properties
ARM: shmobile: koelsch: Sound DMA support via DVC on DTS
ARM: shmobile: koelsch: Sound DMA support via SRC on DTS
ARM: shmobile: koelsch: Sound DMA support via BUSIF on DTS
ARM: shmobile: koelsch: Sound DMA support on DTS
ARM: shmobile: koelsch: Sound PIO support on DTS
ARM: shmobile: koelsch: fixup I2C2 clock frequency
ARM: shmobile: lager: Sound DMA support via DVC on DTS
ARM: shmobile: lager: Sound DMA support via SRC on DTS
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Do not select RESET_CONTROLLER as it is user selectable
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUbmzlAAoJEN2kpao7fSL4Ur4P/Aoc7f8uuZk9qfdwC0UQ11sE
Lt6QG++3H4a/IhxoyE0OBgrFs3rShQDZ4Jk3Du0Tvb7D3gqDL2TB1ouDi1b9xiLP
qPatbIYHpIMRDbOAIibevqkH6iF9ZAn9gBMzBrPv1aiUjVz8WR6ubachJIa1LfEX
KSZR895d0f+c+fjFUxMCNirnmr3fS/W/Stn33Qtxm8/fmoMsTkrDEkVrWkGSPh5J
GwJrE+O1G8DNC5y1gc+kmRkX2iHfiTYchKMgnCnGC3FXTdHp3/yhkBdFD8aB2UH9
94umJ9qVZAn/V8noxba7Lk2Vg3Qrky4kLxZt14QsGUWaI8Jmz9XdqCARD9m1dkeN
Bb7X6JyQiImAbpRwlkzdaWP1jvEG4VG2SkI0p+8QSnmtef9C6Oj8M/Iunnjsvont
RCpqhRKKWEDpKOiVwFQGrLw8oRSdrMy4PEIDJD1kgeAme308VEhi+sdh3MVu82hD
xptJpHS2U9PpsAJTPBoUEy1FVHEM7THsyK7o7ICGZF7ZpWrw6YwD/imVC/5Ue+Uc
jwnJMWNLPX/wSRHMcP89ThjgivUR/LtxfV2UVrioG9biz9jVxEMxwvZS3Tnh1JkO
XL92wb3US090zFj12Di/x44Cn3GCQsRJpS3yHdCTzAf8DfzNm7Uey4+cuhB2h9dU
Rl5riS0KQ7Etxbr+4hn/
=M/Sw
-----END PGP SIGNATURE-----
Merge tag 'berlin-soc-3.19-2' of git://git.infradead.org/users/hesselba/linux-berlin into next/soc
Pull "Berlin SoC changes for v3.19 (round 2)" from Sebastian Hesselbarth:
- Do not select RESET_CONTROLLER as it is user selectable
* tag 'berlin-soc-3.19-2' of git://git.infradead.org/users/hesselba/linux-berlin:
ARM: berlin: do not select RESET_CONTROLLER
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- AHCI and SATA PHY nodes for BG2
- USB and USB PHZ nodes for BG2/BG2CD/BG2Q
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUbm0pAAoJEN2kpao7fSL4RW8P/A+0U0qoj8FbBpDwiwhjADwG
4327uzYbI+TG1fajJYxbDlMzvDNjRXb2yRb/eivgEoY7LsLR7Vbi1mwKsNAqH6+6
n1RRtil1Rir4nILN2gnN911O24owGkvOUV4CN14uzDLR6K/smoaSYFcfFH6FS6Os
NaYccrpobWCb4tZKjWPxo8FuknmTD+siUQmZRtazToWd9xiir7RhKwSrX8i/1jNp
6vuhtn4L2nTZhycFjl1RZI6sZBOKtVBRD6yiuUSc6YjUPo+UEpaZdYQwcjOu906R
c/99RgPa1ThN4OGYnGdco4grnSYU5hta0/xvVgaWXVDXie2Gg/gE3TCKzM6iWT2b
EIWL8sCAOvHs8qTyknRukSGREPaTlcxMt+nogz6iD60+Dv//AJziJSqGnzGPDPSO
Ud4hshdScwSGRZHfa0GRk3b2Y6P5F+gf2YuJuMcuWqz6kN5bbnQl3YvNYCiypvNH
PWalrCaV8xS5UqN2JsRinJioUnVcGRBikfY/09xTLcweizZdXyoXjVvsNf7i5tPu
XgyuXZob7uHwjJn6rQ2YsVeDQW/WPZ+df+da5Atq3xAnhAEuIgY74SPrRugdzdJQ
r59v6YdSauMJdh5xJ1pNsaWDMJ7mGkv2E8txXOazWVWErfaI57lRwepXz99UgXBa
RIUUPggoO/lrecw5c5mb
=ZS1m
-----END PGP SIGNATURE-----
Merge tag 'berlin-dt-3.19-2' of git://git.infradead.org/users/hesselba/linux-berlin into next/dt
Pull "Berlin DT changes for v3.19 (round 2)" from Sebastian Hesselbarth:
- AHCI and SATA PHY nodes for BG2
- USB and USB PHZ nodes for BG2/BG2CD/BG2Q
* tag 'berlin-dt-3.19-2' of git://git.infradead.org/users/hesselba/linux-berlin:
ARM: dts: berlin: enable USB on the Google Chromecast
ARM: dts: berlin: add BG2CD nodes for USB support
ARM: dts: Berlin: enable USB on the BG2Q DMP
ARM: dts: berlin: add BG2Q nodes for USB support
ARM: berlin: Enable SATA on Sony NSZ-GS7
ARM: berlin: Add AHCI and SATA PHY nodes to BG2
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This device actually has a 8250 serial with a shift of 0.
Tested this on a BCM4708.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The recently introduced resume hook in the edma driver
is not referenced when CONFIG_PM_SLEEP is not set, which
results in a compile warning in keystone builds.
This adds an appropriate #ifdef.
Cc: Nishanth Menon <nm@ti.com>
Cc: Daniel Mack <zonque@gmail.com>
Cc: Joel Fernandes <joelf@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Fixes: a2b1175131: ("ARM: common: edma: add suspend resume hook")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Remove legacy support for at91sam9261/at91sam9g10 boards.
This include board files removal plus all legacy code for non DT boards
support.
Use the Device Tree for running this board with newer kernels.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This patch was generated by running 'make tegra_defconfig' followed by
'make savedefconfig' with the v3.18-rc1 tag checked out. Two values go
away: CONFIG_SCSI is selected by CONFIG_ATA and CONFIG_SCSI_MULTI_LUN
was removed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10
SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there
are enough differences to warrant a new base dtsi.
The differences are:
* 3 EMAC controllers
* 5 I2C controllers
* 3 SPI controllers
* 1.5 GHZ dual A9s
* Support for DDR4
Besides the usual memory map and IRQ changes, the clock framework will be
different, so this patch just adds the fixed-clocks.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
We still need to support platform data for omap3 until it's booting
in device tree only mode. So let's add platform_data/omap-gpmc.h for
that, and a minimal linux/omap-gpmc.h for the save and restore used
by the PM code.
Let's also keep a minimal mach-omap2/gpmc.h still around to avoid
churn on the board-*.c files. Once omap3 boots in device tree only
mode, we can drop mach-omap2/gpmc.h and we can make the data
structures in platform_data/omap-gpmc.h private to the GPMC driver.
Note that we can now also remove gpmc-nand.h and gpmc-onenand.h.
Cc: Arnd Bergmann <arnd@arndb.de>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
be incomplete and broken, and the 3430sdp is only used in few automated
boot test systems AFAIK and those have been booting in device tree only
mode for quite some time now.
Note that this branch has a dependency to the related device tree
changes and GPMC changes sent in a separate pull request.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUY5y3AAoJEBvUPslcq6Vz8ooP/0aqtqBGZpAR5oI+WUrvA8OH
5Z9S0r23eMr7MPtvur/i9JEAPg8svU2QZcJkI2Ap7sTECCYwccZuoK3KPSDNDBHz
oTje63iYl+3ZQwzIsbCS69AEMms7+J+kvP4DcUMLN7Xgy4xh1wjujY4p2q2ayu+b
MTQuCHF3LAoM/VZuqSI9pghu8W66eGnRoYWY2054+JR9YjG8SF7gqMkuw+iWwVZ8
8vupI/phiAKaJ6eF/NvjYh3gNWHjxnqnLym8+JUJd/M/t1irge9Qa9ppNGmdgqrN
lh26KyXypYwZRAxwPCRN0gq8hVZPOvwEKUN/x4kcLoK3TI1YESj0NtCDjTKknBTN
y69pZRmm4kFl2m+52yoMqYGaajZ7NlVuWMHA+2TKLDe1Y0w92PLlB8InXKmrqqkV
fXjBMBXgLy6kYkqvP+qVeIa+7UVrpvS/loyuTu4VfYwvajIYy7JMs57ryhm0A2H+
XXZ4owl98hTVAVXZ8hh3YDc1pIFlgI4GEb2N+r2vHUgifohhO+4OiG2evwUwVBZi
Fc+ySkWH0WuPnR0rGQvoAbUcmSKE2ir7HH+Q4gKQvGISl3EuUnqsbFrtqY9kS3iI
/xAz3UFCZ/3oe6EeyasvuGt3l9vHyzC1j2W4M57WxmFFrwqxm44A6km+UQfvmaCP
g2tVua3TNdoTtoh+Zhox
=yb48
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.19/cleanup-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/omap-gpmc
Pull "omap clean-up for v3.19" from Tony Lindgren:
Drop few unused omap board files. The support for ti81xx is known to
be incomplete and broken, and the 3430sdp is only used in few automated
boot test systems AFAIK and those have been booting in device tree only
mode for quite some time now.
Note that this branch has a dependency to the related device tree
changes and GPMC changes sent in a separate pull request.
* tag 'omap-for-v3.19/cleanup-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Drop board file for 3430sdp
ARM: OMAP2+: Drop board file for ti8168evm
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
changes allow us to drop dependencies to bootloader timings now
that the known device tree entries have been fixed. So we can now
require proper timings to be configured and get rid of the legacy
smsc91x code.
Note that this branch has a dependency to the related device tree
branch sent in a separate pull request as timings are now required.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUY5toAAoJEBvUPslcq6VzHAwQALbDoi++oqPFfgd9iHZngsFo
wxAsb1n4ENaazBJtG2SayDDUo7h3zxKrh/NRqEO43g7oW1V6nD86a5ItM7HlnzH6
upjHAb8O3du3SL8Zmu+AMgcoqB2yz8iZjphPW2r25gnt6on9uFQio5AVMturEpO0
PVyWdpT0sTvLa1JZRjhmn/2cLC1z7eFdG4yjQQdwbrR5WDUX3IQz3X6n7dTM5IJy
oH+gM2k9x8ymR7rfFDjBEuZl+0ShHJLfg30ubAGai+MfyLtSBSdKIIpiNdVEbbCe
ytMVhTD4pS+5ToVNZ8m5rGtZjY+g0VN57wM8AfKTN7OF6L0nb8ZeOoz0dEJkXQcw
IlZ0MP1/k/HhOyQ8FRWcSqvG/frvQjQSHNTaoJAWNvjpHtxQ4Lox1r5mnmy3PICv
2SxDYEysohwBrv/TQJlTMDJn+ndAvygbGxDbMYMbpqwmC1jsL5PA4vMnpMVDrBWo
h7V2dHd/uw9uFB+FnSKvOJYMYs2vdsArlxYrk8br0RHt7syugWiVfKDjPvBhOum2
y24Q6bRXUZqloiq2hG4VNN+vhmB6TNdnAXV15kzp+pzmsNh3gsNRTMytQvi0el51
ztYBDvugwrN9WtNryKEaqV4bQrlFiWsxremVfcm8FiynGd8HqRUjf271lGXblsJe
IfcIIVJwnpn0Cd/8SWZp
=CA9d
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.19/gpmc-timings' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/omap-gpmc
Pull "omap gpmc changes for v3.19" from Tony Lindgren:
GPMC (General Purpose Memory Controller) changes for omaps. These
changes allow us to drop dependencies to bootloader timings now
that the known device tree entries have been fixed. So we can now
require proper timings to be configured and get rid of the legacy
smsc91x code.
Note that this branch has a dependency to the related device tree
branch sent in a separate pull request as timings are now required.
* tag 'omap-for-v3.19/gpmc-timings' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Remove unnecesary include in GPMC driver
ARM: OMAP2+: Drop legacy code for gpmc-smc91x.c
ARM: OMAP2+: Require proper GPMC timings for devices
ARM: OMAP2+: Show bootloader GPMC timings to allow configuring the .dts file
ARM: OMAP2+: Fix support for multiple devices on a GPMC chip select
ARM: OMAP2+: gpmc: Sanity check GPMC fck on probe
ARM: OMAP2+: gpmc: Keep Chip Select disabled while configuring it
ARM: OMAP2+: gpmc: Always enable A26-A11 for non NAND devices
ARM: OMAP2+: gpmc: Error out if timings fail in gpmc_probe_generic_child()
ARM: OMAP2+: gpmc: Print error message in set_gpmc_timing_reg()
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- rate init for rk3288 clocks
- enablement of various peripherals
- new boardfile for Haoyu Marsboard (rk3066 based)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCAAGBQJUa1KSAAoJEPOmecmc0R2BuUsIAKC74yQhApYDPib1o8PrtW4I
f8N41vfF+zrxUHYOAIZUMCjNuaBBagnvlXe6EmGZ9crQhThMytEKUP4rG2pkScw5
+MKF2aw4sKUHPDDZ0n9VMVMW0i0HfkVlhB921cDfhKVcBpGE44YNusC5+1wsa+8r
USGDl0EVTSMyAjXD/ogSqberQBBfFc4eqS0H+ZkCmA/saKa+tLpH0heqY/prq3FU
mryXryGIUkCSwN7CB/lt45jT6qfb1UdNOgahK24lt2EmH9R/0IIrqzI8dOf6mnSA
lBKnLPazbes0jny2iJSVfNQmlgWodpPY3kNEwxho4LrYhu+sTzW2oKMZrAXTxqY=
=j7JA
-----END PGP SIGNATURE-----
Merge tag 'v3.19-rockchip-dts2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Pull "ARM: rockchip: second batch of dts related changes" from Heiko Stuebner:
- the dts part of the rk3288 smp support
- rate init for rk3288 clocks
- enablement of various peripherals
- new boardfile for Haoyu Marsboard (rk3066 based)
* tag 'v3.19-rockchip-dts2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: enable PWM on Radxa Rock
ARM: dts: rockchip: fix invalid unit-address in rk3188.dtsi
ARM: dts: rk3288: add VOP iommu nodes
ARM: dts: rockchip: add reset for CPU nodes
ARM: dts: rockchip: add intmem node for rk3288 smp support
ARM: dts: rockchip: add pmu references to cpus nodes
ARM: dts: rockchip: add serial aliases for rk3066 and rk3188
ARM: dts: rockchip: Add devicetree source for MarsBoard RK3066
ARM: dts: rockchip: Add EMAC Rockchip for RK3066 SoCs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
A lot of things happened during that merge window, but mostly:
- Preliminary Support for the A80
- New Boards Support
+ Mele M3
+ Banana Pi
+ Optimus
+ OLinuXino Lime2
- Device Tree Relicensing to GPLv2/X11 dual license
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUa8GwAAoJEBx+YmzsjxAgswkP/Rf1EwwEbQYnIDJaSbK6/okS
DYo9Sv2b3drI6sOR5TduYY7tH9DchCootb5YtLSboZTieEOrmM2VHwV/ZRMcKRXD
OglmS6EcSkXTCs05X2dPtvnRxNQxzebmD64V1AmQylIuOBQQL2mW2FqHYH5JtGQ8
UXj1RNAOwBuCWFwxsiUt92seQZOVMsHjeEyTDuCBFw0QbVpDdaJ5OBrNxDY2nrKp
XzbMUvVBoPQXk65KBXvxL6l5yGKEyRxXXYNEtf6tb7bj8tfSst9fqVQgK6/V073+
oJn+Fr4qHSr7PmRkWkVKjS7UIZdkip2SKrdkZPJeowGRLKFDGafCsc95FCKbo9B4
RbBS6adETilkSpkVUh2amg6F+o1DnzNleeeEDrGEoDfumaLU567vN/VWeQralgwC
9uDYfy7f3MHBt7mp8aMnE4N6cOY99yHILSv2AI7ndzo1iXR+l2tYcRgj9P6eXkxq
/ytSCN477IMdFzwStHngzqyYAtfKsjJoGH1dComqEjDvorSNWDFY7odW43hEWzZF
cW/vAs6Jitofn70PbpSTNJrjzGAJbEqAv9llBMubSkcq8Uxfk6ZF53ahbAEPh177
Xqtd2QLyB+oOPbF/pbqkM19an/XDa9ZmZAQEBX3c38KTp5GfdpZV9CroClWwNXDH
kJg8WRAtjWIjd8n/THBA
=dKZr
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt
Pull "Allwinner Device Tree Changes for 3.19" from Maxime Ripard:
A lot of things happened during that merge window, but mostly:
- Preliminary Support for the A80
- New Boards Support
+ Mele M3
+ Banana Pi
+ Optimus
+ OLinuXino Lime2
- Device Tree Relicensing to GPLv2/X11 dual license
* tag 'sunxi-dt-for-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (52 commits)
ARM: dts: sun6i: Add ethernet support to M9 board
ARM: sun6i: DT: Add PLL6 multiple outputs
ARM: dts: sun6i: Add support for the status led
ARM: dts: sun6i: Add EHCI support for the M9 board
ARM: dts: sunxi: Add regulator-boot-on property to ahci-5v regulator
ARM: dts: sun7i: Cubietruck: add power supply regulator for USB OTG VBUS
ARM: dts: sun7i: Cubietruck: override regulator pin
ARM: sun7i: dtsi: add support for usbphy0
ARM: dtsi: sunxi: add common VBUS regulator
ARM: dts: sunxi: Banana Pi: increase startup-delay for the GMAC PHY regulator
ARM: dts: sunxi: Use sun4i-a10-apb1-clk for sun6i/sun8i apb2 clocks.
ARM: dts: sunxi: unify APB1 clock
ARM: dts: sun6i: Re-parent ahb1_mux to pll6 as required by dma controller
ARM: sun5i: olinuxino: Relicense the device tree under GPLv2/X11
ARM: sun4i: cubieboard: Relicense the device tree under GPLv2/X11
ARM: sun7i: pcduino3: Relicense the device tree under GPLv2/X11
ARM: sun4i: pcduino: Relicense the device tree under GPLv2/X11
ARM: sun7i: olinuxino lime: Relicense the device tree under GPLv2/X11
ARM: dts: sun9i: Enable uart4 for A80 Optimus board
ARM: dts: sun9i: Add uart4 pinmux setting for A80 SoC
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Pull "ARM: meson: DTS related changes" from Carlo Caione:
here is the pull request for the DT related changes for the 3.19.
It's mainly the work done by Beniamino for the preliminary support of
the Amlogic Meson8 SoC, the support for L2 cache and the I2C
controller.
Please note that the support for the Tronsmart S89 Elite TV box has not
been included since the Meson8 development will be done now on a
different dev board kindly provided by Amlogic.
* tag 'v3.19-meson-dts' of https://github.com/carlocaione/linux-meson:
ARM: dts: meson: add I2C controller nodes
ARM: meson: DTS: enable L2 cache
ARM: dts: add dtsi for Amlogic Meson8 SoCs
DTS: meson: Add forgotten compatible in board DTS
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This has mostly been about introducing A80 support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUa8NAAAoJEBx+YmzsjxAgNZ0P/22p1VKumZyoNRKF3vHn+iNV
MBDa7UgVWXXQvBuysPs4n0MmG4sF/jKuD9IzVp6AI6U0M4HFqYwNJJl5ScT0+9ho
jXgdZ/CfDGmbkQGHLYeDbj+ShuZFtpkcpf0373qh3EaJyoJaOTaYRlbkpVp/GSfb
M97Q/cqYw+rOqs/YrSJOQgKAAePl6Avi6hOVJ/cRATBvsdm80fcQ0SbuhTVWlH9j
5UXtLMDDbsCHnXCV05OkzkgQyJhNIhWuK8rURMTFG1HY5kkMQKSg1V8HSdjMoQp4
dx+HP8J5j3deshCOcRGxO4aCo3CPp8GYR2c5jPXYCTTnjrhCOiHI25GAcmOhuXXI
Tpixwo08pqTzTrevI8q6heAwBk2c3JA5INKswHOuRd988oD7vSfJpEYmyN+H6v1S
wjzNDdsPecH+1hVZhp5iQ0NzDX7K/9N8gt24A/shin2cnCHgkVoU1/MFq/S3ZLQk
qtibbcvdgBXAiX5BWlqPi2pWUdQ6LWXh3+UvLu6uEIvg5lrhoPsOilbuUbgQ7fdR
B6OOwWur9MoV/Y/C8aquubU9Dwj8nrmYJ5lzNvkffD6zFAx7Pg803WewaNowAoGG
e9MU6gAAn4/Km8Oig+dIkptnYHW+nPoodPNyoAMaJ9Ce+3YzpxclPVjEAzyzkZFh
+1geJcIUj9hYSJeKT0gu
=cJ5x
-----END PGP SIGNATURE-----
Merge tag 'sunxi-core-for-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/soc
Pull "Allwinner Core Additions for 3.19" from Maxime Ripard:
This has mostly been about introducing A80 support
* tag 'sunxi-core-for-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: sunxi: make sun6i SMP ops static
ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER and RESET_CONTROLLER for sun9i
Documentation: sunxi: Add A80 datasheet link
devicetree: bindings: Document supported Allwinner sunxi SoCs
ARM: sunxi: Introduce Allwinner A80 support
devicetree: bindings: Add vendor prefix for Merrii Technology Co., Ltd.
ARM: sunxi: Add debug uart used by sun9i (Allwinner A80)
Documentation: sunxi: Update Allwinner SoC documentation (A31/A31s/A23)
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Pull "ARM: meson: SOC related changes" from Carlo Caione:
This is the pull request for the SoC related changes for the 3.19.
The support for Meson8 is added together with L2 cache management.
* tag 'v3.19-meson-soc' of https://github.com/carlocaione/linux-meson:
clocksource: meson6: Select CLKSRC_MMIO
ARM: meson: enable L2 cache
ARM: meson: document meson8 compatible properties
ARM: meson: add meson8 support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCAAGBQJUa1NRAAoJEPOmecmc0R2BhycH/RSVMLZ8o5AWEwXEhDaf0Y/8
YnH0uW1wZazAsDtkOHvxBwIHX16E7tNoODZ5eT/OqMK55SSWuxaayOOx7uRx44va
qf3pV8S/Wh+gjUIwhAkvLd9kgoVHuJRS++WzG9YrcT89qUaLcmekXKukxA32eKwM
xjwZJsyYWVseL3UupTY+lMT4dtuaIfaxN6m2WtMWViKwQR8zHNC6fwySQbqGBwAe
X5eoWA6Tv0c1NXrHghjxL1uVj4htqPZhgRUne5BTgGay2D7uJFxNWvQ92ppK5DdD
4c6sH1y2/IXSZYnrCEYg0ARRyhZreZtVWW5ZvPTWHBr6WXOZe33fw6+MvO5hPGk=
=KyXS
-----END PGP SIGNATURE-----
Merge tag 'v3.19-rockchip-soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/soc
Pull "code part of the rk3288 smp support" from Heiko Stübner:
here is the second batch of soc related changes, consisting only
of the smp support for rk3288.
Due to the slight misheap of the v3.18 cpuclk pull being merge, it is based
on exactly this merge commit from Olof to next/soc.
* tag 'v3.19-rockchip-soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: rockchip: add basic smp support for rk3288
ARM: rockchip: add option to access the pmu via a phandle in smp_operations
ARM: rockchip: convert to regmap and use pmu syscon if available
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
top of the multiplatform patches, this moves out
some drivers and reduced the amount of code carried
in arch/arm/mach-integrator.
- Move the Integrator/AP timer to drivers/clocksource
- Move the restart functionality to the device tree,
patches to enable restart for the Integrator have
been merged to the reset tree (orthogonal)
- Move debug LEDs to device tree (using the syscon
LED driver merged for v3.18)
- Move core module LEDs to device tree (using the
syscon LED driver merged for v3.18)
- Move the SoC driver (chip ID etc) to
drivers/soc/versatile/soc-integrator.c
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUavcgAAoJEEEQszewGV1zxHgP/3i1LxdQ+B1ztOpZRZ+Bi4iQ
5KU9j93eMMTlZ3nASvRBIx4MgnUVItuUQ5idnmATCDfoP2lhj/JWPw7G5vyEvRoj
2yuTB9IoutGoTPm58UeglPPedwcv2Lc9p7Boz/cnZVc4KfLldU66yoIV+s1vlijN
OAhgOyShIjLUv5ikwNPRAjEXw7fJZc6ixhTt/EJrPbiMhjkXMKJs/SXovzhOw25a
UVmMu36rwnVyQllfoS4yd+wpHa+Jg6ZhxH3nIveQpEVt8MOukOPiYa5ePmglXpkF
B0u0vaACrZfiPCeQL3RD4LN8Z9QLR9Mt1VDbFkWnTRTKdNA034dhIoD0ZxsoGepb
cV9QfA1n1Q6hKUqg59PfZv4MKwPXA1TmF5J3ZBNL1xK+bsRBHZmBq1dKg4rww1bu
tyxJfg3LmUCQe5PkcT7HZJFv1yXnEXduXUX0TYclPhp+GnAyudwNkw4/7mmz2gPT
XEhd64xjB+yVyzN8zu34KIrsDvv/Z7CyKzYAsaR+yY4DbUuh2p2sNupCnci4Hs/k
PO09w76mxRulFBVw5ZuLBzevPpa3hasny05bqnku6/VTp1RfOM+5i60B/gGnIWFo
KLxaDcvbyuP+nAdQIl+/X8Zv0tQ0KAqlZFvgroxCeUtF5JwXlbdYbbVEO0FVmMB/
TjfE+8xCchI2cZPci9J2
=rplU
-----END PGP SIGNATURE-----
Merge tag 'integrator-v3.19-arm-soc-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/soc
Pull "ARM SoC Integrator updates for v3.19" from Linus Walleij:
Integrator updates for the v3.19 merge cycle on
top of the multiplatform patches, this moves out
some drivers and reduced the amount of code carried
in arch/arm/mach-integrator.
- Move the Integrator/AP timer to drivers/clocksource
- Move the restart functionality to the device tree,
patches to enable restart for the Integrator have
been merged to the reset tree (orthogonal)
- Move debug LEDs to device tree (using the syscon
LED driver merged for v3.18)
- Move core module LEDs to device tree (using the
syscon LED driver merged for v3.18)
- Move the SoC driver (chip ID etc) to
drivers/soc/versatile/soc-integrator.c
* tag 'integrator-v3.19-arm-soc-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
soc: move SoC driver for the ARM Integrator
ARM: integrator: move core module LED to device tree
ARM: integrator: move debug LEDs to syscon LED driver
ARM: integrator: move restart to the device tree
ARM: integrator: move AP timer to clocksource
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Use WFI when putting CPU1 to sleep. Don't hold CPU1 in reset
since that results in increased power consumption.
Reset CPU1 briefly during CPU1 bootup.
This has been tested for hotplug and suspend/resume and results
in no increased power consumption.
Signed-off-by: Alan Tull <atull@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees Celsius.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones corresponding
to the four thermal sensors provided by soctherm.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Add a DT node for the TRNG (True Random Number Generator) block.
Keep this block enabled as it does not depend on any external connection,
and thus should be available on all boards.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
all other nodes in bcm63138.dtsi use "interrupts", this had to be just a typo
which never got noticed, even it may have quite some consequences.
Signed-off-by: Radek Dostal <radek.dostal@streamunlimited.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
This resolves some of the obvious conflicts between the at91 cleanup and
drivers branches.
Conflicts:
arch/arm/mach-at91/at91sam9g45.c
arch/arm/mach-at91/at91sam9rl.c
drivers/rtc/Kconfig
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
support in perf. The main change enabling this is moving the CCI PMU
driver away from the arm-pmu abstraction, allowing the arch code to
focus specifically on support for CPU PMUs.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCgAGBQJUZeYuAAoJELescNyEwWM0u7QH/1AOiUjffkY3kKFyI4STU2Dw
EO/ReouiSfmGpB5VHFwndGweQJPrw1ihViropEZyRo7tlHFJVFxTS8a2HxF+Pv6y
JcvGVMrCKvsk1slsuq0hHpOs3SFj6b0EX+fg4iggUo5oNrgSo/qgNeQtNOnUpR7v
ZAcMm/N6dKS6ZVwpzmayT0MCwg1HLr8iFuHXWOnwZIQ8WhXSlF6CUOIoRDO/63Ta
Dsz/NX6vAGnY1tInKRV/gTcuTihku0qbkLTCMKnd9+jZhZrOIHOtV5XqGvRrlq+t
66oJgsUFtG2FbkmAwnm+sep8Frztj2NLqKIxnKI+72AthrSvmGiPXh8kyUrQRGQ=
=gOqc
-----END PGP SIGNATURE-----
Merge tag 'arm-perf-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into next/drivers
Pull "ARM: perf: updates for 3.19" from Will Deacon:
This patch series takes us slightly further on the road to big.LITTLE
support in perf. The main change enabling this is moving the CCI PMU
driver away from the arm-pmu abstraction, allowing the arch code to
focus specifically on support for CPU PMUs.
* tag 'arm-perf-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux:
arm: perf: fold hotplug notifier into arm_pmu
arm: perf: dynamically allocate cpu hardware data
arm: perf: fold percpu_pmu into pmu_hw_events
arm: perf: kill get_hw_events()
arm: perf: limit size of accounting data
arm: perf: use IDR types for CPU PMUs
arm: perf: make PMU probing data-driven
arm: perf: add missing pr_info newlines
arm: perf: factor out callchain code
ARM: perf: use pr_* instead of printk
ARM: perf: remove useless return and check of idx in counter handling
bus: cci: move away from arm_pmu framework
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUZiEOAAoJELQ5Ylss8dNDmWgP/iPeoLk6Oh1aANsStfoKOACu
YtHN09nOXAGN60HtjwR6FFYu7R1knMiybTykZhcLR3sLmIYfoTOpRb7Wp2ocXUKm
3c8wPZ1sNDBVWUd2ooeD3/Q9n55gLchupMSs28LH9FtkgTbhK1HeS7DqspWocpZe
d4KKYfYfKStJlUE4sK0vYD6quL86H5pWgq9i3yYFcV6DuAyAdsYkyT5tNIGOC7BK
ND8WuR2tkdDhrsR+5wE0DHJCYP3bXKpBlyzrSuxEAcMJE5VwZc9ynrJyShjCou7W
ABQCSIIZjYYKCBXohxHSD1qhcf6HubJUvWQavUcdmfsQXnzUz5xd1D7v6SzeeZSL
mS5AVnY393yOhl/LjF5d18mXM7M8wCuRngm0F1IA9mS999SKJAHCa4/lCG4tN6IN
4azIp4bow6clVjU5HmGA6jmWkkwDeVRtRI9ugqMjbCs2+C77Bgb7y1PVkn6vHOug
lSJ2CnfvN0xW+hwBrOWIMmXJNXBdghP40Nhlcfll/d5OGI2ly0z5K7mX3gyRKtzC
vf9ueFFBjGMyHAS8MFK7jXnCTTqtdgQpxrDJmCAdL4ARi+RI2U0WB/kr5q+OXq4D
t1KLtX+1agb2+YvFR8cExWGPcYoY8KYjx0o6I6hwgkzFrNxxfRKIqmUJGGGMms3r
CdjV5Mt0QNx68sjxAV0Q
=KhoS
-----END PGP SIGNATURE-----
Merge tag 'v3.19-next-soc' of https://github.com/mbgg/linux-mediatek into next/soc
Pull "Add earlyprintk to mt8127 and mt8135 and update Kconfig entry for
Mediatek SoCs" from Matthias Brugger:
Here comes the pull request which add earlyprintk support for mt8127 and mt8135.
Apart from that the Kconfig entry for the Mediatek architecture was fixed.
* tag 'v3.19-next-soc' of https://github.com/mbgg/linux-mediatek:
ARM: mediatek: Fix description for mediatek SoCs
ARM: mediatek: Add earlyprintk support for mt8127 & mt8135
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUZiGhAAoJELQ5Ylss8dNDs6oQAIVbGnJA4j2ajIGQmUuTVCdy
8S+QfAogEem3ZSpeG/Ku8UgV6QCbfF/gg/++hoXn5XyR8pl8Mk6lh+3mfpiJr/Bt
zVPmqxaS4cRbDToBpMah05YMBwDoG3C/zArGglKJDMQV+TIzid/fDcyAH4Z6LqpL
vS+kAm8ovTiCLIFLgXeimhxldPhP4xcVE+i0t2hfGzyTglmJJvn1YwCpMgkfBazM
D9xkZIcoI0YgNkqFfiCfVRPxm6Tb95kYtUn6XwwQwJUx5pKW/uwSx54tf9sV2myQ
0UsuMGtBb2CIraPsAvY67ndC3lcA1f/RpaA2cjJyaDg+EYNr44nLbu14v4+xqoo6
Ud6iXjrzqa/pfACdRmUaWhReCFdmrHceuVd4hYPBvMRsCSNVjLnDVLr1LwVqpPv0
Nsxtzjw2s3+M43mBZfrva8lJVas/OgxGEk1JlufXFirfZBEyPiSGy7gxtQ/lm+kM
aSpCsreIOcTjkN2MXNea3BWOLo/vHzoMEvQeqo2EwYqTjNqYMS5mdMvIvEJcxUVa
uLWTf6SjcEeEVKamZ9Y3m6uIOgZv2KiQzeibaxccDCZG4DH2QR6IJvzQYEgI1Ui2
MXxrLY0SFp4G1UKv/nXalMDwI/HreGQGCCenlWyABv6/7/qiLX27CkVU8I5WOuod
31+J0spYkykFJ9vee9qC
=DrlM
-----END PGP SIGNATURE-----
Merge tag 'v3.19-next-dts' of https://github.com/mbgg/linux-mediatek into next/dt
Pull "Add support for mt6592, mt8127 and mt8135 Socs from Mediatek"
from Matthias Brugger:
Here comes the pull request which introduces basic support for
Mediatek SoCs mt6592, mt8127 and mt8135.
The patches for the mt81xx got merged in the late tree for v3.18 but
were not be merged at the end. They got a small fix regarding the
compatible and model string in the dts files.
* tag 'v3.19-next-dts' of https://github.com/mbgg/linux-mediatek:
dt-bindings: add documentation for Mediatek SoC
ARM: mediatek: add dts for mt6592-evb
ARM: mediatek: Add basic support for mt6592
dt-bindings: add more chips in documentation for Mediatek SoC
ARM: dts: Build dtb for mt8127 & mt8135
ARM: mediatek: add dts for MT8135 evaluation board.
ARM: mediatek: Add basic support for mt8135
ARM: mediatek: add dts for 8127 Moose board
ARM: mediatek: Add basic support for mt8127
Signed-off-by; Arnd Bergmann <arnd@arndb.de>
It is only about a not so recent driver for old platforms: RTT as RTC driver:
- RTT as RTC driver enhancements and machine specific include files removal
- RTT as RTC driver conversion to device tree
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJUZg/EAAoJEAf03oE53VmQ/KAIAJi5Ky2ekaZ4FGWbDrnQBHV+
X0M/wvCdHw4D7VENo1W3U3ulf5r0XimeY6nnbmx3Ki0fTE2O3VyfLNzkjQtMf6iX
TfoJM9y4fWsY5AXnynYO1Gj/2CH6Xab79Kb5sxL8b9VvlUMxlsKoQOmUYHC775OX
YiBfp3dZYODkMyIIQmSkoZGj+kkgWbjMrp9CPueqVltha/EbfBP96Kib2G/aJVkb
F9QyOq8B/mpUk2P29L1hc9X0/tjwaLZsO97zzhYVj7VwZS9sbYztQgmUNdtEds4/
7EhMwSXxb9L5LkuoyuHFpRLMGzLrN9XBftE58s92hXwnM2KZE4eNo/JF0SGDOKo=
=POJG
-----END PGP SIGNATURE-----
Merge tag 'at91-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/drivers
Pull "First batch of drivers for 3.19" from Nicolas Ferre:
It is only about a not so recent driver for old platforms: RTT as RTC driver:
- RTT as RTC driver enhancements and machine specific include files removal
- RTT as RTC driver conversion to device tree
* tag 'at91-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
rtc: at91sam9: add DT bindings documentation
rtc: at91sam9: use clk API instead of relying on AT91_SLOW_CLOCK
ARM: at91: add clk_lookup entry for RTT devices
rtc: at91sam9: rework the Kconfig description
rtc: at91sam9: make use of syscon/regmap to access GPBR registers
rtc: at91sam9: add DT support
rtc: at91sam9: replace devm_ioremap by devm_ioremap_resource
rtc: at91sam9: use standard readl/writel functions instead of raw versions
rtc: at91sam9: remove references to mach specific headers
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- some trivial fixes: macro for IRQ, license wording
- DMA description for sama5d4
- RTT as RTC driver definition plus associated GPBR for several SoCs
- addition of missing nodes: rtc for at91sam9rl, isi for at91sam9g45
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJUbMTeAAoJEAf03oE53VmQnG0H/1EDeVYZhOaFkCyLjNsrQhLt
w080xpUDwRRKYbUP/RJvRp7BcArwe650xncaWjh7tLrA3BZQ5WAMeNggFjUofykr
uNzE2ZuIfeW08g7OEo7tFuZxKsejW14e0ezyR64hClFON1S2+kHtOkBe8Vxd0VPc
LG3W2UoPLK6rzzYKO6vRzm8k0Ah27dhbDhhN+Z52DstQ+bx0fWEF0Y9bTx/pszlJ
YGuDnGBruyIkAxtZYbqQ8UXH3uB8FeT9VOPYG8ADIdQgEPchOoHxy56yKVXa7tKo
PP/HUE2fZ4tNv6eSVi/P5ZVCD+ycoevwfOGk+NJKwzoIwMMVfdYAlrnorWfplsk=
=3QgK
-----END PGP SIGNATURE-----
Merge tag 'at91-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/dt2
Pull "Second DT batch for 3.19" from Nicolas Ferre:
- some trivial fixes: macro for IRQ, license wording
- DMA description for sama5d4
- RTT as RTC driver definition plus associated GPBR for several SoCs
- addition of missing nodes: rtc for at91sam9rl, isi for at91sam9g45
* tag 'at91-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
ARM: at91/dt: at91sam9g45: add ISI node
ARM: at91/dt: enable the RTT block on the at91sam9m10g45ek board
ARM: at91/dt: enable the RTT block on the sam9g20ek board
ARM: at91/dt: add GPBR nodes
ARM: at91/dt: add RTT nodes to at91 dtsis
ARM: at91/dt: at91sam9rl: add rtc
ARM: at91: fix GPLv2 wording
ARM: at91/dt: sama5d4: add DMA support
ARM: at91/dt: sama5d4: use macro instead of numeric value
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- fixes following legacy board removal
- removal of an unused config option CONFIG_MACH_SAMA5_DT
- move of some header files out of include/mach directory
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJUZOvPAAoJEAf03oE53VmQlLMH/Aq/q9FYWyiZqq+DHccUuMvt
IJG2LjTabKb7ihHbsrwaF6kqddISeF4vrBgIoNhNxqfD836MuG5vBpGR1iTXyfqF
q/s/CI6Zmw3KWxCTUJSE8ix8Y6KA5vdI84D4dLorjlYhmFj0xXrteSooMlJ0t9uJ
d8o5gOhaL0nQnhdJ950MsSVopsFzjJ0nzxr0PqsVGx6/DJRB+CyKi9e7419B+Vie
phULLFux3Ai4m7eOHmFxc8vBFwQwSPam2nBiqgFgT1kKDY1igzjwk8PGv1fkLlIk
llBzCQsuXnnScV2auDF7UOEOZHue+eMPajYd+iZkjy5khkTYbdLyz5eW6gZiRdw=
=yqzO
-----END PGP SIGNATURE-----
Merge tag 'at91-cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/cleanup
Pull "Second batch of cleanup/SoC for 3.19" from Nicolas Ferre:
- fixes following legacy board removal
- removal of an unused config option CONFIG_MACH_SAMA5_DT
- move of some header files out of include/mach directory
* tag 'at91-cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
ARM: at91: move sdramc/ddrsdr header to include/soc/at91
ARM: at91: remove CONFIG_MACH_SAMA5_DT
ARM: at91: remove unused CONFIG_ARCH_AT91SAM9G45 option
ARM: at91: remove useless init_time for DT-only SoCs
ARM: at91: fix build breakage due to legacy board removals
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Pull "Broadcom Cygnus SoC defconfig" from Florian Fainelli:
This pull requests removes one level in menuconfig for the BCM SoCs for the
bcm_defconfig file.
* tag 'arm-soc/for-3.19/cygnus-defconfig-v2' of http://github.com/brcm/linux:
ARM: bcm_defconfig: remove one level of menu from Kconfig
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Pull "Broadcom Cygnus SoC platform support" from Florian Fainelli:
This pull request contains the platform code to support the Broadcom Cygnus SoC
using the iProc architecture:
- add support for the Broadcom Cygnus SoC
- consolidate the BCM5301X Kconfig options under the iProc menuconfig entry
- remove one level of menu in menuconfig
* tag 'arm-soc/for-3.19/cygnus-platform-v2' of http://github.com/brcm/linux:
ARM: mach-bcm: ARCH_BCM_MOBILE: remove one level of menu from Kconfig
ARM: mach-bcm: Consolidate currently supported IPROC SoCs
ARM: cygnus: Initial support for Broadcom Cygnus SoC
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Pull "Broadcom Cygnus SoC Device Tree changes" from Florian Fainelli:
This pull request contains the Broadcom Cygnus Device Tree changes:
- binding documentation for the SoC and clock
- cygnus SoC and clock dtsi files
- DTS for Cygnus Entreprise phone, BCM911360K and BCM958300K
* tag 'arm-soc/for-3.19/cygnus-dts-v2' of http://github.com/brcm/linux:
ARM: dts: Enable Broadcom Cygnus SoC
dt-bindings: Document Broadcom Cygnus SoC and clocks
[arnd: something went wrong here, we already had pulled an earlier
version of the same patches, which had the wrong license statement.
I've pulled this one over the old pull request and fixed up the
conflicts now]
Conflicts:
arch/arm/boot/dts/bcm-cygnus-clock.dtsi
arch/arm/boot/dts/bcm-cygnus.dtsi
arch/arm/boot/dts/bcm911360_entphn.dts
arch/arm/boot/dts/bcm911360k.dts
arch/arm/boot/dts/bcm958300k.dts
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
remove menu "Broadcom Mobile SoC Selection"
This requires:
- selecting ARCH_BCM_MOBILE based on SoC selections
- fixup multi_v7_defconfig to work with new menu levels of mach-bcm.
Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
StrongARM debug-macro.S is quite standalone thing, depending only on
register mappings. Move it to proper place and add Kconfig entry.
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch corrects the vendor-prefix for isl29028 in the compatible property from
"isil,isl29028" to "isl,isl29028" according to listed vendor-prefixes in
Documentation/devicetree/bindings/vendor-prefixes.txt. Incorrect vendor-prefix "isl"
was reported by checkpatch.pl warning for drivers/staging/iio/light/isl29028.c.
Thus incorrect vendor-prefix "isil" was corrected for every mention of device isl29028.
Signed-off-by: Darshana Padmadas <darshanapadmadas@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The model B and B+ differ in the GPIO lines for ACT and PWR leds, and the
I2S interface.
Signed-off-by: Matthias Klein <matthias.klein@linux.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Tero Kristo to move things a bit closer to becoming a proper
device driver.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUYkHXAAoJEBvUPslcq6Vz0CQP/2SUPXiq5/WXIe0Q1g4V1BmD
KQ8Jc9+DHbx3+7PBaG9QwKkPwI9f7xykNYnvqvanwU3FEqIeckL7yvkwZiN68zye
5QbBNPcco2X8mbs6PahDhkRcs5pUSAeqHkxB9hUipP9u0Np1MzmPV0pyltB0CyE4
6TI+F1u57HqqyyioeLdiyOTlIYQucfhqGitMMzgw7Z+YjcqUQBObKiu3f5xWj9kM
W9EB2APsY9h9D9OXwz4SmVAV1J6vdCtMkZtPmDdFTlj8Fy3qMd/B7gqRMuTcQcTK
L5LMu+n58e4jiuA0So4Hz9DcH+sM/Ui06bNWBFuZ69IGKSWpHKzwDn/tE6+r8cvq
oKvdL6Tu3lJv0fa8M1R1JJWYkvZCKGIhiIUc2kMjOYY+Ds8+82M/P3ng0RvPRhAQ
38HA0RjNSlsxhrpY8iFLcme+brHmuneaH/Ekthv+U66Kwfn3mZGJHl+Z5suo4Wu8
ySdjpqh4g5MZeWF2o95P7pTFNT5nopzh3vbLvhRYCChRFenBxrzbcQXarf3LMgbG
MVN1c4t1L9fK9bJoOF3kul9X+LsWdtMak6mMesN4RjlY/8X6cI3sfj4ptVJZRdz5
Vq1GPuouSzJ8dHR+tG5l4h9IQc9LrMtt/dVQrTQlvQF0jPP2RVxCWMnvdIG3SmoM
fEN/GFYRZslx7uT2hhsg
=r4xr
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.19/prcm-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Pull "omap prcm clean-up for v3.19" from Tony Lindgren:
Clean-up series for omap PRCM (Power Reset Clock Module) from
Tero Kristo to move things a bit closer to becoming a proper
device driver.
* tag 'omap-for-v3.19/prcm-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (26 commits)
ARM: OMAP2+: PRM: provide generic API for system reset
ARM: OMAP3+: PRM: add generic API for reconfiguring I/O chain
ARM: OMAP4: PRM: make PRCM interrupt handler related functions static
ARM: OMAP3: PRM: make PRCM interrupt handler related functions static
ARM: OMAP4: PRM: make omap4_prm_read/write_inst_reg calls static
ARM: AM33xx: PRM: make direct register access functions static
ARM: AM33xx: PRM: move global warm reset implementation to driver
ARM: OMAP4+: CM: remove omap4_cm1/cm2_* functions
ARM: OMAP4: CM: make cminst direct register access functions static
ARM: OMAP4: CM: move public definitions from cminst44xx.h to cm44xx.h
ARM: OMAP2+: PRM: add generic API for checking hardreset status
ARM: OMAP2+: PRM: add generic API for deasserting hardware reset
ARM: OMAP2+: PRM: add generic API for asserting hardware reset
ARM: AM33xx: PRM: add support for prm_init
ARM: AM43xx: hwmod: use OMAP4 hardreset ops instead of the AM33xx version
ARM: AM33xx: hwmod: remove am33xx specific module SoC opts
ARM: OMAP2/3: CM: make cm_split_idlest_reg SoC calls static
ARM: OMAP2+: CM: add common APIs for cm_module_enable/disable
ARM: OMAP2+: CM: make clkdm_hwsup operations static
ARM: OMAP4+/AM33xx: CM: add common API for cm_wait_module_idle
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Fix currently harmless but wrong sizes for various GPMC connected
devices
- Set up timings for several GPMC connected devices to get rid of
bootloader dependencies in later patches
- Enable various drivers for dra7xx
- Prepare Igep boards to support new variants
- Add intial support for BeagleBoard-X15
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUY5fPAAoJEBvUPslcq6VzbiUQAMIwdwWCqW3DZEy9PP8U1/ON
kBRsRCNveVOUyGQPWAQDcGREKo6qSVies46PLvJLEfPolTRFcU157ADPfID5+5FR
FcfkSAit4fSma+RdQqV9QwkyPvNWolL9zTzUeDEdu3Ic50NMhUhO5+ZT1PrNRtcR
S77H9yjIWqdqAma8uzFBiNp9oSSSERnl43FoOuHOsuqABYwWECejv+TC9FzA4TDM
b8rCHbBULwhk3oRDs558SBu+6YgnIppQ6EeXbWqv7D4lkmeVM3lPKg2MRXg/Zg42
+36nS9Ld0uIqs3u84p6IeauKCCz1D4rKsd/Wkzj9BiTI4/YD2e4aO4RhZVFugjAo
poTBiDD/fJwPm5bwFq7Yake3CY6q3l55gzOrisW+nbCRlMXm9rQ8Do23nIPsQ7tx
tbnjNvOfR7SFkgL0R1yyI138MMI/qvm0bkqXA7IP9mGN6v73tepBeHwFyHGwVebD
IFqrGbxIAC1A46w09q6yF9W3BExWUEW+FKIkV+wwg8NSMdsw6nDNlalcyWXyUO1n
j/RQ9y0EXJ051koMd8Wx5eWgpWRZDp3HrQkTqgcWTHf8JwS9fP1GFSM2LgUU0FJ4
OR/rozfEEJzeuhv4jAIDzD9o/dRd29Yx+xiFKxJfOK4yhIhBzlEmNfriv7HG7lYi
Pf0bsZwTIoy9FOiIjmhA
=7eWb
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.19/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Pull "Device tree related changes for omaps" from Tony Lindgren:
- Fix currently harmless but wrong sizes for various GPMC connected
devices
- Set up timings for several GPMC connected devices to get rid of
bootloader dependencies in later patches
- Enable various drivers for dra7xx
- Prepare Igep boards to support new variants
- Add intial support for BeagleBoard-X15
* tag 'omap-for-v3.19/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (37 commits)
ARM: dts: DRA7: Add aliases for all serial ports
ARM: dts: Add am57xx-beagle-x15
ARM: OMAP2+: igep00x0: Add pdata-quirks for the btwilink device.
ARM: dts: omap3-igep00x0: Remove i2c2 node.
ARM: dts: omap3-igep0020-rev-f: Support IGEPv2 Rev. F
ARM: dts: omap3-igep0020-common: Introduce igep0020 common dtsi file.
ARM: dts: omap3-igep0030-rev-g: Support IGEP COM MODULE Rev. G
ARM: dts: omap3-igep0030-common: Introduce igep0030 common dtsi file.
ARM: dts: omap3-igep00x0: Move outside common file the on board Wifi module.
ARM: dts: omap3-igep0020: Specify IGEPv2 revision in device tree.
ARM: dts: omap3-igep0030: Specify IGEP COM revision in device tree.
ARM: dts: omap3-igep00x0: Move NAND configuration to a common place.
ARM: dts: omap3-igep00x0: Fix UART2 pins that aren't common.
ARM: dts: dra7: add labels to DWC3 nodes
ARM: dts: dra72x-evm: Enable CPSW and MDIO
ARM: dts: dra7-evm: Keep all VDD rails always-on
ARM: dts: dra72-evm: Add MMC nodes
ARM: dts: dra72-evm: Add power button node
ARM: dts: dra72-evm: Provide explicit pinmux for TPS PMIC
ARM: dts: dra72-evm: Add regulator information to USB2 PHYs
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
omap4 and later, and to fix clock DPLL fixes by adding determine_rate
and set_rate_and_parent.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUZm0BAAoJEBvUPslcq6Vzpv4QALpopUWu91kXgiXBulKkmQ2d
PF0P4XqTH4wtJtSImkWVMahtSv04NVKFHeq4zxnZOPLDjg1km3ZumRpxVUI9v4V3
JqK2bRZRYtfgUU4bzPp8n09Yb2MJCmwOeXi2RFg7FPhRW+2Y9HbQFfGYU7fGbd83
Uihg8Ss4l0Je03kp+sMHadh1Mzka0sRMuAStVKJhp/+awt1E6zQkGKCUzZdCaXIH
7rIuPylv1usS+ZwkOQGPS0odBTOxIstkimIMK3kbSkuJteLgXCEzZ9ACwxGLkjNh
5JZyMI/D6m4uMmSzVySxK3yq3VEHjI5IBGHa4nFPpXhxUl86/gtIG/FxNfcf2DKF
hoDrlkfzDwLETchOF9Wd3pBRNSFCatDbwQcEYi/6AzY/eKoPZo3mDBTErctWD8Ds
LKFVUTzLxw90UQ0KnhYYaNATsqFUEbXOTL7iSN/diddAuBHkcLJC1yLx6xEUWQ+G
Qn6EvQvNb6ddx/01Ag8dOwDjJET4GD0XTLZ9T1DBSQ8+scd5pXE+NARRGgtPWAY7
RfsnU+x6UxKizVs3ibjU+2Eej7XA35Z3lgs36ve8iQtM7c72UK5pK8X7FMi5cVSA
tgpLQ1/xd7+oUZdzggBHjJtt9SoyKizjL+JKxD699yMP0i9qJezSDrD35nDzUvAA
oHd1ZuOlIadCyEOtNm5q
=R6s9
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.19/clocks-and-pm' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Pull "omap soc changes for v3.19" from Tony Lindgren:
SoC related changes for omaps. Mostly to make PM easier to use for
omap4 and later, and to fix clock DPLL fixes by adding determine_rate
and set_rate_and_parent.
* tag 'omap-for-v3.19/clocks-and-pm' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: hwmod: drop unnecessary list initialization
ARM: OMAP3+: DPLL: use determine_rate() and set_rate_and_parent()
ARM: OMAP3: clock: add support for dpll4_set_rate_and_parent
ARM: OMAP4: clock: add support for determine_rate for omap4 regm4xen DPLL
ARM: OMAP3: clock: add new rate changing logic support for noncore DPLLs
ARM: OMAP3: clock: use clk_features flags for omap3 DPLL4 checks
ARM: OMAP4+: PM: Program CPU logic power state
ARM: OMAP4+: PM: Centralize static dependency mapping table
ARM: OMAP4: PM: Only do static dependency configuration in omap4_init_static_deps
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Hello Arnd, Kevin, Olof,
This is a very quiet release, featuring a small cleanup, a tosa change
on its charger driver, and support for pxa device-tree based pxa27x
boards.
The device-tree part will only be fully activated once clocks support
is fully operation in the common clock framework.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUbR+1AAoJEAP2et0duMsSscgP/35kcEKXy1mVn7Tvf+bBrcCH
bFQrJafPI6TJ/XI62XmUZ88q8s8uCrzNsvLQOuG4He2caewboAeSjlD1hpDGM7kS
jckDWsKXa4F6VXfabzkEOVisP5gXnmtckGSeYAXtLQP2U9BzU5NECb3tcT7CW9gy
C0UhLM741Os95EeArzRfQORAvFVFyKbrC+Y7kQKLaW6Wxr5n8IunoZVThNjJWgIn
OBbBwGDwyX9oSp28hPcTRbkgzSsdHk7ch21OQgK8EbRCGQ4IHPB7TJ2FmSMu0cg9
3Iv2sGadnQnLfUczFbdCCu2mKbM1g8z/SfiLP6E3DL/5pvlpeEAxiTMsCNrJ/pOb
sP7eyNdiG3hgPPXgOoAp/b6OUh49cZS/3SGKvA1Ao8nkQO3pPvFEo55mGFc8h5TA
e9h0QUbL1ITJFcEBoWUlLxxhw8cE9BSuEQXUzyHpwhf/YKcVH4UUVQiSHjaxcHl5
a60nvyZ8IXXBgnVXaKDS07vw1ztg7+CQfvCOs/hMcAy6Y5DhBt0CvKTTUTrpRGa3
uHbVHVZ6G7mWoKoR8BmqFGgo1y1SX41MGslsnXsYqeIqYT+SLTsokaUOVVM+KA7k
pQ4xqobAICF57KuZ09MOkw32f9ShNuO5lS3/DDKSvDfs9liLHUqfP2AlhFvXYcXb
VSnVb1BjO1S2aKN0NdPN
=Kpce
-----END PGP SIGNATURE-----
Merge tag 'pxa-for-3.19' of https://github.com/rjarzmik/linux into next/soc
Pull "arm: pxa: pxa for v3.19" from Robert Jarzmik:
This is a very quiet release, featuring a small cleanup, a tosa change
on its charger driver, and support for pxa device-tree based pxa27x
boards.
The device-tree part will only be fully activated once clocks support
is fully operation in the common clock framework.
* tag 'pxa-for-3.19' of https://github.com/rjarzmik/linux:
arm: pxa: add pxa27x device-tree support
arm: pxa: remove unnecessary includes from pxa-dt
arm: pxa: move init functions into generic.h
arm: pxa: add device-tree irq init for pxa27x
ARM: pxa: tosa: switch to gpio-charger
arm: mach-pxa: Convert pr_warning to pr_warn
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
"dss_fck" is a hacky clock, used to work around problems with MODULEMODE
bit handling in DSS hwmods.
These problems have now been solved, so we can remove the dss_fck clock.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Archit Taneja <archit.taneja@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
RFBI iclk was set to point to hacky "dss_fck", which will be removed.
Instead use "l3_div_ck", which is the proper clock for this. "l3_div_ck"
is the parent of "dss_fck", so the clock rate is the same as previously.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Archit Taneja <archit.taneja@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Instead of using a hacky "dss_fck" clock (which toggles the MODULEMODE
bit) as DSS L3 interface clock, set the .modulemode field in the
omap44xx_dss_hwmod. This works now that the DSS core hwmod is enabled
during DSS submodule resets.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Archit Taneja <archit.taneja@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Set DSS core hwmod as the parent for all the DSS submodules.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Archit Taneja <archit.taneja@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Set DSS core hwmod as the parent for all the DSS submodules.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Archit Taneja <archit.taneja@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add a device-tree machine entry (DT_MACHINE_START) for pxa27x based
platforms.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Arnd Bergmann <arnd@arndb.de>
As the init functions necessary for machine init have moved to
generic.h, remove the unnecessary includes and prototypes definitions
from pxa-dt.c.
This removes the include of mach/pxaXXX-regs.h, and make pxa-dt generic
enough to accept other pxa variants.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Arnd Bergmann <arnd@arndb.de>
In order to have a unique .c file for all pxa variants device-tree
definitions, all the initialization functions for MACHINE_START and
DT_MACHINE_START have been put together into generic.h.
The alternative would have been one pxaXXX-dt.c file per variant.
The move is necessary because each include/mach/pxaXXX.h includes the
variant register descriptions which intersects and conflicts one with
each other.
The change is a preparation for pxa-dt.c to support multiple pxa,
ie. pxa3xx and pxa27x.
The machine files including mach/pxaXXX.h all include generic.h, which
guarantees no regression should be introduced.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Add the initializer for irqs in a device-tree machine on a pxa27x.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Switch to simpler gpio-charger module. PDA power requires additional
setup in platform file and is more suited for boards with separate AC
and USB charging inputs. Tosa has a unified input, so it's better suited
for gpio-charger.
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Use the more common pr_warn.
Other miscellanea:
o Coalesce formats
o Realign arguments
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Commits bcf8c7e770 and
4bf7753b8a introduced compilation errors
("error: 'NR_IRQS_LEGACY' undeclared (first use in this function)") because
they remove the asm/irq.h inclusion while the init_time function needs it
for the NR_IRQS_LEGACY definition.
In the other hand, the point of these commits is to remove board file
support, and init_time is only needed when booting non-DT boards, we can
thus safely remove init_time functions.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add reboot node, reusing syscon-reboot
- Add I2C nodes Hisilicon IP
- Add IR node based on Hisilicon IP
- Add Watchdog node based on ARM IP
- Add GPIO nodes based on ARM GPIO IP
- Add SATA node based on Hisilicon IP
- Add USB nodes
- Add MMC nodes based on Synopsys IP
- Add GMAC nodes based on Hisilicon IP
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJUXLB1AAoJEGROujcbgXtLFMAP/inSVfdrh06VppC62eaeHTjV
xX7qTOU8Kk9LpbNIU0KEOWkKWDpKHdwK/aG60+Ep2jly+IAxI9e7ZizzO/f20zKe
jYvvVr1ODvNsADXlZL/EkF8przzQjD9eQm0UCkjGKHEosad9cO/vGD4RYaw2Ip/s
N1gQMAvJJaQrYZQUGhbfW/DAJbf3EkevZnfY7WXwEejyQGfvzD6iJcL/5sRm36N2
12Nq+KaO8hg7Y2RED3yyqBPcf73feM8zDoqh7skuthGwKwtVYrsYb/AfJwaIIqPW
+llvO+VAxdIg4xu0OGpM4FsTrhTA444cRQfv0AtjG10cg+FOfk3SA9XshZCAuTiu
h1Kb/yQO3d/FfLvkl/MIpZbOaaDsXahysphaVNDMoEkrvoUvvT0JEbt4nh8+T9yi
ahOh9Z3IIrOHndY7CmNDrig9YAzcFJoW+0yqkDUSgmg6ZkuAnK9W07G98PAW1M5r
rB3emfHXjF9c4VLLO6PqetWEObhjyiIf3UY4wyjq7ZsYeT70OuhT3BqTPedLgFRM
KEPvbhzDtIuL65u6pbc3c5TSwceHZM9fU54psRsC3Ec29j/SzYTr486RVMffOFWH
Jh0Zz23K+LPRJHzI3Ci8D5/UXjhr+5/HZFXYxb3bs0OWEpEz/ZXRLdgYU3gsfxsT
1ut4CTRYMvT6oz9W05DC
=ltI6
-----END PGP SIGNATURE-----
Merge tag 'hix5hd2-dt-for-3.19' of git://github.com/hisilicon/linux-hisi into next/dt
Pull "ARM: DT: Hisilicon terminal SoC HiX5HD2 DT updates for 3.19" from Wei Xu:
- Add reboot node, reusing syscon-reboot
- Add I2C nodes Hisilicon IP
- Add IR node based on Hisilicon IP
- Add Watchdog node based on ARM IP
- Add GPIO nodes based on ARM GPIO IP
- Add SATA node based on Hisilicon IP
- Add USB nodes
- Add MMC nodes based on Synopsys IP
- Add GMAC nodes based on Hisilicon IP
* tag 'hix5hd2-dt-for-3.19' of git://github.com/hisilicon/linux-hisi:
ARM: dts: hix5hd2: add reboot node
ARM: dts: hix5hd2: add i2c node
ARM: dts: hix5hd2: add ir node
ARM: dts: hix5hd2: add wdg node
ARM: dts: hix5hd2: add gpio node
ARM: dts: hix5hd2: add sata node
ARM: dts: hix5hd2: add usb node
ARM: dts: hix5hd2: add mmc node
ARM: dts: hix5hd2: add gmac node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Use keyboard as gpio-keys node name
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUapdxAAoJENfPZGlqN0++GJ0P/ROuRziwZCeXmsOv6zPNv1XR
EVY93sam8qoFTgJaGiGbEi7stOIpEW0GPxUJzGDPgysMhSxBt2hqqAMtzRAK8uvl
d+zMFIPGxPpzQW7lpVdeYnZLyr78jmhwXUsX//bOyIAmhDA80Oo43rWK5ksgGXml
wkGVhKRipVkyCRztae72T0I5oTIbPSs25P4Qo6NdYlzLOWQ9ss3iQWxYBUBlMb/v
MwJIy515IF+qhLJngaIG1J+d5x2s4gF68szv+oaUFPH6fRFpgEtl7XMrnvFrj/us
HGWOi2L6cRBrySkY9D/ApbC4VC/QGbGdRkOJxWj+/p+JxXm3WVm+uPzH6WNARsFU
EDrODAUfob9eilylDOxrv6fKmc/i4NOYfPfOor9dYDWeNgSXLgWorB1P26cVR9Yg
bhE5zUcJguw2PJDPIDdfotFxU4cdU6E/NUaMVbGvKRjwB8zTYxMoj2psdYxorMap
MRn504OAoiHiXqgGHaKvRYTlqE2PO0Mqc1EsPJSE1MVwdI2P4i4SPb3/qija8LWW
bz1bTxxdCcGEe17EDisgbrqF0Bmeit3GB896UR8XZPy/Xsocjx0p4NkFatkkrMAb
UNcSY6UfOssqH0+0CfMELP1uLOhwMZGNpw/ifKvOJGO7RDPi9d1VYSjY+vqWaf96
nLFR+oR2uja0F0/DaotP
=H8mr
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt-cleanups3-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Pull "Third Round of Renesas ARM Based SoC DT Cleanups for v3.19" from Simon Horman:
* Use keyboard as gpio-keys node name
* tag 'renesas-dt-cleanups3-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: kzm9g-reference: Use keyboard as gpio-keys node name
ARM: shmobile: koelsch: Use keyboard as gpio-keys node name
ARM: shmobile: lager: Use keyboard as gpio-keys node name
ARM: shmobile: armadillo800eva: Use keyboard as gpio-keys node name
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add parent_hwmod pointer to omap_hwmod. This can be set to point to a
"parent" hwmod that needs to be enabled for the "child" hwmod to work.
This is used at hwmod setup time: when doing the initial setup and
reset, first enable the parent hwmod, and after setup and reset is done,
restore the parent hwmod to postsetup_state.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Archit Taneja <archit.taneja@gmail.com>
[paul@pwsan.com: add kerneldoc documentation for parent_hwmod; note that it
is a temporary workaround]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
* Enable DU using DT on marzen/r8a7779, lager/r8a7790 and koelsch/r8a7791
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUWBRRAAoJENfPZGlqN0++Pm0P/3Qa+X8o4kAZETi+ER+Q7s/B
d0EGNAw/1b/Si7D2SpftRHvHx5TDL2QiU0QIAPWAcd4u1NJxaYP/SDwRETGQnHbV
TsL25mASYNByP6DXTrBJneiDS5U88DwVP5q5FW9WEkvIbmtzbxTe/7OnSPAjhxl0
83kXATiHwdRct4KYLW8ngNhaY/9OUjrL+wZ8ffN/dM0EpSyixXK5bHmWLFC5/HGY
D8b+zW/NTSBOYTk1OR6QSlp/eGmjRCG2UJn4toHWKse2defxZ/hyTUas4ysgDXzC
gsWT96yLwmueTRcSBglkKGFbPukWcyKPt7sRphtZlTYbJmpS0ncBTfC2s0+Jv2RR
VDpeAmB6NXQ5L7Ck51ryt4A8kX88uOgHrmcz+NGJadNE07TZgLJBLDf6aSjDsytr
NIZq7RFNK975Qv3QldQJX4PYmqcWJMI5WDPnm2buzZsKHkjQrpKIicAiSlwzJX/9
4SeCF2yrZuJJVnJwit8gOvvBHq5ORQrumAs1xrPQiu570p+6jBjjJ5v4sDvuF5UY
nXfMTUGrNYe8JSxjf8NTmXJX8DRKSLq0tGcHbzajvKVzuy8Gp6+yFNkrqzQj2HK6
dy4TLtuvMk5JB4E5Q22xdYYV4TorO28qiuGoGDOOwIx6+940MdY/ucE2Z4i4M2R7
/NZJCpITds6HxVZJWAKo
=m0Ov
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt-du-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup
Pull "Renesas ARM Based SoC DT DU Updates for v3.19" from Simon Horman:
* Enable DU using DT on marzen/r8a7779, lager/r8a7790 and koelsch/r8a7791
* tag 'renesas-dt-du-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: koelsch: Enable DU device in DT
ARM: shmobile: koelsch-reference: Remove DU platform device
ARM: shmobile: lager: Enable DU device in DT
ARM: shmobile: lager-reference: Remove DU platform device
ARM: shmobile: marzen: Enable DU device in DT
ARM: shmobile: dts: Add common file for AA104XD12 panel
ARM: shmobile: r8a7791: Add DU node to device tree
ARM: shmobile: r8a7790: Add DU node to device tree
ARM: shmobile: r8a7779: Add DU node to device tree
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Kernel-side struct msghdr is (currently) using the same layout as
userland one, but it's not a one-to-one copy - even without considering
32bit compat issues, we have msg_iov, msg_name and msg_control copied
to kernel[1]. It's fairly localized, so we get away with a few functions
where that knowledge is needed (and we could shrink that set even
more). Pretty much everything deals with the kernel-side variant and
the few places that want userland one just use a bunch of force-casts
to paper over the differences.
The thing is, kernel-side definition of struct msghdr is *not* exposed
in include/uapi - libc doesn't see it, etc. So we can add struct user_msghdr,
with proper annotations and let the few places that ever deal with those
beasts use it for userland pointers. Saner typechecking aside, that will
allow to change the layout of kernel-side msghdr - e.g. replace
msg_iov/msg_iovlen there with struct iov_iter, getting rid of the need
to modify the iovec as we copy data to/from it, etc.
We could introduce kernel_msghdr instead, but that would create much more
noise - the absolute majority of the instances would need to have the
type switched to kernel_msghdr and definition of struct msghdr in
include/linux/socket.h is not going to be seen by userland anyway.
This commit just introduces user_msghdr and switches the few places that
are dealing with userland-side msghdr to it.
[1] actually, it's even trickier than that - we copy msg_control for
sendmsg, but keep the userland address on recvmsg.
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* Enable PCI domains for R-Car Gen2 devices
* Make APMU resource code SoC-specific
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUZAXRAAoJENfPZGlqN0++qlgQAIne34JegIo6zR6IHUyHzvNK
QqXeFTQvWyUX5jCVsn79gL7gwOuOoSwDqvrdGOla/LH4zayfG/kloFowxoO6qcdl
UGKKTJMWgh4BKMusIskjoDShqGDIbyPRMcs+SdmU0+qrGZh9gYfifUZqopQ2+FpL
2vvPA0vR5J7kfT5Vg8sUkYdbPoivcnL76D5nZonsEcIn0wKEyTL9AY0b5uNMJIxc
em1zBtt5zICwA5iiJKe7Q59z1st5Z/LDWFQP24uquKZwfShawMddm9kPfLqHlSnr
SD9qzAaBPar30R+QDfQH7pC4q3MlALAqAmIWIgaBDLubkJwd5N5yTAgQ7Uw4uqH6
8mwfYY4cnyD9R5CTVUYVn/pY1+QYjjXoYHWlgJkhhsnC8iwYd/FLcXhy793Kk0ac
b2UusUO/zEILVh2wZT2ki50LIURM7dW0CUhl5Gt4G8c+zMQ8FwtZi33eW9Gpf+1k
xWPvKMt5rIi0YyI19mxlhdAp2GF2yWR7uycb4FeN/z/ce5GOAaDOWt1Gtib3YjM9
EQxGFPCWhrTJ/vfufYr4tfPLJeedQ8XpFIKL9ACvIY67zOst5nEkE9g6Lyt23ByU
NbwQSHV8dpIWGkmps4QazDyy2vwQTrUxa0XPU2JcAxO50UjiHGlK6WOKAn610StU
xji8z2cdEbNZ5zV/1tfs
=g7rn
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc2-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Pull "Second Round of Renesas ARM Based SoC Soc Updates for v3.19" from Simon Horman:
* Enable PCI domains for R-Car Gen2 devices
* Make APMU resource code SoC-specific
* tag 'renesas-soc2-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Enable PCI domains for R-Car Gen2 devices
ARM: shmobile: r8a7791: Correct number of CPU cores
ARM: shmobile: Separate APMU resource data into CPU dependant part
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Select CONFIG_ZONE_DMA when CONFIG_ARM_LPAE is enabled
* Add CA7 arch_timer initialization for r8a7794
* Handle CA7 arch timer delay
* Add shmobile_init_late() to sh7372
- This is consistent with other shmobile SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUWBX0AAoJENfPZGlqN0++oZoP/1BV0Lzhol3eQ/RlqG9maNCO
iR2tAdfeScxwqD+VE8pHJQIoyYF8sfKKEaJxsyPl2KP1BzzBXGkNnsp35vNPG8p7
32AY27+98R7AqJ2ajKAqqdc7ooZLam1BW7kv99XmSKx/9n4Y1RKXaXVweRmxh3d5
dBaKGVX8ixl7yDZ7prsQqECzh7XN1/rhPXP50nq0aZtR0CRgAPzHyGGooc7s3zIz
7enlXev2u178I0YH9kujBbB/pjWCxrygKsB7gWp+t/klb9R0MWmVoB8/ae5rFRbq
E+ULTVJ2G0cnhCTncu7N65/N69rmrbCGaGLBzKqV4Ve3qXImr0L6AqGmAGPMlqJT
V+C44tGCjTJ7rc2gwv3Y6EPi/BQmEGRAGUp6GLBC0wexQdP6GRa7HrxsiRPuXrF6
OTG42oGqslMNemF0yZjzJU/SDutLYqYHhbqzl8akGr+PpB58ybjplM0mAyae/pp6
JTDYqCvlowsXN3FWgSZOIZ8UFM58UElGt9DBGCyEypTUADAFqD0SiUU7QCRFGKaj
VhfgQ/gzwmKG19C1DgLTZv+8fzR/lvwBBtjwlP0io4Rd52rUGtmxcvH/0KV8INXq
GsI9mEb6B4ZUFhG0Dgkna1XM9227PIQr126K/PDPjQPNHxVoVMQUuo9DrFNmXMt7
XEhA8eE9kxnf73DQEPB7
=bG2T
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Pull "Renesas ARM Based SoC Soc Updates for v3.19" from Simon Horman:
* Select CONFIG_ZONE_DMA when CONFIG_ARM_LPAE is enabled
* Add CA7 arch_timer initialization for r8a7794
* Handle CA7 arch timer delay
* Add shmobile_init_late() to sh7372
- This is consistent with other shmobile SoCs
* tag 'renesas-soc-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Select CONFIG_ZONE_DMA when CONFIG_ARM_LPAE is enabled
ARM: shmobile: rcar-gen2: Add CA7 arch_timer initialization for r8a7794
ARM: shmobile: sh7372: Add shmobile_init_late()
ARM: shmobile: Handle CA7 arch timer delay
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch fixes a long standing issue introduced during the 3.16 merge window.
Shortly after the merge, exynos5250-based arndale boards began to produce the
following errors:
kern.err kernel: exynos-cpufreq exynos-cpufreq: failed to set cpu voltage
kern.err kernel: cpufreq: __target_index: Failed to change cpu frequency: -22
Further analysis revealed that the S5M8767 voltage regulator used on the
exynos5250-based arndale board utilizes the S3C2410 I2C controller. If the
S3C2410 I2C controller driver is not enabled, the S5M8767 voltage regulator
fails to probe. Therefore a dependency exists between these two drivers.
In the exynos_defconfig both CONFIG_REGULATOR_S5M8767 and CONFIG_I2C_S3C2410
options are enabled, and no errors are produced. However, in the
multi_v7_defconfig only the CONFIG_REGULATOR_S5M8767 option is enabled and the
errors are present. So let's enable the CONFIG_I2C_S3C2410 option in the
multi_v7_defconfig to allow the S5M8767 voltage regulator to probe.
Signed-off-by: Tyler Baker <tyler.baker@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
This contains the serial port numbering fixes that are required for the
serial port numbering to stay the same with or without the serial core
making use of the aliases defined in DT.
eMMC is also fixed for TN7 and Roth boards which were using the wrong
regulators.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJUZNbZAAoJEN0jrNd/PrOhZugP/2SABzzEa1EwAwE0ksM/Z47x
MYDGUQ7nKuagGNwdHsQPEf+JXLADS1eOzdoQ187SaJdSt0DmbOzoU2IbG9b6Rm4j
31Al6XL2PdyDOeopMSbrwLHh7+HVhaW7TEQcCMqDJEEgsJIWY0sLuuDLLirpMoaO
oPD9anXAlVYhcDN8bPdW0gUMrZOGU9rB+q1jTj9kW1qX9xsNHb05WvLiZOwV032d
Hw0/q/BJ/MzoqXT/Z2UrIPpgcL9xnVw3NUPqE+dCXoAGRSsG6ggue+9TDAVyU7Xw
Fg4Hwm/qwnk1lAKvMgGw+fjLd/gUdIuo2kAg5sY2tGo+HTbgMMIz2LlXoz3gmx8/
XnBIKnCqv79kVIyRsOVYLXWrPJx5Ns8rMWXxM/SnD6hPNsudE/rr5dBHP+vS40AU
V/ty6G7BME1LM99h76Ixoaaw5ojjYLPdTb30SEKePKLsY+8gYh6up5Fuo1SdENlv
sIuQR1R7pGbsmshfMd5+xNH55QEucYD/IKz59Zc5+fZJBMEViMH2Q2NIsLYCsO1C
oSN3ck9Gwan2PrEV42uVOHPoQdqta8ZGm02Fl3pJb/2W04/KB3ahdCcPbBI9UGol
zR1EPbUlEiLN1Fczw7gy0/zrFO2Cq4VzwuHZgwiQvsxY8K2ChmsvloBnt9Rpj+VS
Xqbno7ENFXdRiIMWoIn0
=ick3
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.18-fixes-for-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into fixes
Pull "ARM: tegra: Device tree fixes for v3.18-rc5" from Thierry Reding:
This contains the serial port numbering fixes that are required for the
serial port numbering to stay the same with or without the serial core
making use of the aliases defined in DT.
eMMC is also fixed for TN7 and Roth boards which were using the wrong
regulators.
* tag 'tegra-for-3.18-fixes-for-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: roth: Fix SD card VDD_IO regulator
ARM: tegra: Remove eMMC vmmc property for roth/tn7
ARM: dts: tegra: move serial aliases to per-board
ARM: tegra: Add serial port labels to Tegra124 DT
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Correct IIC0 parent clock on r8a7740
* Correct SD3CKCR address to device tree on r8a7790
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUYrybAAoJENfPZGlqN0++V0EP/1VvilCY1UkP4JG142J9GLKl
8V4H30OfVWr9m9O6LPEwOB/qkl9L6mlyu+oxTi1VI+96542IREfYz/REdy3HmgS2
zD7SEMikoqNbuPfjimonBSbtjRvNLrdcNBjrP9u0pJEZYmGBJelNWxTHAsp6fxDy
6nG+/hiNO3i7hyMaZwsYB+5E+9itJkSv4YOS9bh0IAM+WIMN+VasrMSGu9ZKUCT/
f2zcy2xLR/Zmd2ad6zpfFXDznO6C2vBfGg+fZ97K7H5mkSdkpSR5vYwxVWQY+49L
iTlevIi9E7ubp3QIgiSDy9qLAmWxL6wGm4Utj90c+jSKeLPd9NTmGAz0bIjVSYND
b8pmdww3dbYsxyqsWbYlscpYwxN83jynEQx3ZU0dCEA9X7o7SfkQpZlhw/qkNAIu
3iwEqNbrLLlz9nyl7lMFRUPGcn6pugd5ylq6zhfHR9cRRuMAjkkA/1iTEt4kPXSq
6wFLArgNSID9ood0mpuVzp0xWmqY9XsxwYQJLfIE53W8CatWP/HAWAEBiunCJVTg
p0A1WbRrVL0GIQ8QEOjfAo+a0WF0gaiT4Xr66tq6U0o0JwSXr7fws77cl82GXyol
m7AKJ+lzPS2RQg0DdjZAQ1OkA9laQmXtQb44a6OipMw2JdM3oG5yvK0IAb+sxjh1
mOiUw0Zggyf/L+PAxeKJ
=Du2A
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes
Pull "Renesas ARM Based SoC DT Fixes for v3.18" from Simon Horman:
* Correct IIC0 parent clock on r8a7740
* Correct SD3CKCR address to device tree on r8a7790
* tag 'renesas-dt-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock
ARM: shmobile: r8a7790: Fix SD3CKCR address to device tree
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Set i2c clks_per_count to 2 on kzm9g
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUaV6WAAoJENfPZGlqN0++9AUP/iDfxX9KCy+xAn6UzmxGfvRB
tJuyu+0L/ZAIRSl1ZNaCueluDJWuYOSHTt7n4CP8SYbJIXIXDnlkK7RhRmiPVkkr
1IolYesNnv0Nb3BIIXob/TdOY0DmoPGwR0Y5aQz16OED4lTYO+DDWfMS9JWLWoy5
ILAqfGJl3qJop1QIzt9miGALQ06rj/NZdYSxu3fAz5bd5AiVPI9MCqcO0xiISluo
yAKL48p8alSdiltcaUQ+1PyFLRBaT58MEhrkfylBzlS83HD7MZK6ki1lS1k+Ghcz
TJpXCZQvy/VIgtgDj7Dm+pGzbChJbwOQkVxzfCWARrPFjQrdsUjMJ8pNWjwCU9qK
vwJkfqsVaGu77t7+4//llDSp8UYbD5uKF2a1H69O1OJs7hVMBEUVHp2XjLX6ceUz
OcZa0KWK0f+AlsisSLNuiOJ5LPb43E4ISYhSIs5pXhydhQGb7GFMA6mFFarPb4CA
EAHWcQ6sqtwVXnISACK2uCY2WO0oL9nCDcA7e4ZBqGFcx55pD6P68wpmztDUYHyb
q9FmVIyCU5s6dK6q+7YxJ8z/AN89AeiscUN2Q43N6xDnM2VZbrhs9dSsYnTiuPb6
ecNJmuzi8NwUoAr8dVn39pmAp56WYsKaBwbktGRzFPD0Fy43RdusSHyJzoHq637+
4FC8N7jGuOqj6dgkaYbP
=e8cy
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes
Pull "Renesas ARM Based SoC Fixes for v3.18" from Simon Horman:
* Set i2c clks_per_count to 2 on kzm9g
* tag 'renesas-soc-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: kzm9g legacy: Set i2c clks_per_count to 2
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable the RTT and GPBR devices and specify the general purpose register
used to store the current time.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Enable the RTT and GPBR devices and specify the general purpose register
used to store the current time.
Enable wakeup on RTT event on the shutdown controller device.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
at91sam926x, at91sam9g45 and at91sam9rl SoCs all have at least one RTT
block.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add rtc support to the at91sam9rl dtsi file.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
During the submission of these new sama5d4 files, the GPL notice mentioned the
device tree as a library, which is not really accurate.
Fix all these library mentions to reflect the fact that it's actually just a
file.
Reported-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
A fix for the A31 dma controller that requires the AHB clock to be parented to
PLL6 in order to operate.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUa8ABAAoJEBx+YmzsjxAg2HoP/3UCG+58cnEAQTFwVsroU4MT
f91pcPounpGXPmZupQCs/aEHQKSVOEzn2EnHSZQb3I9XEezVKqJHgwm/BlsCHkL0
8WCnG/72p/HoWyMDPr2EPIa1s5oS5wqG0V7rTztTndQI/jHXqPqOdhkicF2n4B7D
hLTxIGeCXA8yh6B3pXF4SdvJEd/I63gcQexzxOJ4HSEsEyGExeTSWwNJqfkl+T2f
ZdyKvvgDbqfgwM6eOX8R6n9RET1Rxtm8NBVdSB2ruuixSV3TT3nYofOgdFddSMtf
WpNUwbVBKE/J0r+NpSQ44E4hFR8W99ieXH3HCPn1+GjHWvFALC0cZTPd6NgIkpBy
uEuAVShJd02Z0JzeTVW7DaCyDgW0QRV7BhBazKuCMppbv8eNR8CbqPe44iY1tmmP
+m7b3HURgs9I5FAwDMrScSPfyH7+tALdTmsXJdBk273cXptRoJAPe+N5G02WLjSk
wo1sW86XcG02Jd20lbdubjsSL5b6pD5pu8zjKISZZI/1kH8m8delvH+ObCjsvaC8
DWELzxRqE6hsi6HjWmkakCZvydn9P0Te5AjX/kzonpqGN30Kzwkk902K3gI/6fT1
5bE9QcC435ckeWLGPMRkLSadHIaUMrmlzt0X4ZN9Evu8F4heT/HqT9wApx8dCwuo
AkcVwXY7Kzxs6dICuojB
=SmW6
-----END PGP SIGNATURE-----
Merge tag 'sunxi-fixes-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into fixes
Merge "Allwinner fixes for 3.18" from Maxime Ripard:
A fix for the A31 dma controller that requires the AHB clock to be parented to
PLL6 in order to operate.
* tag 'sunxi-fixes-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: dts: sun6i: Re-parent ahb1_mux to pll6 as required by dma controller
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
There is a macro for the irq type.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Second part of at91sam9260/at91sam9g20 legacy !DT removal. This is the core !DT
support removal for these two Atmel SoCs.
Use the Device Tree for running this board with newer kernels.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Remove old board files that use at91sam9260 or at91sam9g20 Atmel SoCs. The
device tree is mature on these SoCs. It must be used now.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Remove legacy support for at91sam9263 boards.
This include board files removal plus all legacy code for non DT boards
support.
Use the Device Tree for running this board with newer kernels.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Explicitly set the dr_mode for the dwc3 controller on the
Snow board to host mode. This is required to ensure the
controller is initialized in the right mode if the kernel is
build with USB gadget support.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The LEDs on the kzm9g board are labeled using upper-case characters.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The LEDs on the koelsch board are labeled using upper-case characters.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The IIC nodes used the generic compatible properties only.
This causes the driver to fail when using Standard Speed, as the
operational clock is driven by the 104 MHz HP clock:
i2c-sh_mobile e6820000.i2c: timing values out of range: L/H=0x208/0x1bf
i2c-sh_mobile: probe of e6820000.i2c failed with error -22
Add the SoC-specific compatible property to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The IIC nodes used the generic compatible properties only.
This may cause the driver to fail when using Standard Speed on IIC
masters where the operational clock is driven by the 130 MHz HP clock.
Add the SoC-specific compatible property to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Current Koelsch I2C2 has 400kHz settings,
but, ak4643 audio codec chip which is connected to I2C2 can't
work such frequency.
Fixup I2C2 clock frequency to 100kHz.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Current Lager IIC2 is using default clock frequency,
but, ak4643 audio codec chip needs 100kHz
This patch clarifies IIC2 clock frequency as 100kHz.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable usb1 on Google Chromecast which is connected to micro-USB
plug used for external power supply, too.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Adds nodes describing the Marvell Berlin BG2CD USB PHY and USB. The BG2CD
SoC has 2 USB ChipIdea controllers, with usb0 host-only and usb1 dual-role
capable.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Enable the 2 available USB PHY and USB nodes on the Marvell Berlin BG2Q
DMP.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Adds nodes describing the Marvell Berlin BG2Q USB PHY and USB. The BG2Q
SoC has 3 USB host controller, compatible with ChipIdea.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
RESET_CONTROLLER is meant to be user-selectable. To respect that,
do not select it automatically when using ARCH_BERLIN.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Add nodes for I2C controllers A,B,AO, which are available in both
Meson6 and Meson8.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Carlo Caione <carlo@caione.org>
This patch makes the edma driver resume correctly after suspend. Tested
on an AM33xx platform with cyclic audio streams and omap_hsmmc.
All information can be reconstructed by already known runtime
information.
As we now use some functions that were previously only used from __init
context, annotations had to be dropped.
[nm@ti.com: added error handling for runtime + suspend_late/early_resume]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Daniel Mack <zonque@gmail.com>
Tested-by: Joel Fernandes <joelf@ti.com>
Acked-by: Joel Fernandes <joelf@ti.com>
[nsekhar@ti.com: remove unneeded pm_runtime_get_sync() from resume]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
These casts to char* are unnecessary and slightly confusing, since
both operands actually have type const char*.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Convert printks to pr_<level> and pr_warning to pr_warn.
Other miscellanea:
o Coalesce formats
o Realign arguments
o Use %s, __func__ instead of embedded function names
o Add pr_fmt to mityomapl138 and mux
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This enables the L2 cache controller available in Amlogic SoCs.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
This adds a dtsi for Amlogic Meson8 SoCs. It differs from the Meson6
dtsi for the number of Cortex-A9 cores (4 vs 2) and for the frequency
of clk81.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
This enables the L2 cache controller available in Amlogic SoCs.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
Add a MACH_MESON8 symbol and add "amlogic,meson8" to the list of
compatible strings for the Meson DT machine to support devices based
on the Meson8 family of SoCs.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
This driver is used by the ehci / ohci usb controllers on stih415/6 SoCs.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Enable the ehci and ohci drivers in the multi_v7_defconfig so that
the USB controllers on stih41x work by default.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Following Arnds review comments, update the miphy365 to follow the
common convention of naming the phy node names as phy@addr.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
At the moment we don't take a reference on some core interconnect
clocks which means when CCF turns off unused clocks the SoC will
hang. As a temp soltuion we will boot with clk_ignore_unused
parameter for all b2120 boards.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
The STiH410 is an advanced multi-HD AVC processor with 3D graphics acceleration
and 1.5-GHz ARM Cortex-A9 SMP CPU part of the stih407 family.
It has wide connectivity including USB 3.0, PCI-e, SATA and gigabit ethernet.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
The stih410 soc which will be added in the following commit is very similar to
the stih407, to enable maximum re-use of the dt files this commit abstracts the
common parts into a shared dt file stihxxx-b2120 for the board, and also a shared
file stih407-family.dtsi for the SoC.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
This patch adds the required pin configiguration for the extra usb
controllers found on the stih410 device.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
This patch adds the DT nodes for the 4 usb ehci and ohci usb controllers
on the stih416 SoC.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
This usb picophy is found on stih415/6 SoC.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
This patch adds the required pin config for all usb controllers
on the stih416.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Certain ARM CPU implementations (e.g. Cortex-A15) may not raise a
floating- point exception whenever deprecated short-vector VFP
instructions are executed. Instead these instructions are treated
as UNALLOCATED. Change the VFP exception handling code to emulate
short-vector instructions even if FPEXC exception bits are not
set.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Tested-by: Will Deacon <will.deacon@arm.com>
Tested-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch remove clear_thread_flag(TIF_UPROBE) in do_work_pending(),
because uprobe_notify_resume() have do this.
Signed-off-by: Yalin Wang <yalin.wang@sonymobile.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The Mele M9 has an ethernet board, enable it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
PLL6 on sun6i has multiple outputs, just like the other sunxi platforms.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Commit d127e9c ("ARM: tegra: make tegra_resume can work with current and later
chips") removed tegra_get_soc_id macro leaving used cpu register corrupted after
branching to v7_invalidate_l1() and as result causing execution of unintended
code on tegra20. Possibly it was expected that r6 would be SoC id func argument
since common cpu reset handler is setting r6 before branching to tegra_resume(),
but neither tegra20_lp1_reset() nor tegra30_lp1_reset() aren't setting r6
register before jumping to resume function. Fix it by re-adding macro.
Fixes: d127e9c (ARM: tegra: make tegra_resume can work with current and later chips)
Cc: <stable@vger.kernel.org> # v3.13+
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add serial port debug macros for the SCIF(A) serial ports.
This includes all supported shmobile SoCs, except for EMEV2.
The configuration logic (both Kconfig and #ifdef) is more complicated than
one would expect, for several reasons:
1. Not all SoCs have the same serial devices, and they're not always
at the same addresses.
2. There are two different types: SCIF and SCIFA. Fortunately they can
easily be distinguished by physical address.
3. Not all boards use the same serial port for the console.
The defaults correspond to the boards that are supported in
mainline. If you want to use a different serial port, just change
the value of CONFIG_DEBUG_UART_PHYS, and the rest will auto-adapt.
4. debug_ll_io_init() maps the SCIF(A) registers to a fixed virtual
address. 0xfdxxxxxx was chosen, as it should lie below VMALLOC_END
= 0xff000000, and must not conflict with the 2 MiB reserved region
at PCI_IO_VIRT_BASE = 0xfee00000.
- On SoCs not using the legacy machine_desc.map_io(),
debug_ll_io_init() is called by the ARM core code.
- On SoCs using the legacy machine_desc.map_io(),
debug_ll_io_init() must be called explicitly. Calls are added
for r8a7740, r8a7779, sh7372, and sh73a0.
This was derived from the r8a7790 version by Laurent Pinchart.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Another small set of fixes:
- Some DT compatible typo fixes
- irq setup fix dealing with irq storms on orion
- i2c quirk generalization for mvebu
- A handful of smaller fixes for OMAP
- A couple of added file patterns for OMAP entries in MAINTAINERS
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUaTBRAAoJEIwa5zzehBx3+wYP/iTZRQpaYuo3zw55oyYhyeUZ
oh530Fz9ItyMi8rcGl4Tf0hh4tcdhYkpB2nCBgQ4x7FexyLvd2ZubLXOwwOnVter
D+pVjpxdBuKtCdYm1+x35Zk6efbOYtJ7UDE1cGUQP+zA56Rx0K935/vlKZVkxJ19
ytEksAna7z9PR4wR/YhYpMdcAxa7YXm7qnlU9gLx56MPBzUN5yvTP9bXs1qBOgPw
ZC18uunr3RNIcmqEui+SEsCiDflkAe3xbwKvnsCmvQsyDsKYRmtuPOK8B86c9K9b
LWedSG36/bcxb6IG/McAcqYgtReAUz0KkxvXu3SsAbWOLnzWPCgDUSgbvAtFt1Oz
qtYPNNqqEC9fpiJE2LKJopK83+p5tYZ+MrJjGsqtIUJhLBW5xFs77NkrMDyEJJyN
T+6GDDWk1UsMI49MRb1Nw6GTKmJvcOr0V3+OyHdjAOYqTbSeToOr5HHzCVYqhBTy
fN3syzZKPAjXddAl70ixEy2o9CLckUBBrSrMyIEfENCAP74w+tc3UHFIv0yGmyDb
95I5dfX2mvb/rxckQLOW7ewjp4DPAq7Kdo6+CBR39TJUEolweNQlUcZHQccalS6I
cQ/SnVCYTQkIMFIhPrQQnL6/Yvwj/Qo+wu/hJL+3f4XKOKEQ88QpgCgVwKVN9Scg
nBsEM2n2IbLPwuzAkvdv
=0RR/
-----END PGP SIGNATURE-----
Merge tag 'armsoc-for-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Another small set of fixes:
- some DT compatible typo fixes
- irq setup fix dealing with irq storms on orion
- i2c quirk generalization for mvebu
- a handful of smaller fixes for OMAP
- a couple of added file patterns for OMAP entries in MAINTAINERS"
* tag 'armsoc-for-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: at91/dt: Fix sama5d3x typos
pinctrl: dra: dt-bindings: Fix output pull up/down
MAINTAINERS: Update entry for omap related .dts files to cover new SoCs
MAINTAINERS: add more files under OMAP SUPPORT
ARM: dts: AM437x-SK-EVM: Fix DCDC3 voltage
ARM: dts: AM437x-GP-EVM: Fix DCDC3 voltage
ARM: dts: AM43x-EPOS-EVM: Fix DCDC3 voltage
ARM: dts: am335x-evm: Fix 5th NAND partition's name
ARM: orion: Fix for certain sequence of request_irq can cause irq storm
ARM: mvebu: armada xp: Generalize use of i2c quirk
Some DT files had a typo with a missing "5" in sama5d3x first compatible string.
Signed-off-by: Peter Rosin <peda@axentia.se>
[nicolas.ferre@atmel.com: modify commit log]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
MAINTAINERS file to avoid missing PMIC and SoC related patches:
- Fix random hangs on am437x because of incorrect default
value for the DDR regulator
- Fix wrong partition name for NAND on am335x-evm
- Fix wrong pinctrl defines for dra7xx
- Update maintainers entries for PMICs and SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUYj1ZAAoJEBvUPslcq6VzpBEQAL12JZOSxU7WP5gTaKmTTBi9
YVIlE0yM8gkkfbyAqZLZDrssjjRPE696ys6aB+WdhuxasyIH5uhn9UHjWW/4UflG
8rEazQJBC/gqv8DqBUDGz/c3EiKOPmHt6XUNeFxeDHgRrOVh1ivpxNOGKGnJOMmi
UNpSBejWUO7O8vR2mDgnDeSTgmIC6yq5Wm7JDaWwuh9iyCmzD2z0+AYF8tf6vrDf
LubKHXfdatNjAj5NCyJQsJtfr9iS57o3YIsqOS43KvGIYDLVQhzbezQjGtkAavUR
HNZcVDbmK3ohIsPT6CuzPIbAg+l0YL/8lRytSaFjmMN6b2TPV6NKeijIK85GUYvN
aR/8nFnZSJNaG8F7NAPuA6qxq4d0m6oPC3q2PLX9P1RQNP+ch/DrQarK4AMMMpV6
C8sUDvhWYH7Lsa/xVomKo/0pTNc+K11xdVpxxdEridYLsCxR1UE7yr2P8tM0gq2F
yb14rsw9kgH89n8sIUZRgC3eM5dUhL4pidx8kiBvkqbDZc90C+Oclj52EEnKiA96
6BXSVAFaXU9+A9Q/EKXCqeJjLZX4GXbG8oe4n1uGePiS6hxpbHt3nhxvdOjDFYgc
69jlVkKY1M0mG1JfVKl/eYn/HYHs9a84BI1Lra4zmdmSl55/kD1Q1OFCkBi8rZQ0
5FFumJMQ1AVrQ6oOvIPM
=YQGC
-----END PGP SIGNATURE-----
Merge tag 'omap-fixes-against-v3.18-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Merge "omap fixes against v3.18-rc4" from Tony Lindgren:
Few omap fixes for hangs and wrong pinctrl defines, and update
MAINTAINERS file to avoid missing PMIC and SoC related patches:
- Fix random hangs on am437x because of incorrect default
value for the DDR regulator
- Fix wrong partition name for NAND on am335x-evm
- Fix wrong pinctrl defines for dra7xx
- Update maintainers entries for PMICs and SoCs
* tag 'omap-fixes-against-v3.18-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
pinctrl: dra: dt-bindings: Fix output pull up/down
MAINTAINERS: Update entry for omap related .dts files to cover new SoCs
MAINTAINERS: add more files under OMAP SUPPORT
ARM: dts: AM437x-SK-EVM: Fix DCDC3 voltage
ARM: dts: AM437x-GP-EVM: Fix DCDC3 voltage
ARM: dts: AM43x-EPOS-EVM: Fix DCDC3 voltage
ARM: dts: am335x-evm: Fix 5th NAND partition's name
Signed-off-by: Olof Johansson <olof@lixom.net>
- Armada XP
- Generalize i2c quirk
- orion
- Fix irq storm caused by specific sequence of request_irq
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJUVVu8AAoJEP45WPkGe8Zn31YQAJUE6cuk/brSae4s8tjIKWYP
N45wwa2WSMOUscYIThlrfWn9M+KASU/X6dq/y9m7cJZs8mz87qpLV65zMZwnS44x
clQ5gCE6ntGvnnRDQkidQ524/eKVbcJCUtZFRb9I/wqITvev/puhabLLLbs+5SL5
5rqZsY831N5E0B2/eF9j+knUlzQoaK0xjMA3MAULC/KA1qb7p4vjwdl8SP/V4iqa
GC7FERy7dFvGvBiL2FqnrCoFsdzltfIhE5C+XUj7BKdvZSYPaO0eP+UoXDmL7FMv
EVqDcCtSG2Mp2+fSPWAChZoHO11Lo6zjX3HzCgLXyaNIpBD4BoaJO8W0oyiBkzYj
OQX0Wm7WDzcOQlueRA5AKihSHOu28LQ+De7ashneRv5ZPkBzmr5Kgjg9C/+WbguS
JpCfhBDwPizbri4LcJnBb6x8BSnEdIfYbqW/DIpmLbN7I/rb2dH+AeNwPgJfQPCz
GUrU/foPnDSgo3C2fQq/5/1GxnnzHQwQUJNjI6Kb92GeFdurteSJyvRkalsbiuXN
MljwnVZCNuggcloqYLD5MLzEa3I5PIlg1f7TfgfKd8yVvJ5jXfDgwD0k1Bxy6DhY
ZiXXjTCVsr+a1P02LV5HtMGG6hd7iJx3aaABBWNaMypS5qtuiH5m7rJ7MG2Mtpbq
6D6Kh+7DVw0EfKGUJPPv
=JCsp
-----END PGP SIGNATURE-----
Merge tag 'mvebu-fixes-3.18' of git://git.infradead.org/linux-mvebu into fixes
Merge "mvebu fixes for v3.18" from Jason Cooper:
- Armada XP
- Generalize i2c quirk
- orion
- Fix irq storm caused by specific sequence of request_irq
* tag 'mvebu-fixes-3.18' of git://git.infradead.org/linux-mvebu:
ARM: orion: Fix for certain sequence of request_irq can cause irq storm
ARM: mvebu: armada xp: Generalize use of i2c quirk
The sun6i SMP ops are currently not marked as static, as reported by
sparse. Let's mark it as such.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Pull ARM fixes from Russell King:
"Two fixes this time, one to ensure that the kuser helper option
depends on MMU as they aren't available for noMMU targets (and if the
option is selected, we end up oopsing.)
The second fix plugs a corner case with the decompressor, ensuring
that the instruction stream can see the relocated code in every case
on ARMv7 CPUs"
* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: 8198/1: make kuser helpers depend on MMU
ARM: 8191/1: decompressor: ensure I-side picks up relocated code
This enables user space access to the 3 PWM available on the Radxa Rock headers.
Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This updates platform data related to Si4713, which
has been updated to be compatible with DT interface.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
In order to have subsytem agnostic media bus format definitions we've
moved media bus definition to include/uapi/linux/media-bus-format.h and
prefixed values with MEDIA_BUS_FMT instead of V4L2_MBUS_FMT.
Reference new definitions in all platform drivers.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
The clock nodes for DSS VIDEO1/2 and HDMI have wrong register addresses.
This patch fixes the addresses so that they point to
CM_CLKSEL_VIDEO1_PLL_SYS, CM_CLKSEL_VIDEO2_PLL_SYS and
CM_CLKSEL_HDMI_PLL_SYS.
Reported-by: Somnath Mukherjee <somnath@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Most of the patches are clock-related. The DPLL implementation is
changed to better align to the common clock framework.
There is also a patch that removes a few lines from the hwmod code -
this patch should have no functional effect.
Basic build, boot, and PM test logs for these patches can be found here:
http://www.pwsan.com/omap/testlogs/omap-a-for-v3.19/20141113094101/
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUZTTPAAoJEMePsQ0LvSpLe1UP/1LphSxqomh57oi2VEN0ggon
9NJacfdwfu5Ic9PHtJzHMUC6CUs/SWBuQFbfdO0pWrUnhtvQLx1fjTz6m+2FftjO
2n/vp9Rs1sIHXXBfKuve6NFK2sDmwO3fnCqIXXuolGSQexO4QtOoYH6tPBFZxYMR
FogReNBbq5rbIrpU75Rc9F1ALKRQIXThznVs3A0lpVpoky1PalcZOe957IEhvjsk
jyLzY/PnuB3W9z5efTyOoCpljJSpHypp6a+/1u0QiQcBT9KAVJs6XqDwTt0o4ben
CeBHU3FNgIsbehB6NDo9Zkj34qIEVcJJWzW0tTrXWrds+qBTIL2VrkzvEq3YAH1x
R31hX6jEyknAySAyx5BJX8UddITx7WCf/mU7nZJhs7byGIthMKGmFVzcYbwkMLoP
LK+JW+5eT2vNxE62ixv1A4g1AXmodQIGKpBgzeZ/6aBRbEQZdZ3LJBRkbfa65mpJ
LM5ud4R4cx1eTx+B7KzZ055WPQtn7Pkok+AxiwgtqGHHcK/V+uDor105umaaaPtL
YeU1qM0tsUHJjg85tq7pO18ch7LY9GeWVSX5CLQiIwDlrTMQADiA0Cn5w0mR1pWw
5RFU5cbaTl4FoDjcPDaf8nyXE54MFOoQWNr1bA3ApZFdSZ7STBDS1yBjiV/ao+29
XIcHnETIXipHt0lqgf/2
=tw+W
-----END PGP SIGNATURE-----
Merge tag 'for-v3.19/omap-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.19/soc
Some OMAP clock/hwmod patches for v3.19.
Most of the patches are clock-related. The DPLL implementation is
changed to better align to the common clock framework.
There is also a patch that removes a few lines from the hwmod code -
this patch should have no functional effect.
Basic build, boot, and PM test logs for these patches can be found here:
http://www.pwsan.com/omap/testlogs/omap-a-for-v3.19/20141113094101/
The mt6592-evb is an evaluation board based on the MT6592 SoC.
Signed-off-by: Howard Chen <ibanezchen@gmail.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* A dtsi for boards based on Mediatek MT6592 SoCs
* Compatible string in arch/arm/mach-mediatek/mediatek.c
Signed-off-by: Howard Chen <ibanezchen@gmail.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This allows the "make dtbs" to build the moose and mt8135-evbp1
for MediaTek SoC
Signed-off-by: Joe.C <yingjoe.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
We support more MediaTek SoCs now, update the description.
Signed-off-by: Joe.C <yingjoe.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Conflicts:
drivers/net/ethernet/chelsio/cxgb4vf/sge.c
drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
sge.c was overlapping two changes, one to use the new
__dev_alloc_page() in net-next, and one to use s->fl_pg_order in net.
ixgbe_phy.c was a set of overlapping whitespace changes.
Signed-off-by: David S. Miller <davem@davemloft.net>
Use the global current_stack_pointer to get the value of the stack pointer.
This change supports being able to compile the kernel with both gcc and clang.
Signed-off-by: Behan Webster <behanw@converseincode.com>
Reviewed-by: Mark Charlebois <charlebm@gmail.com>
Reviewed-by: Jan-Simon Möller <dl9pf@gmx.de>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Use the global current_stack_pointer to calculate the end of the stack for
current_pt_regs()
Signed-off-by: Behan Webster <behanw@converseincode.com>
Reviewed-by: Mark Charlebois <charlebm@gmail.com>
Reviewed-by: Jan-Simon Möller <dl9pf@gmx.de>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Using global current_stack_pointer works on both clang and gcc.
current_stack_pointer is an unsigned long and needs to be cast
as a pointer to dereference.
Signed-off-by: Mark Charlebois <charlebm@gmail.com>
Signed-off-by: Behan Webster <behanw@converseincode.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Use the global current_stack_pointer to get the value of the stack pointer.
This change supports being able to compile the kernel with both gcc and clang.
Signed-off-by: Behan Webster <behanw@converseincode.com>
Reviewed-by: Mark Charlebois <charlebm@gmail.com>
Reviewed-by: Jan-Simon Möller <dl9pf@gmx.de>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Use the global current_stack_pointer to get the value of the stack pointer.
This change supports being able to compile the kernel with both gcc and clang.
Signed-off-by: Behan Webster <behanw@converseincode.com>
Reviewed-by: Mark Charlebois <charlebm@gmail.com>
Reviewed-by: Jan-Simon Möller <dl9pf@gmx.de>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Use the global current_stack_pointer to get the value of the stack pointer.
This change supports being able to compile the kernel with both gcc and Clang.
Signed-off-by: Behan Webster <behanw@converseincode.com>
Reviewed-by: Mark Charlebois <charlebm@gmail.com>
Reviewed-by: Jan-Simon Möller <dl9pf@gmx.de>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Define a global named register for current_stack_pointer. The use of this new
variable guarantees that both gcc and clang can access this register in C code.
Signed-off-by: Behan Webster <behanw@converseincode.com>
Reviewed-by: Jan-Simon Möller <dl9pf@gmx.de>
Reviewed-by: Mark Charlebois <charlebm@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The kuser helpers page is not set up on non-MMU systems, so it does
not make sense to allow CONFIG_KUSER_HELPERS to be enabled when
CONFIG_MMU=n. Allowing it to be set on !MMU results in an oops in
set_tls (used in execve and the arm_syscall trap handler):
Unhandled exception: IPSR = 00000005 LR = fffffff1
CPU: 0 PID: 1 Comm: swapper Not tainted 3.18.0-rc1-00041-ga30465a #216
task: 8b838000 ti: 8b82a000 task.ti: 8b82a000
PC is at flush_thread+0x32/0x40
LR is at flush_thread+0x21/0x40
pc : [<8f00157a>] lr : [<8f001569>] psr: 4100000b
sp : 8b82be20 ip : 00000000 fp : 8b83c000
r10: 00000001 r9 : 88018c84 r8 : 8bb85000
r7 : 8b838000 r6 : 00000000 r5 : 8bb77400 r4 : 8b82a000
r3 : ffff0ff0 r2 : 8b82a000 r1 : 00000000 r0 : 88020354
xPSR: 4100000b
CPU: 0 PID: 1 Comm: swapper Not tainted 3.18.0-rc1-00041-ga30465a #216
[<8f002bc1>] (unwind_backtrace) from [<8f002033>] (show_stack+0xb/0xc)
[<8f002033>] (show_stack) from [<8f00265b>] (__invalid_entry+0x4b/0x4c)
As best I can tell this issue existed for the set_tls ARM syscall
before commit fbfb872f5f "ARM: 8148/1: flush TLS and thumbee
register state during exec" consolidated the TLS manipulation code
into the set_tls helper function, but now that we're using it to flush
register state during execve, !MMU users encounter the oops at the
first exec.
Prevent CONFIG_MMU=n configurations from enabling
CONFIG_KUSER_HELPERS.
Fixes: fbfb872f5f (ARM: 8148/1: flush TLS and thumbee register state during exec)
Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
Reported-by: Stefan Agner <stefan@agner.ch>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: stable@vger.kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
To speed up decompression, the decompressor sets up a flat, cacheable
mapping of memory. However, when there is insufficient space to hold
the page tables for this mapping, we don't bother to enable the caches
and subsequently skip all the cache maintenance hooks.
Skipping the cache maintenance before jumping to the relocated code
allows the processor to predict the branch and populate the I-cache
with stale data before the relocation loop has completed (since a
bootloader may have SCTLR.I set, which permits normal, cacheable
instruction fetches regardless of SCTLR.M).
This patch moves the cache maintenance check into the maintenance
routines themselves, allowing the v6/v7 versions to invalidate the
I-cache regardless of the MMU state.
Cc: <stable@vger.kernel.org>
Reported-by: Marc Carino <marc.ceeeee@gmail.com>
Tested-by: Julien Grall <julien.grall@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The Mele M9 / A1000G quad has a blue status led, add support for this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Mele M9 / A1000G quad uses both usb-ports, one goes to an internal
usb wifi card, the other to a build-in usb-hub, so neither need their
OHCI companion controller to be enabled since the are always connected at
USB-2 speeds.
The controller which is attached to the wifi also does not need a vbus
regulator.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This avoids it getting briefly turned off between when the regulator getting
registered and the ahci driver turning it back on, thus avoiding the disk
going into emergency head park mode.
Reported-by: Bruno Prémont <bonbons@linux-vserver.org>
Tested-by: Bruno Prémont <bonbons@linux-vserver.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ml->node and sl->node are currently initialized
by means of INIT_LIST_HEAD(). That initialiation
is followed by a list_add() call.
Looking at what both these functions do we will have:
ml->node.next = &ml->node;
ml->node.prev = &ml->node;
oi->master->master_ports.next.prev = &ml->node;
ml->node.next = &oi->master->master_ports.next;
ml->node.prev = &oi->master->master_ports;
oi->master->master_ports.next = &ml->node;
from this, it's clear that both INIT_LIST_HEAD() calls
are unnecessary and can be safely removed.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Currently, DPLLs are hiding the gory details of switching parent
within set_rate, which confuses the common clock code and is wrong.
Fixed by applying the new determine_rate() and set_rate_and_parent()
functionality to any clock-ops previously using the broken approach.
This patch also removes the broken legacy code.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Expand the support of omap4 per-dpll to provide set_rate_and_parent.
This is required for proper behavior of clk_change_rate with
determine_rate support.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Similarly to OMAP3 noncore DPLL, the implementation of this DPLL clock
type is wrong. This patch adds basic functionality for determine_rate
for this clock type which will be taken into use in the patches following
later.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Currently, DPLL code hides the re-parenting within its internals, which
is wrong. This needs to be exposed to the common clock code via
determine_rate and set_rate_and_parent APIs. This patch adds support
for these, which will be taken into use in the following patches.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
DPLL4 can't be reprogrammed on OMAP3430 ES1.0 due to hardware limitation.
Currently, the code does runtime omap_rev() check to see the chip it is
being executed on, instead, change this to use clk_features flags.
This avoids need for runtime omap_rev() checks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
vddio_sdmmc3 is a vdd_io, and thus should be under the vqmmc-supply
property, not vmmc-supply.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This property was wrong and broke eMMC since commit 52221610d ("mmc:
sdhci: Improve external VDD regulator support"). Align the eMMC
properties to those of other Tegra boards.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
There are general changes pending to make the /aliases/serial* entries
number the serial ports on the system. On Tegra, so far the ports have
been just numbered dynamically as they are configured so that makes them
change.
To avoid this, add specific aliases per board to keep the old numbers.
This allows us to change the numbering by default on future SoCs while
keeping the numbering on existing boards.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Thierry Reding <treding@nvidia.com>
These labels will be used to provide deterministic numbering of consoles
in a later patch.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
[treding@nvidia.com: drop aliases, reword commit message]
Signed-off-by: Thierry Reding <treding@nvidia.com>
First export the clk32k clk.
Then add clk_lookup entries for RTT devices so that rtc-at91sam9 driver
can retrieve and manipulate the slow clk.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Johan Hovold <johan@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Move the (DDR) SDRAM controller headers to include/soc/at91 to remove the
dependency on mach/ headers from the at91-reset driver.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
CONFIG_MACH_SAMA5_DT is useless as the only way to boot on sama5 based boards is
to use device tree.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[nicolas.ferre@atmel.com: adapt on top of cleanup branch]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The CONFIG_ARCH_AT91SAM9G45 config option was removed by ("ARM: at91: remove
at91sam9g45/9m10 legacy board support") so cleanup the use of it.
Reported-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This creates a new SoC bus driver for the ARM Integrator
family core modules to register the SoC bus and provide
sysfs info for the core module. We delete the corresponding
code from the Integrator machine and select this driver to
get a clean result.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This gets rid of the custom LED driver in the Integrator directory
altogether and switches us over to using the syscon LEDs for this.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Integrator debug block is a simple set of registers, make
it a syscon and register the four LEDs on the Integrator/AP
baseboard as syscon LEDs.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Using the augmented reset driver for the Versatile family,
we can move the reset handling for the Integrator out of the
machine. We add a "syscon" attribute to the core module, and
access the syscon registers using this handle. We need to
select SYSCON, POWER, POWER_RESET and POWER_RESET_VERSATILE
in order for the restart functionality to always be
available on all systems (it should not be optional).
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch removes all unused static iomapping from exynos4/5_iodesc
table, and at the same time removes related macros from mach/map.h and
plat/map-s5p.h. All such mappings are present in exynos.c but not
currently there are no users of these mappings, so it is safe to remove
these.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Change the dtsi and dts file, soc initialization code to make
use of DT support clock.
So now in the code we do only need call of_clk_init to initialize
the clocks.
Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Add items in arch/arm/boot/dt/Makefile to compile the dtb
for mach-mmp.
Change the dts and dtsi file to use #include instead of \include\
Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Unit addresses, whilst written in hex, don't contain a 0x prefix.
Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Cubietruck uses different pin for the USB OTG VBUS that
is why we override the one defined in sunxi-common-regulators.dtsi
Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Until now the regulator nodes for powering USB VBUS
existed only for the two host controllers. Now the regulator
is added for USB OTG too.
Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The only place where the time is invalid is when the ACPI_CSTATE_FFH entry
method is not set. Otherwise for all the drivers, the time can be correctly
measured.
Instead of duplicating the CPUIDLE_FLAG_TIME_VALID flag in all the drivers
for all the states, just invert the logic by replacing it by the flag
CPUIDLE_FLAG_TIME_INVALID, hence we can set this flag only for the acpi idle
driver, remove the former flag from all the drivers and invert the logic with
this flag in the different governor.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Evbp1 is a tablet evaluation board based on MT8135 SoC.
Signed-off-by: Joe.C <yingjoe.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Moose is a tablet evalutation board based on MT8127 SoC.
Signed-off-by: Joe.C <yingjoe.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
OMAP wdt driver supports only ti,omap3-wdt compatible. In DRA7 dt
wdt compatible property is defined as ti,omap4-wdt by mistake instead of
ti,omap3-wdt. Correcting the typo.
Fixes: 6e58b8f1da ("ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm board")
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Remove unused function prototype that was left by commit 149c09d3a6
("ARM: AM33xx: remove old clock data and link in new clock init code")
which removed the definition.
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
BeagleBoard-X15 is the next generation Open Source Hardware
BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHz A15
processor. The platform features 2GB DDR3L (w/dual 32bit busses),
eSATA, 3 USB3.0 ports, integrated HDMI (1920x1080@60), separate LCD
port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G
Ethernet.
For more information, refer to:
BeagleBoard-X15 Wiki:
http://www.elinux.org/Beagleboard:BeagleBoard-X15
AM5728 is part of the Sitara product family whose additional details
will be available: http://www.ti.com/lsds/ti/arm/overview.page
Technical Reference Manual for AM5728 is public domain at:
http://www.ti.com/lit/spruhz6
Just add basic support for the moment, the following updates are needed:
i) Ethernet - depends on SoC dts fixes
ii) USB Client (USB2) - depends on GPIO extcon
ii) HDMI - additional driver fixes pending
iii) Audio - additional driver fixes pending
NOTE:
AM5728 Data Manual (SPRS915L - August 2014) section 4.1.1 states: "All
unused power supply balls must be supplied with the voltages specified
in the Section 5.2, Recommended Operating Conditions". This implies
that all unused voltage rails for AM5728 can never be switched off even
if the hardware blocks inside that voltage domain is unused. Switching
off these unused rails may result in stability issues on other domains
and increased leakage and power-on-hour impacts.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add btwilink device for IGEPv2 Rev. F and IGEP COM MODULE Rev. G.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can't suppose that the i2c2 pins are configured as I2C bus, these pins are
connected to expansion connectors.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for the new hardware revision of the IGEPv2. Basically, the new
revision F replaces the old Wifi module for a Wilink8 based module.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use the omap3-igep0020-common.dtsi file and remove repeated parts leaving
the nodes that are not common between IGEPv2 hardware revisions.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for the new hardware revision of the IGEP COM MODULE. Basically,
the new revision G replaces the old Wifi module for a Wilink8 based module.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
