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ARM: meson: DTS: enable L2 cache

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This enables the L2 cache controller available in Amlogic SoCs.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
This commit is contained in:
Beniamino Galvani 2014-11-18 15:30:35 +01:00 committed by Carlo Caione
parent aeff05a39a
commit 550ab390d7
3 changed files with 13 additions and 0 deletions
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7
arch/arm/boot/dts/meson.dtsi
View File

@ -50,6 +50,13 @@
/ {
interrupt-parent = <&gic>;
L2: l2-cache-controller@c4200000 {
compatible = "arm,pl310-cache";
reg = <0xc4200000 0x1000>;
cache-unified;
cache-level = <2>;
};
gic: interrupt-controller@c4301000 {
compatible = "arm,cortex-a9-gic";
reg = <0xc4301000 0x1000>,

2
arch/arm/boot/dts/meson6.dtsi
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@ -60,12 +60,14 @@ cpus {
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x200>;
};
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x201>;
};
};

4
arch/arm/boot/dts/meson8.dtsi
View File

@ -58,24 +58,28 @@ cpus {
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x200>;
};
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x201>;
};
cpu@202 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x202>;
};
cpu@203 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x203>;
};
};