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ARM: imx: add enet init for i.mx6sx
Add enet init for i.mx6sx: - Add phy ar8031 fixup - Set enet clock source from internal PLL Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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@ -8,12 +8,62 @@
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#include <linux/irqchip.h>
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#include <linux/of_platform.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "common.h"
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#include "cpuidle.h"
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static int ar8031_phy_fixup(struct phy_device *dev)
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{
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u16 val;
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/* Set RGMII IO voltage to 1.8V */
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phy_write(dev, 0x1d, 0x1f);
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phy_write(dev, 0x1e, 0x8);
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/* introduce tx clock delay */
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phy_write(dev, 0x1d, 0x5);
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val = phy_read(dev, 0x1e);
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val |= 0x0100;
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phy_write(dev, 0x1e, val);
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return 0;
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}
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#define PHY_ID_AR8031 0x004dd074
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static void __init imx6sx_enet_phy_init(void)
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{
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if (IS_BUILTIN(CONFIG_PHYLIB))
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phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
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ar8031_phy_fixup);
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}
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static void __init imx6sx_enet_clk_sel(void)
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{
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struct regmap *gpr;
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gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
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if (!IS_ERR(gpr)) {
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regmap_update_bits(gpr, IOMUXC_GPR1,
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IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);
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regmap_update_bits(gpr, IOMUXC_GPR1,
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IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);
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} else {
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pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
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}
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}
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static inline void imx6sx_enet_init(void)
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{
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imx6sx_enet_phy_init();
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imx6sx_enet_clk_sel();
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}
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static void __init imx6sx_init_machine(void)
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{
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struct device *parent;
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@ -26,6 +76,7 @@ static void __init imx6sx_init_machine(void)
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of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
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imx6sx_enet_init();
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imx_anatop_init();
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imx6sx_pm_init();
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}
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