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STi DT updates for v3.19, round 2.

Browse Source 
Highlights:
 -----------
  - Refactor STiH407 SoC and board to add STiH410 SoC support
  - Add USB support to STiH416 SoC
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Merge tag 'sti-dt-for-v3.19-2' of git://git.stlinux.com/devel/kernel/linux-sti into next/dt

Pull "STi DT updates for v3.19, round 2" from Maxime Coquelin:

Highlights:
-----------
 - Refactor STiH407 SoC and board to add STiH410 SoC support
 - Add USB support to STiH416 SoC

* tag 'sti-dt-for-v3.19-2' of git://git.stlinux.com/devel/kernel/linux-sti:
  ARM: STi: DT: STiH416: Change miphy356 node name to phy@fe382000
  ARM: STi: DT: STih407: STih410: Add clk_ignore_unused to kernel bootargs
  ARM: STi: DT: STiH410: Add STiH410 SoC and b2120 board support.
  ARM: STi: DT: STih407: Abstract common dt nodes into shared files.
  ARM: STi: DT: STiH410: Add pinctl config for usb controllers.
  ARM: STi: DT: STiH410: Add defines for STiH410 DT clocks
  ARM: STi: DT: STiH416: Add DT nodes for the ehci and ohci usb controllers.
  ARM: STi: DT: STiH416: Add DT node for the stih415/6 usb2 phy
  ARM: STi: DT: STiH416: Add pinctl setup for usb controllers.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2014-11-20 17:36:23 +01:00
commit ec498f8e51
13 changed files with 670 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/Makefile
View File

@ -420,6 +420,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear320-hmi.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
stih410-b2120.dtb \
stih415-b2000.dtb \
stih415-b2020.dtb \
stih416-b2000.dtb \

55
arch/arm/boot/dts/stih407-b2120.dts
View File

@ -7,13 +7,15 @@
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "stih407.dtsi"
#include "stih407-clock.dtsi"
#include "stih407-family.dtsi"
#include "stihxxx-b2120.dtsi"
/ {
model = "STiH407 B2120";
compatible = "st,stih407-b2120", "st,stih407";
chosen {
bootargs = "console=ttyAS0,115200";
bootargs = "console=ttyAS0,115200 clk_ignore_unused";
linux,stdout-path = &sbc_serial0;
};
@ -26,53 +28,4 @@ aliases {
ttyAS0 = &sbc_serial0;
};
soc {
sbc_serial0: serial@9530000 {
status = "okay";
};
leds {
compatible = "gpio-leds";
red {
#gpio-cells = <2>;
label = "Front Panel LED";
gpios = <&pio4 1 0>;
linux,default-trigger = "heartbeat";
};
green {
#gpio-cells = <2>;
gpios = <&pio1 3 0>;
default-state = "off";
};
};
i2c@9842000 {
status = "okay";
};
i2c@9843000 {
status = "okay";
};
i2c@9844000 {
status = "okay";
};
i2c@9845000 {
status = "okay";
};
i2c@9540000 {
status = "okay";
};
/* SSC11 to HDMI */
i2c@9541000 {
status = "okay";
/* HDMI V1.3a supports Standard mode only */
clock-frequency = <100000>;
st,i2c-min-scl-pulse-width-us = <0>;
st,i2c-min-sda-pulse-width-us = <5>;
};
};
};

1
arch/arm/boot/dts/stih407.dtsi → arch/arm/boot/dts/stih407-family.dtsi
View File

@ -6,7 +6,6 @@
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include "stih407-clock.dtsi"
#include "stih407-pinctrl.dtsi"
#include <dt-bindings/reset-controller/stih407-resets.h>
/ {

29
arch/arm/boot/dts/stih410-b2120.dts Normal file
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@ -0,0 +1,29 @@
/*
* Copyright (C) 2014 STMicroelectronics (R&D) Limited.
* Author: Peter Griffin <peter.griffin@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "stih410.dtsi"
#include "stihxxx-b2120.dtsi"
/ {
model = "STiH410 B2120";
compatible = "st,stih410-b2120", "st,stih410";
chosen {
bootargs = "console=ttyAS0,115200 clk_ignore_unused";
linux,stdout-path = &sbc_serial0;
};
memory {
device_type = "memory";
reg = <0x40000000 0x80000000>;
};
aliases {
ttyAS0 = &sbc_serial0;
};
};

338
arch/arm/boot/dts/stih410-clock.dtsi Normal file
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@ -0,0 +1,338 @@
/*
* Copyright (C) 2014 STMicroelectronics R&D Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/clock/stih410-clks.h>
/ {
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "st,stih410-clk", "simple-bus";
/*
* Fixed 30MHz oscillator inputs to SoC
*/
clk_sysin: clk-sysin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <30000000>;
clock-output-names = "CLK_SYSIN";
};
/*
* ARM Peripheral clock for timers
*/
arm_periph_clk: clk-m-a9-periphs {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
};
/*
* A9 PLL.
*/
clockgen-a9@92b0000 {
compatible = "st,clkgen-c32";
reg = <0x92b0000 0xffff>;
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clockgen-a9-pll-odf";
};
};
/*
* ARM CPU related clocks.
*/
clk_m_a9: clk-m-a9@92b0000 {
#clock-cells = <0>;
compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
reg = <0x92b0000 0x10000>;
clocks = <&clockgen_a9_pll 0>,
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
};
/*
* ARM Peripheral clock for timers
*/
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_s_c0_flexgen 13>;
clock-output-names = "clk-m-a9-ext2f-div2";
clock-div = <2>;
clock-mult = <1>;
};
/*
* Bootloader initialized system infrastructure clock for
* serial devices.
*/
clk_ext2f_a9: clockgen-c0@13 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
clock-output-names = "clk-s-icn-reg-0";
};
clockgen-a@090ff000 {
compatible = "st,clkgen-c32";
reg = <0x90ff000 0x1000>;
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-pll-ofd-0";
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
compatible = "st,flexgen";
#clock-cells = <1>;
clocks = <&clk_s_a0_pll 0>,
<&clk_sysin>;
clock-output-names = "clk-ic-lmi0",
"clk-ic-lmi1";
};
};
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-C", "st,quadfs";
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
clock-output-names = "clk-s-c0-fs0-ch0",
"clk-s-c0-fs0-ch1",
"clk-s-c0-fs0-ch2",
"clk-s-c0-fs0-ch3";
};
clk_s_c0: clockgen-c@09103000 {
compatible = "st,clkgen-c32";
reg = <0x9103000 0x1000>;
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-c0-pll0-odf-0";
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen";
clocks = <&clk_s_c0_pll0 0>,
<&clk_s_c0_pll1 0>,
<&clk_s_c0_quadfs 0>,
<&clk_s_c0_quadfs 1>,
<&clk_s_c0_quadfs 2>,
<&clk_s_c0_quadfs 3>,
<&clk_sysin>;
clock-output-names = "clk-icn-gpu",
"clk-fdma",
"clk-nand",
"clk-hva",
"clk-proc-stfe",
"clk-proc-tp",
"clk-rx-icn-dmu",
"clk-rx-icn-hva",
"clk-icn-cpu",
"clk-tx-icn-dmu",
"clk-mmc-0",
"clk-mmc-1",
"clk-jpegdec",
"clk-ext2fa9",
"clk-ic-bdisp-0",
"clk-ic-bdisp-1",
"clk-pp-dmu",
"clk-vid-dmu",
"clk-dss-lpc",
"clk-st231-aud-0",
"clk-st231-gp-1",
"clk-st231-dmu",
"clk-icn-lmi",
"clk-tx-icn-disp-1",
"clk-icn-sbc",
"clk-stfe-frc2",
"clk-eth-phy",
"clk-eth-ref-phyclk",
"clk-flash-promip",
"clk-main-disp",
"clk-aux-disp",
"clk-compo-dvp",
"clk-tx-icn-hades",
"clk-rx-icn-hades",
"clk-icn-reg-16",
"clk-pp-hades",
"clk-clust-hades",
"clk-hwpe-hades",
"clk-fc-hades";
};
};
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
clock-output-names = "clk-s-d0-fs0-ch0",
"clk-s-d0-fs0-ch1",
"clk-s-d0-fs0-ch2",
"clk-s-d0-fs0-ch3";
};
clockgen-d0@09104000 {
compatible = "st,clkgen-c32";
reg = <0x9104000 0x1000>;
clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen";
clocks = <&clk_s_d0_quadfs 0>,
<&clk_s_d0_quadfs 1>,
<&clk_s_d0_quadfs 2>,
<&clk_s_d0_quadfs 3>,
<&clk_sysin>;
clock-output-names = "clk-pcm-0",
"clk-pcm-1",
"clk-pcm-2",
"clk-spdiff",
"clk-pcmr10-master",
"clk-usb2-phy";
};
};
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
clock-output-names = "clk-s-d2-fs0-ch0",
"clk-s-d2-fs0-ch1",
"clk-s-d2-fs0-ch2",
"clk-s-d2-fs0-ch3";
};
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
clockgen-d2@x9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
clk_s_d2_flexgen: clk-s-d2-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen";
clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
<&clk_s_d2_quadfs 2>,
<&clk_s_d2_quadfs 3>,
<&clk_sysin>,
<&clk_sysin>,
<&clk_tmdsout_hdmi>;
clock-output-names = "clk-pix-main-disp",
"clk-pix-pip",
"clk-pix-gdp1",
"clk-pix-gdp2",
"clk-pix-gdp3",
"clk-pix-gdp4",
"clk-pix-aux-disp",
"clk-denc",
"clk-pix-hddac",
"clk-hddac",
"clk-sddac",
"clk-pix-dvo",
"clk-dvo",
"clk-pix-hdmi",
"clk-tmds-hdmi",
"clk-ref-hdmiphy";
};
};
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
clock-output-names = "clk-s-d3-fs0-ch0",
"clk-s-d3-fs0-ch1",
"clk-s-d3-fs0-ch2",
"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
compatible = "st,clkgen-c32";
reg = <0x9107000 0x1000>;
clk_s_d3_flexgen: clk-s-d3-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen";
clocks = <&clk_s_d3_quadfs 0>,
<&clk_s_d3_quadfs 1>,
<&clk_s_d3_quadfs 2>,
<&clk_s_d3_quadfs 3>,
<&clk_sysin>;
clock-output-names = "clk-stfe-frc1",
"clk-tsout-0",
"clk-tsout-1",
"clk-mchi",
"clk-vsens-compo",
"clk-frc1-remote",
"clk-lpc-0",
"clk-lpc-1";
};
};
};
};

34
arch/arm/boot/dts/stih410-pinctrl.dtsi Normal file
View File

@ -0,0 +1,34 @@
/*
* Copyright (C) 2014 STMicroelectronics Limited.
* Author: Peter Griffin <peter.griffin@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include "st-pincfg.h"
/ {
soc {
pin-controller-rear {
usb0 {
pinctrl_usb0: usb2-0 {
st,pins {
usb-oc-detect = <&pio35 0 ALT1 IN>;
usb-pwr-enable = <&pio35 1 ALT1 OUT>;
};
};
};
usb1 {
pinctrl_usb1: usb2-1 {
st,pins {
usb-oc-detect = <&pio35 2 ALT1 IN>;
usb-pwr-enable = <&pio35 3 ALT1 OUT>;
};
};
};
};
};
};

14
arch/arm/boot/dts/stih410.dtsi Normal file
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@ -0,0 +1,14 @@
/*
* Copyright (C) 2014 STMicroelectronics Limited.
* Author: Peter Griffin <peter.griffin@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include "stih410-clock.dtsi"
#include "stih407-family.dtsi"
#include "stih410-pinctrl.dtsi"
/ {
};

2
arch/arm/boot/dts/stih416-b2020.dts
View File

@ -20,7 +20,7 @@ mmc1: sdhci@fe81f000 {
non-removable;
};
miphy365x_phy: miphy365x@fe382000 {
miphy365x_phy: phy@fe382000 {
phy_port0: port@fe382000 {
st,sata-gen = <3>;
};

2
arch/arm/boot/dts/stih416-b2020e.dts
View File

@ -38,7 +38,7 @@ mmc1: sdhci@fe81f000 {
non-removable;
};
miphy365x_phy: miphy365x@fe382000 {
miphy365x_phy: phy@fe382000 {
phy_port0: port@fe382000 {
st,sata-gen = <3>;
};

34
arch/arm/boot/dts/stih416-pinctrl.dtsi
View File

@ -147,6 +147,15 @@ st,pins {
};
};
usb {
pinctrl_usb3: usb3 {
st,pins {
oc-detect = <&pio40 0 ALT1 IN>;
pwr-enable = <&pio40 1 ALT1 OUT>;
};
};
};
sbc_i2c1 {
pinctrl_sbc_i2c1_default: sbc_i2c1-default {
st,pins {
@ -318,6 +327,16 @@ st,pins {
};
};
usb {
pinctrl_usb0: usb0 {
st,pins {
oc-detect = <&pio9 4 ALT1 IN>;
pwr-enable = <&pio9 5 ALT1 OUT>;
};
};
};
i2c1 {
pinctrl_i2c1_default: i2c1-default {
st,pins {
@ -506,6 +525,21 @@ st,pins {
};
};
};
usb {
pinctrl_usb1: usb1 {
st,pins {
oc-detect = <&pio18 0 ALT1 IN>;
pwr-enable = <&pio18 1 ALT1 OUT>;
};
};
pinctrl_usb2: usb2 {
st,pins {
oc-detect = <&pio18 2 ALT1 IN>;
pwr-enable = <&pio18 3 ALT1 OUT>;
};
};
};
};
pin-controller-fvdp-fe {

131
arch/arm/boot/dts/stih416.dtsi
View File

@ -281,7 +281,7 @@ mmc1: sdhci@fe81f000 {
clocks = <&clk_s_a1_ls 8>;
};
miphy365x_phy: miphy365x@fe382000 {
miphy365x_phy: phy@fe382000 {
compatible = "st,miphy365x-phy";
st,syscfg = <&syscfg_rear>;
#address-cells = <1>;
@ -316,5 +316,134 @@ sata0: sata@fe380000 {
status = "disabled";
};
usb2_phy: phy@0 {
compatible = "st,stih416-usb-phy";
#phy-cells = <0>;
st,syscfg = <&syscfg_rear>;
clocks = <&clk_sysin>;
clock-names = "osc_phy";
};
ehci0: usb@fe1ffe00 {
compatible = "st,st-ehci-300x";
reg = <0xfe1ffe00 0x100>;
interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
resets = <&powerdown STIH416_USB0_POWERDOWN>,
<&softreset STIH416_USB0_SOFTRESET>;
reset-names = "power", "softreset";
};
ohci0: usb@fe1ffc00 {
compatible = "st,st-ohci-300x";
reg = <0xfe1ffc00 0x100>;
interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
status = "okay";
resets = <&powerdown STIH416_USB0_POWERDOWN>,
<&softreset STIH416_USB0_SOFTRESET>;
reset-names = "power", "softreset";
};
ehci1: usb@fe203e00 {
compatible = "st,st-ehci-300x";
reg = <0xfe203e00 0x100>;
interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
resets = <&powerdown STIH416_USB1_POWERDOWN>,
<&softreset STIH416_USB1_SOFTRESET>;
reset-names = "power", "softreset";
};
ohci1: usb@fe203c00 {
compatible = "st,st-ohci-300x";
reg = <0xfe203c00 0x100>;
interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
resets = <&powerdown STIH416_USB1_POWERDOWN>,
<&softreset STIH416_USB1_SOFTRESET>;
reset-names = "power", "softreset";
};
ehci2: usb@fe303e00 {
compatible = "st,st-ehci-300x";
reg = <0xfe303e00 0x100>;
interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
resets = <&powerdown STIH416_USB2_POWERDOWN>,
<&softreset STIH416_USB2_SOFTRESET>;
reset-names = "power", "softreset";
};
ohci2: usb@fe303c00 {
compatible = "st,st-ohci-300x";
reg = <0xfe303c00 0x100>;
interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
resets = <&powerdown STIH416_USB2_POWERDOWN>,
<&softreset STIH416_USB2_SOFTRESET>;
reset-names = "power", "softreset";
};
ehci3: usb@fe343e00 {
compatible = "st,st-ehci-300x";
reg = <0xfe343e00 0x100>;
interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
resets = <&powerdown STIH416_USB3_POWERDOWN>,
<&softreset STIH416_USB3_SOFTRESET>;
reset-names = "power", "softreset";
};
ohci3: usb@fe343c00 {
compatible = "st,st-ohci-300x";
reg = <0xfe343c00 0x100>;
interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
clocks = <&clk_s_a1_ls 0>,
<&clockgen_b0 0>;
clock-names = "ic", "clk48";
phys = <&usb2_phy>;
phy-names = "usb";
resets = <&powerdown STIH416_USB3_POWERDOWN>,
<&softreset STIH416_USB3_SOFTRESET>;
reset-names = "power", "softreset";
};
};
};

59
arch/arm/boot/dts/stihxxx-b2120.dtsi Normal file
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/*
* Copyright (C) 2014 STMicroelectronics (R&D) Limited.
* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
soc {
sbc_serial0: serial@9530000 {
status = "okay";
};
leds {
compatible = "gpio-leds";
red {
#gpio-cells = <2>;
label = "Front Panel LED";
gpios = <&pio4 1 0>;
linux,default-trigger = "heartbeat";
};
green {
#gpio-cells = <2>;
gpios = <&pio1 3 0>;
default-state = "off";
};
};
i2c@9842000 {
status = "okay";
};
i2c@9843000 {
status = "okay";
};
i2c@9844000 {
status = "okay";
};
i2c@9845000 {
status = "okay";
};
i2c@9540000 {
status = "okay";
};
/* SSC11 to HDMI */
i2c@9541000 {
status = "okay";
/* HDMI V1.3a supports Standard mode only */
clock-frequency = <100000>;
st,i2c-min-scl-pulse-width-us = <0>;
st,i2c-min-sda-pulse-width-us = <5>;
};
};
};

25
include/dt-bindings/clock/stih410-clks.h Normal file
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/*
* This header provides constants clk index STMicroelectronics
* STiH410 SoC.
*/
#ifndef _DT_BINDINGS_CLK_STIH410
#define _DT_BINDINGS_CLK_STIH410
#include "stih407-clks.h"
/* STiH410 introduces new clock outputs compared to STiH407 */
/* CLOCKGEN C0 */
#define CLK_TX_ICN_HADES 32
#define CLK_RX_ICN_HADES 33
#define CLK_ICN_REG_16 34
#define CLK_PP_HADES 35
#define CLK_CLUST_HADES 36
#define CLK_HWPE_HADES 37
#define CLK_FC_HADES 38
/* CLOCKGEN D0 */
#define CLK_PCMR10_MASTER 4
#define CLK_USB2_PHY 5
#endif