Commit Graph

12368 Commits

Author SHA1 Message Date
Tianci.Yin
e35e2b117f drm/amdgpu: add a generic fb accessing helper function(v3)
add a generic helper function for accessing framebuffer via MMIO

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:31:13 -04:00
Tianci.Yin
45cf454e4c drm/amdgpu: update amdgpu_discovery to handle revision
update amdgpu_discovery to get IP revision.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:31:06 -04:00
Prike Liang
ad7ce43c5e drm/amdgpu/powerplay: implement interface pp_power_profile_mode
implement get_power_profile_mode for getting power profile mode status.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:30:58 -04:00
Alex Deucher
8c32d0438f drm/amdgpu/vcn: fix allocation size in enc ring test
We need to allocate a large enough buffer for the
session info, otherwise the IB test can overwrite
other memory.

- Session info is 128K according to mesa
- Use the same session info for create and destroy

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Tested-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:30:57 -04:00
Alex Deucher
b24c459f9f drm/amdgpu/uvd7: fix allocation size in enc ring test (v2)
We need to allocate a large enough buffer for the
session info, otherwise the IB test can overwrite
other memory.

v2: - session info is 128K according to mesa
    - use the same session info for create and destroy

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Tested-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:30:55 -04:00
Alex Deucher
481bf82c97 drm/amdgpu/uvd6: fix allocation size in enc ring test (v2)
We need to allocate a large enough buffer for the
session info, otherwise the IB test can overwrite
other memory.

v2: - session info is 128K according to mesa
    - use the same session info for create and destroy

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Tested-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:30:52 -04:00
Alex Deucher
6cbeaa8231 drm/amdgpu/display: fix build when CONFIG_DRM_AMD_DC_DSC_SUPPORT=n
Add proper config check.

Reviewed-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:30:46 -04:00
YueHaibing
dd80ad9ba5 drm/amd/display: Make dc_link_detect_helper static
Fix sparse warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:746:6:
 warning: symbol 'dc_link_detect_helper' was not declared. Should it be static?

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:30:34 -04:00
Bhawanpreet Lakha
a825a2124d drm/amd/display: null check pp_smu clock table before using it
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:30:29 -04:00
Bhawanpreet Lakha
c7e06b0d02 drm/amd/display: handle dp is usb-c
This patch adds handling of dp is usb-c, it is not tested but is
needed to support dp over usb-c

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:30:23 -04:00
Bhawanpreet Lakha
e78a312f81 drm/amd/display: use requested_dispclk_khz instead of clk
Use requested_dispclk_khz / 1000 directly

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:30:17 -04:00
Lewis Huang
edcc9a6b80 drm/amd/display: enable smu set dcfclk
[Why]
SMU fixed this issue after version 0x370c00

[How]
enable smu send message to set dcfclk after smu version 0x370c00

Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:30:02 -04:00
joseph gravenor
cd83fa1ea9 drm/amd/display: fix header for RN clk mgr
[why]
Should always MP0_BASE for any register definition from MP per-IP header files.
I belive the reason the linux version of MP1_BASE works is The 0th element of the 0th table
of that is identical to the corrisponding value of MP0_BASE in the renoir offset header file.
The reason we should only use MP0_BASE is There is only one set of per-IP headers MP
that includes all register definitions related to SMU IP block. This IP includes MP0, MP1, MP2
and  an ecryption engine that can be used only by MP0. As a result all register definitions from
MP file should be based only on MP0_BASE data.

[How]
Change MP1_BASE to MP0_BASE

Signed-off-by: joseph gravenor <joseph.gravenor@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:29:52 -04:00
Eric Yang
2ffb174b1d drm/amd/display: add sanity check for clk table from smu
[Why]
Handle the case where we don't get a valid table. Also fixes compiler
warning for variable potentially used before assignment.

[How]
If the entire table has no valid fclk, reject the table and use our own
hard code.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:29:46 -04:00
Michael Strauss
bfbacdae0a drm/amd/display: Fix rn audio playback and video playback speed
[WHY]
dprefclk is improperly read due to incorrect units used.
Causes an audio clock to be improperly set, making audio
non-functional and videos play back too fast

[HOW]
Scale dprefclk value from MHz to KHz (multiply by 1000)
to ensure that dprefclk_khz is in correct units

Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:29:39 -04:00
Bhawanpreet Lakha
1952a21cf3 drm/amd/display: handle "18" case in TruncToValidBPP
Handle 18 DecimalBPP like other cases

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:29:32 -04:00
Dmytro Laktyushkin
dd8d1b49c0 drm/amd/display: update odm mode validation to be in line with policy
Previously 8k30 worked with dsc and odm combine due to a workaround that ran
the formula a second time with dsc support enable should dsc validation fail.
This worked when clocks were low enough for formula to enable odm to lower
voltage, however now broke due to increased clocks.

This change updates the ODM combine policy within the formula to properly
reflect our current policy within DC, only enabling ODM when we have to, as
well as adding a check for viewport width when dsc is enabled.

As a side effect the redundant call to dml when odm is required is now
unnecessary.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:29:23 -04:00
Sung Lee
3794943cb1 drm/amd/display: add dummy functions to smu for Renoir Silicon Diags
[Why]
Previously only dummy functions were added in Diags for FPGA.
On silicon, this would lead to a segmentation fault on silicon diags.

[How]
Check if diags silicon and if so, add dummy functions.

Signed-off-by: Sung Lee <sung.lee@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:29:17 -04:00
Bhawanpreet Lakha
92a5dc2205 drm/amd/display: change PP_SM defs to 8
DPM level is 8 these were incorrect before. Fix them

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:29:10 -04:00
Bhawanpreet Lakha
652651ffee drm/amd/display: update renoir bounding box and res_caps
The values for bounding box and res_caps were incorrect. So
Fix them

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:28:57 -04:00
Bhawanpreet Lakha
f6586223b1 drm/amd/display: update dcn21 hubbub registers
use dcn20 common regs define to share some regs with dcn20

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:28:51 -04:00
Bhawanpreet Lakha
df1fba075d drm/amd/display: add detile buffer size for renoir
Detile buffer size affects dcc caps, it was already added for
dcn2. Now add it for dcn21

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:28:45 -04:00
Dmytro Laktyushkin
234fa04ea2 drm/amd/display: correct dcn21 NUM_VMID to 16
1 vmid limitation only exists for HOSTVM which is a custom
use case anyway.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:28:37 -04:00
Eric Yang
02981b28cd drm/amd/display: use dcn10 version of program tiling on Renoir
[Why]
Renoir is gfx9, same as dcn10, not dcn20.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:28:21 -04:00
Dmytro Laktyushkin
6ba3712d24 drm/amd/display: initialize RN gpuvm context programming function
Renoir can use vm contexes as long as HOSTVM is off so
this should be initialized.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:28:16 -04:00
Lewis Huang
f93e29f083 drm/amd/display: Temporary workaround to toggle watermark setting
[Why]
Watermarks not propagated to DCHUBP after it is powered on

[How]
Add temoprary function apply_DEDCN21_147_wa to apply wm settings for Renoir

Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:28:10 -04:00
Bhawanpreet Lakha
d4516d3ec5 drm/amd/display: fix incorrect page table address for renoir
Incorrect page table address and programming sys aperture for
stutter gather, so fix it.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:28:04 -04:00
Dmytro Laktyushkin
48d92e8eda drm/amd/display: enable hostvm based on roimmu active for dcn2.1
Enabling hostvm when ROIMMU is not active seems to break GPUVM.
This fixes the issue by not enabling hostvm if ROIMMU is not
activated.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:27:58 -04:00
Lewis Huang
15fdbcc51f drm/amd/display: move the bounding box patch before calculate wm
[why]
driver updateis the dcn2_1_soc into dml before call update_bw_bounding_box

[How]
Move the patch function before calculate wm.

Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Signed-off-by: joseph graveno <joseph.gravenor@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:27:53 -04:00
Bhawanpreet Lakha
4de094ee8a drm/amd/display: add REFCYC_PER_TRIP_TO_MEMORY programming
it allows us to do urgent latency programming

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:27:45 -04:00
Bhawanpreet Lakha
91c665bdc1 drm/amd/display: create dcn21_link_encoder files
[Why]
DCN20 and DCN21 have different phy programming sequences.

[How]
Create a separate dcn21_link_encoder for Renoir

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:27:39 -04:00
Bhawanpreet Lakha
c0fb59a4c3 drm/amd/display: Add renoir hw_seq
This change adds renoir hw_seq, needed to do renoir
specific hw programing

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:27:34 -04:00
Bhawanpreet Lakha
5f687972ff drm/amd/display: Add DCN_BASE regs
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:27:27 -04:00
Bhawanpreet Lakha
ce6095267d drm/amd/display: Add DP_DPHY_INTERNAL_CTR regs
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:27:07 -04:00
Roman Li
9c1a91f6f5 drm/amd/display: disable ext aux support for vega
[Why]
Earlier changes to support configurable aux timeout
caused dc init failure on vega due to missing reg defs.
Needs to be disabled until implemented for vega.

[How]
Set extended aux timeout cap for vega to false.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-By: abdoulaye berthe <abdoulaye.berthe@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:25:03 -04:00
abdoulaye berthe
f6040a439f drm/amd/display: configurable aux timeout support
[Description]
1-add configurable timeout support to aux engine.
2-add timeout support field to dc_caps
3-add reg_key to override extended timeout support

Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:24:56 -04:00
abdoulaye berthe
8276dd871f drm/amd/display: update register field access mechanism
1-add timeout length and multiplier fields to aux_control1 register
2-update access mechanism from macro constructed name to uint32_t
defined addresses.
3-define registers and field per asic family

Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:24:34 -04:00
chen gong
64c5cc9367 drm/amdgpu: No need to check gfxoff status after enable gfxoff feature
smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff) Just turn on a switch.

As to when GPU get into "GFXoff" will be up to drawing load.

So we can not sure which state GPU should be in after enable gfxoff
feature.

Signed-off-by: chen gong <curry.gong@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:24:24 -04:00
Kenneth Feng
5441dd0e2c drm/amd/powerplay: bug fix for memory clock request from display
In some cases, display fixes memory clock frequency to a high value
rather than the natural memory clock switching.
When we comes back from s3 resume, the request from display is not reset,
this causes the bug which makes the memory clock goes into a low value.
Then due to the insuffcient memory clock, the screen flicks.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:24:15 -04:00
Prike Liang
f839110157 drm/amdgpu: fix S3 failed as RLC safe mode entry stucked in polloing gfx acq
Fix gfx cgpg setting sequence for RLC deadlock at safe mode entry in polling gfx response.
The patch can fix VCN IB test failed and DAL get dispaly count failed issue.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:24:09 -04:00
Prike Liang
c8486eef2c drm/amdgpu: add GFX_PIPELINE capacity check for updating gfx cgpg
Before disable gfx pipeline power gating need check the flag AMD_PG_SUPPORT_GFX_PIPELINE.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17 16:23:54 -04:00
Ahzo
ed4766022f drm/amd/display: add NULL checks for clock manager pointer
This fixes kernel NULL pointer dereferences on shutdown:
RIP: 0010:build_audio_output.isra.0+0x97/0x110 [amdgpu]
RIP: 0010:enable_link_dp+0x186/0x300 [amdgpu]

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Ahzo <Ahzo@tutanota.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:32 -04:00
Alex Deucher
97c002be41 drm/amdgpu: enable BACO reset for SMU7 based dGPUs (v2)
Use BACO to reset the GPU if supported on SMU7 based
dGPUs.

v2: don't use baco on CI parts

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:32 -04:00
Alex Deucher
2a113c74ec drm/amdgpu/powerplay: wire up BACO to powerplay API for smu7
Wire up the powerplay callbacks for for BACO for smu7 devices.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
912a0bf574 drm/amdgpu/powerplay: split out common smu7 BACO code
Several of the BACO functions are common across smu7-based
asics.  Split the common code out.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
56f68f18e0 drm/amdgpu/powerplay: add support for BACO on CI
This adds BACO support for CI asics.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
da28d1c026 drm/amdgpu/powerplay: add support for BACO on Fiji
This adds BACO support for Fiji asics.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
28e82af499 drm/amdgpu/powerplay: add support for BACO on VegaM
This adds BACO support for VegaM asics.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
1b0575bdc4 drm/amdgpu/powerplay: add support for BACO on polaris
This adds BACO support for Polaris asics.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
f07fb0244f drm/amdgpu/powerplay: add support for BACO on Iceland
This adds BACO support for Iceland asics.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
cefada559b drm/amdgpu/powerplay: add support for BACO on tonga
This adds BACO support for Tonga.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
42e547efe2 drm/amdgpu/powerplay: add core support for pre-SOC15 baco
This adds core support for BACO on pre-vega asics.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
5d934ac0d0 drm/amdgpu: add new SMU 7.1.3 registers for BACO
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
9fc00ea774 drm/amdgpu: add new SMU 7.1.2 registers for BACO
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
c74c524e7c drm/amdgpu: add new SMU 7.0.1 registers for BACO
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
c06a91c0f8 drm/amdgpu: add new BIF 5.0 register for BACO
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
8763eb7ae9 drm/amdgpu: add new BIF 4.1 register for BACO
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
5337aae9b5 drm/amdgpu/soc15: add support for baco reset with swSMU
Add support for vega20 when the swSMU path is used.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:55:31 -04:00
Alex Deucher
31fa2991f4 drm/amdgpu: remove in_baco_reset hack
It was a vega20 specific hack.  Check if we are in reset
and what reset method we are using.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:51:39 -04:00
Alex Deucher
f5fda6d89a drm/amdgpu: simplify ATPX detection
Use the base class rather than the specific class and drop
the second loop.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:51:39 -04:00
Alex Deucher
897483d8a0 drm/amdgpu: move gpu reset out of amdgpu_device_suspend
Move it into the caller.  There are cases were we don't
want it.  We need it for hibernation, but we don't need
it for runtime pm, so drop it for runtime pm.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:51:39 -04:00
Alex Deucher
803cc26d5c drm/amdgpu: move pci_save_state into suspend path
for amdgpu_device_suspend.  This follows the logic
in the resume path.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:51:39 -04:00
Hersen Wu
e70bd049d0 drm/amdgpu/display: fix build error casused by CONFIG_DRM_AMD_DC_DCN2_1
when CONFIG_DRM_AMD_DC_DCN2_1 is not enable in .config,
there is build error. struct dpm_clocks shoud not be
guarded.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:51:25 -04:00
Hersen Wu
71a0df4be6 drm/amdgpu/display: hook renoir dc to pplib funcs
enable dc get dmp clock table and set dcn watermarks
via pplib.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:51:18 -04:00
Andrey Grodzovsky
ed606f8a34 dmr/amdgpu: Fix crash on SRIOV for ERREVENT_ATHUB_INTERRUPT interrupt.
Ignre the ERREVENT_ATHUB_INTERRUPT for systems without RAS.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-and-tested-by: Jack Zhang <Jack.Zhang1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:51:11 -04:00
Philip Yang
06f7f57e87 drm/amdgpu: user pages array memory leak fix
user_pages array should always be freed after validation regardless if
user pages are changed after bo is created because with HMM change parse
bo always allocate user pages array to get user pages for userptr bo.

v2: remove unused local variable and amend commit

v3: add back get user pages in gem_userptr_ioctl, to detect application
bug where an userptr VMA is not ananymous memory and reject it.

Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Tested-by: Joe Barnett <thejoe@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:51:01 -04:00
Hersen Wu
7bbdbe4059 drm/amdgpu/powerplay: add renoir funcs to support dc
there are two paths for renoir dc access smu.
one dc access smu directly using bios smc
interface: set disply, dprefclk, etc.
another goes through pplib for get dpm clock
table and set watermmark.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:50:55 -04:00
Evan Quan
5bcc92407c drm/amd/powerplay: enable Arcturus runtime VCN dpm on/off
Enable runtime VCN DPM on/off on Arcturus.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:50:43 -04:00
Kenneth Feng
372120f0a5 drm/amd/powerplay: bug fix for pcie parameters override
Bug fix for pcie paramerers override on swsmu.
Below is a scenario to have this problem.
pptable definition on pcie dpm:
0 -> pcie gen speed:1, pcie lanes: *16
1 -> pcie gen speed:4, pcie lanes: *16
Then if we have a system only have the capbility:
pcie gen speed: 3, pcie lanes: *8,
we will override dpm 1 to pcie gen speed 3, pcie lanes *8.
But the code skips the dpm 0 configuration.
So the real pcie dpm parameters are:
0 -> pcie gen speed:1, pcie lanes: *16
1 -> pcie gen speed:3, pcie lanes: *8
Then the wrong pcie lanes will be toggled.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:50:37 -04:00
Emily Deng
bcccee89f4 drm/amdgpu: Fix tdr3 could hang with slow compute issue
When index is 1, need to set compute ring timeout for sriov and passthrough.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:50:23 -04:00
Christian König
b2c18f0a9c drm/amdgpu: fix potential VM faults
When we allocate new page tables under memory
pressure we should not evict old ones.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:50:18 -04:00
Christian König
b146570010 drm/amdgpu: fix error handling in amdgpu_bo_list_create
We need to drop normal and userptr BOs separately.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:50:07 -04:00
Dennis Li
820924745b drm/amdgpu: add RAS support for VML2 and ATCL2
v1: Add codes to query the EDC count of VML2 & ATCL2
v2: Rename VML2/ATCL2 registers and drop their mask define
v3: Add back the ECC mask for VML2 registers

Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:49:57 -04:00
Dennis Li
87d92e1f90 drm/amd/include: add register define for VML2 and ATCL2
Add VML2 and ATCL2 ECC registers to support VEGA20 RAS

Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:49:51 -04:00
Dennis Li
13ba03442a drm/amdgpu: change to query the actual EDC counter
For the potential request in the future, change to
query the actual EDC counter.

Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:49:44 -04:00
Le Ma
c0cff9e43e drm/amd/powerplay: add BACO platformCaps for VEGA20
BACO reset is needed for RAS recovery.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:49:36 -04:00
Le Ma
16562d32c7 drm/amd/powerplay: send EnterBaco msg with argument as RAS recovery flag
1 indicates RAS recovery flag in SMU FW.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:49:29 -04:00
Le Ma
df9331e561 drm/amd/powerplay: avoid disabling ECC if RAS is enabled for VEGA20
Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when
BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting
for ECC supported SKU.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:49:22 -04:00
Le Ma
956f670509 drm/amdgpu/soc15: disable doorbell interrupt as part of BACO entry sequence
Workaround to make RAS recovery work in BACO reset.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:49:14 -04:00
Hans de Goede
402c60d7b0 drm/amdgpu: Bail earlier when amdgpu.cik_/si_support is not set to 1
Bail from the pci_driver probe function instead of from the drm_driver
load function.

This avoid /dev/dri/card0 temporarily getting registered and then
unregistered again, sending unwanted add / remove udev events to
userspace.

Specifically this avoids triggering the (userspace) bug fixed by this
plymouth merge-request:
https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/59

Note that despite that being a userspace bug, not sending unnecessary
udev events is a good idea in general.

BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1490490
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:49:07 -04:00
Alex Deucher
44e149bb1e drm/amdgpu/display: clean up dcn2*_pp_smu functions
Use the dcn21 functions in dcn21_resource.c and make the
dcn20 functions static since they are only used in
dcn20_resource now.

Cc: bhawanpreet.lakha@amd.com
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:49:01 -04:00
Xiaojie Yuan
bb3d7d322d drm/amd/powerplay: re-enable FW_DSTATE feature bit
SMU firmware has fix the bug, so remove this workaround.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:48:55 -04:00
Xiaojie Yuan
5f6a556f98 drm/amdgpu/discovery: reserve discovery data at the top of VRAM
IP Discovery data is TMR fenced by the latest PSP BL,
so we need to reserve this region.

Tested on navi10/12/14 with VBIOS integrated with latest PSP BL.

v2: use DISCOVERY_TMR_SIZE macro as bo size
    use amdgpu_bo_create_kernel_at() to allocate bo

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:48:46 -04:00
Kevin Wang
4e71e08592 drm/amdgpu/swSMU: custom UMD pstate peak clock for navi14
add navi14 umd pstate peak clock support.

NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK   1670 MHz
NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK  1448 MHz
NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK  1181 MHz
NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK  1717 MHz
NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK   1448 MHz

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:48:37 -04:00
Evan Quan
7e899409fd drm/amd/powerplay: enable df cstate control on swSMU routine
Currently this is only supported on Vega20 with 40.50 and later
SMC firmware.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:48:29 -04:00
Evan Quan
06615f9a0c drm/amd/powerplay: enable df cstate control on powerplay routine
Currently this is only supported on Vega20 with 40.50 and later
SMC firmware.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15 15:48:09 -04:00
Alex Deucher
bc7ef86566 drm/amdgpu/swSMU/navi: add feature toggles for more things
Add toggles for more power features.  Helpful in debugging.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:39:07 -05:00
Ville Syrjälä
ff06184a49 drm/amdgpu/powerplay: Use swap() where appropriate
@swap@
identifier TEMP;
expression A,B;
@@
- TEMP = A;
- A = B;
- B = TEMP;
+ swap(A, B);

@@
type T;
identifier swap.TEMP;
@@
(
- T TEMP;
|
- T TEMP = {...};
)
... when != TEMP

Cc: Rex Zhu <rex.zhu@amd.com>
Cc: Evan Quan <evan.quan@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Christian König" <christian.koenig@amd.com>
Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:39:07 -05:00
Ville Syrjälä
34b86b75df drm/amd/display: Use swap() where appropriate
Mostly a cocci-job, but it flat out refused to remove the
declaration in drivers/gpu/drm/amd/display/dc/core/dc.c so
had to do that part manually.

@swap@
identifier TEMP;
expression A,B;
@@
- TEMP = A;
- A = B;
- B = TEMP;
+ swap(A, B);

@@
type T;
identifier swap.TEMP;
@@
(
- T TEMP;
|
- T TEMP = {...};
)
... when != TEMP

Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Christian König" <christian.koenig@amd.com>
Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:39:06 -05:00
chen gong
6696b8adb8 drm/amdgpu: Do not implement power-on for SDMA after do mode2 reset on Renoir
Find that ring sdma0 test failed if turn on SDMA powergating after do
mode2 reset.

Perhaps the mode2 reset does not reset the SDMA PG state, SDMA is
already powered up so there is no need to ask the SMU to power it up
again. So I skip this function for a moment.

Signed-off-by: chen gong <curry.gong@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:39:06 -05:00
Xiaojie Yuan
c1972a56eb drm/amd/powerplay: add more feature bits
Additional features that can be enabled in the SMU.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:39:06 -05:00
Xiaojie Yuan
e8939b4a0d drm/amdgpu/sdma5: fix mask value of POLL_REGMEM packet for pipe sync
sdma will hang once sequence number to be polled reaches 0x1000_0000

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:39:06 -05:00
Alex Deucher
02fc146748 drm/amdgpu/powerplay: fix typo in mvdd table setup
Polaris and vegam use count for the value rather than
level.  This looks like a copy paste typo from when
the code was adapted from previous asics.

I'm not sure that the SMU actually uses this value, so
I don't know that it actually is a bug per se.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=108609
Reported-by: Robert Strube <rstrube@gmail.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:35:41 -05:00
Nirmoy Das
b9ed69e6fd drm/amdgpu: fix memory leak
cleanup error handling code and make sure temporary info array
with the handles are freed by amdgpu_bo_list_put() on
idr_replace()'s failure.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:35:35 -05:00
Tao Zhou
6e4be98767 drm/amdgpu: avoid ras error injection for retired page
check whether a page is bad page before umc error injection, bad page
should not be accessed again

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:35:27 -05:00
Luben Tuikov
4e930d96c9 drm/amdgpu: Use the ALIGN() macro
Use the ALIGN() macro to set "num_dw" to a
multiple of 8, i.e. lower 3 bits cleared.

Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:35:20 -05:00
Alex Deucher
54e9ab2edb drm/amdgpu/ras: document the reboot ras option
We recently added it, but never documented it.

Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:35:18 -05:00
Alex Deucher
a20bfd0fd4 drm/amdgpu/ras: fix typos in documentation
Fix a couple of spelling typos.

Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:35:11 -05:00
Dmytro Laktyushkin
976035dd4f drm/amd/display: add renoir specific watermark range and clk helper
Doing this allows us to split it for diffrent asics. This design will
be helpful for future Asciis.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:35:01 -05:00
Eric Yang
a51894f015 drm/amd/display: hook up notify watermark ranges and get clock table
[Why]
Previously SMU was giving us 0s for the clock table. Now they have valid
clock table. We should use theirs. Also, need to send SMU watermark
ranges for selecting optimal watermarks.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:34:47 -05:00
Sung Lee
a0dd575b7b drm/amd/display: Skip DIG Check if Link is Virtual for Display Count
[WHY]
Without a check for virtual links, every link's DIG was getting
checked for enabled or disabled. If link was virtual, since it
did not have a DIG, this would cause issues.

[HOW]
Skip DIG Enable check if link is virtual and add virtual link to
to display count.

Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:34:41 -05:00
Wayne Lin
4a36fcbaec drm/amd/display: correct stream LTE_340MCSC_SCRAMBLE value
[Why]
HDMI 2.0 requires scrambling under specific conditions. We refer to
stream property LTE_340MCSC_SCRAMBLE to determine whether en/dis
scrambling.
While creating stream for sink, we setup LTE_340MCSC_SCRAMBLE by
referring to edid_caps. However, dm_helpers_parse_edid_caps()
doesn't construct HDMI Forum block data for edid_caps.
Moreover, fill_stream_properties_from_drm_display_mode() aslo
unconsciously clear the LTE_340MCSC_SCRAMBLE flag.

[How]
Drm already provides drm_display_info to refer HDMI Forum vsdb info.
Set stream LTE_340MCSC_SCRAMBLE by drm_display_info and remove
memset in fill_stream_properties_from_drm_display_mode()

Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:34:33 -05:00
David Galiffi
dd998291db drm/amd/display: Fix dongle_caps containing stale information.
[WHY]

During detection:
function: get_active_converter_info populates link->dpcd_caps.dongle_caps
only when dpcd_rev >= DPCD_REV_11 and DWN_STRM_PORTX_TYPE is
DOWN_STREAM_DETAILED_HDMI or DOWN_STREAM_DETAILED_DP_PLUS_PLUS.
Otherwise, it is not cleared, and stale information remains.

During mode validation:
function: dp_active_dongle_validate_timing reads
link->dpcd_caps.dongle_caps->dongle_type to determine the maximum
pixel clock to support. This information is now stale and no longer
valid.

[HOW]
dp_active_dongle_validate_timing should be using
link->dpcd_caps->dongle_type instead.

Signed-off-by: David Galiffi <david.galiffi@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:34:27 -05:00
Jaehyun Chung
8396745da8 drm/amd/display: Add capability check for static ramp calc
[Why]
Static ramp to max refresh rate does not have capability check on
calculated v_total. Programming a lower v_total_min and max than the
total causes continuous spurious HPDs.

[How]
Add a capability check after v_total calculation similar to calculate
v_total helper functions.

Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:34:20 -05:00
Aric Cyr
fc067805ac drm/amd/display: 3.2.54
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:34:13 -05:00
Xiaodong Yan
33fd29007d drm/amd/display: make aux defer delay and aux sw start delay seperate
[why]
1. defer delay and sw start delay has been mixed up, defer delay was
programmed to AUX_SW_CONTROL:AUX_SW_START_DELAY.
2. There's no delay for defer

[how]
1. Set  aux sw start to 0
2. Add delay for defer scenario

Signed-off-by: Xiaodong Yan <Xiaodong.Yan@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:34:06 -05:00
Charlene Liu
ce10a0f39b drm/amd/display: use vbios message to call smu for dpm level
[Description]
use vbios message to call smu for dpm level
also only program dmdata in vsyncflip as HW requirement.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:33:58 -05:00
Leo Li
52883b36f7 drm/amd/display: Fix maybe-uninitialized warning
[Why]

Compiling with GCC 9.1.0 gives the following warning (I have
warnings-as-errors enabled):

drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/core/dc.c: In function 'dc_validate_seamless_boot_timing':
drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/core/dc.c:1180:8: error: 'se' may be used uninitialized in this function [-Werror=maybe-uninitialized]
 1180 |   if (!se->funcs->dp_get_pixel_format(
      |        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 1181 |    se,
      |    ~~~
 1182 |    &hw_crtc_timing.pixel_encoding,
      |    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 1183 |    &hw_crtc_timing.display_color_depth))

[How]

Initialize se to NULL.

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:33:50 -05:00
Martin Leung
93c2340bdc drm/amd/display: add more checks to validate seamless boot timing
[why]
we found using an active DP to HDMI panel that we weren't validating
dp_pixel_format and hardware timing v_front_porch, causing screen to
blank and/or corrupt while attempting a seamless boot.

[how]
added checks during dc_validate_seamless_boot_timing for these values

Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:33:44 -05:00
Vitaly Prosyak
566b4252fe drm/amd/display: add new active dongle to existent w/a
[Why & How]
Dongle 0x00E04C power down all internal circuits including
AUX communication preventing reading DPCD table.
Encoder will skip DP RX power down on disable output
to keep receiver powered all the time.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:33:37 -05:00
Michael Strauss
b356843ee5 drm/amd/display: Update number of dcn21 audio endpoints
[WHY]
Number of audio endpoints wasn't updated from dcn20's 6 when created

[HOW]
Changed num_audio to 4 to match the correct sbios value

Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:33:30 -05:00
Joseph Gravenor
ac81c2a75b drm/amd/display: add guard for SMU ver, for 48mhz clk
[why]
dp_48m_refclk_driver_pwdn is persistent through S3 and S5.
This was worked arround in SMU FW 55.21.0. Earlier FW don't have this fix
so we will hang on reboot

[how]
add a guard for smu versions before SMU FW 55.21.0

Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:33:23 -05:00
Eric Yang
57133a28bc drm/amd/display: fix code to control 48mhz refclk
[Why]
The SMU message to enable this feature looks at argument. Previous code
didn't send right argument. This change will allow the feature to be
be enabled.

[How]
Fixed one issue where SMU message to enable the feature was sent without
setting the parameter.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:33:15 -05:00
Eric Yang
ab4a4072f2 drm/amd/display: exit PSR during detection
[Why]
If 48mhz refclk is turned off during PSR, we will have issue doing
link training during detection.

[How]
Get out of PSR before detection

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:33:07 -05:00
Julian Parkin
edb922b022 drm/amd/display: Program DWB watermarks from correct state
[Why]
When diags adds a DWB via a stream update, we calculate MMHUBBUB
paramaters, but dc->current_state has not yet been updated
when the DWB programming happens. This leads to overflow on
high bandwidth tests since the incorrect MMHUBBUB arbitration
parameters are programmed.

[How]
Pass the updated context down to the (enable|update)_writeback functions
so that they can use the correct watermarks when programming MMHUBBUB.

Signed-off-by: Julian Parkin <julian.parkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:33:00 -05:00
Aric Cyr
1503676caf drm/amd/display: 3.2.53
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:32:54 -05:00
Wesley Chalmers
f432f0060f drm/amd/display: Use dcn1 Optimal Taps Get
[WHY]
dpp2_get_optimal_number_of_taps is incorrect, and dcn2 should be using
dpp1_get_optimal_number_of_taps instead

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:32:46 -05:00
Sivapiriyan Kumarasamy
82db2e3c39 drm/amd/display: fix bug with check for HPD Low in verify link cap
[Why]
There is a bug when determining if link training should be retried when
HPD is low in dp_verify_link_cap_with_retries.

[How]
Correctly, fail dp_verify_link_cap_with_retries without retry when
HPD is low.

Signed-off-by: Sivapiriyan Kumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:32:39 -05:00
Josip Pavic
15caeabc57 drm/amd/display: wait for set pipe mcp command completion
[Why]
When the driver sends a pipe set command to the DMCU FW, it does not wait
for the command to complete. This can lead to unpredictable behavior if,
for example, the driver were to request a pipe disable to the FW via MCP,
then power down some hardware before the firmware has completed processing
the command.

[How]
Wait for the DMCU FW to finish processing set pipe commands

Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:32:32 -05:00
Nikola Cornij
486cc0ee55 drm/amd/display: Add output bitrate to DML calculations
[why]
Output bitrate was mistakenly left out, causing corruption on some
DSC low resolution (such as 800x600) modes.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:32:24 -05:00
Aric Cyr
c59802313e drm/amd/display: Properly round nominal frequency for SPD
[Why]
Some displays rely on the SPD verticle frequency maximum value.
Must round the calculated refresh rate to the nearest integer.

[How]
Round the nominal calculated refresh rate to the nearest whole
integer.

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:32:16 -05:00
Joshua Aberback
62f3abd153 drm/amd/display: Restore should_update_pstate_support after bad revert
[Why]
This function was mistakenly reverted as part of a legitimate revert. The
old version that was reverted to has bad logic, and is causing situations
where p-state change support is being toggled when it shouldn't be,
resulting in hangs.

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:32:10 -05:00
Lewis Huang
f537d474df drm/amd/display: check phy dpalt lane count config
[Why]
Type-c PHY config is not align with dpcd lane count.
When those values didn't match, it cause driver do
link training with 4 lane but phy only can output 2 lane.
The link trainig always fail.

[How]
1. Modify get_max_link_cap function. According DPALT_DP4
to update max lane count.
2. Add dp_mst_verify_link_cap to handle MST case because
we didn't call dp_mst_verify_link_cap for MST case.

Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:32:03 -05:00
Wayne Lin
d832fc3b18 drm/amd/display: build up VSIF infopacket
[Why]
Didn't send VSIF infopacket when it's 4k mode defined in HDMI 1.4b.
For HDMI 1.4b, While displaying 4k modes, it should send VSP.

[How]
Call mod_build_hf_vsif_infopacket() function to build info frame
and send it.

Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:31:56 -05:00
Anthony Koo
f4ce271b6a drm/amd/display: 3.2.52
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:31:49 -05:00
Joshua Aberback
d56eaa7cfb drm/amd/display: Add missing shifts and masks for dpp registers on dcn2
[Why]
The register CM_TEST_DEBUG_DATA is used in dpp1_program_input_csc, which is
called from dpp2_cnv_setup, but the shifts and masks for the fields of that
register are not initialized for dcn2. This causes all reads of that register
to return 0.

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:31:42 -05:00
Jun Lei
deb79818e1 drm/amd/display: add explicit comparator as default optimization check
[why]
memcmp is vulnerable to regression due to dc_clocks structures not being
organized properly (not "current" clock related structures being at the beginning
of the structure) and causes unnecessary setting of the optimize bit

[how]
add a dcn sepcific comparator, implement for dcn2

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:31:35 -05:00
Wayne Lin
3c2381b92c drm/amd/display: add support for VSIP info packet
[Why]
The vendor specific infoframe is needed for HDMI while displaying
specific modes.
DC supports sending it, but we aren't currently building it

[How]
Add mod_build_hf_vsif_infopacket() to build the vendor specific
info packet.

Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:25:22 -05:00
Joseph Gravenor
9ae1b27f31 drm/amd/display: fix hotplug during display off
[why]
HPD is not suppressed when we lower
clocks on renoir. B/c of this we do link
training when the 48mhz refclk is off, which
will cause ASIC hang.

[how]
Exit optimized power state for detection purpose.

Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:25:13 -05:00
Dmytro Laktyushkin
8b8eda0144 drm/amd/display: fix pipe re-assignment when odm present
Currently pipe split may steal an existing ODM pipe depending on stream
sequence. This change prevents that from happening as easily.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Gary Kattan <Gary.Kattan@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:25:06 -05:00
Julian Parkin
377c9d0473 drm/amd/display: Reprogram FMT on pipe change
[Why]
When planes are added or removed from a stream, the change
in pipe usage from dynamic MPC combine can cause a second
stream using ODM combine to pick a different pipe to combine with.

In this scenario, a different OPP is connected to the ODM without
programming its FMT.

[How]
Reprogram the FMT in dcn20_program_pipe whenever a pipe is
newly enabled, or when its opp changes.

Signed-off-by: Julian Parkin <julian.parkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:25:00 -05:00
Aric Cyr
1caba4e83b drm/amd/display: Update V_UPDATE whenever VSTARTUP changes
[Why]
If VSTARTUP changes due to bandwidth requirements, we must
recalculate and update VLINE2 as well for proper flip reporting.

[How]
After all calls to program_global_sync which reconfigures
VSTARTUP, also make sure to update V_UPDATE (i.e. VLINE2 on DCNx).

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:24:53 -05:00
Wyatt Wood
cbc697b2e3 drm/amd/display: Add Logging for Gamma Related information
[Why]
A recent bug showed that logging would be useful in debugging
various gamma issues.

[How]
Fix formatting for easier graphing.
Prevent performance hit when doing diag.

Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:24:46 -05:00
Wenjing Liu
ef5a7d266e drm/amd/display: skip enable stream on disconnected display
[why]
Virtual signal means there is no display attached.
In this case we will assign a virtual signal type to the stream.
We should only enable the front end of the stream but not the back end.

[how]
When stream is enabling with virtual signal type, skip backend programming.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:24:39 -05:00
Wayne Lin
1cb1d47741 drm/amd/display: Correct values in AVI infoframe
[Why]
While displaying 4k modes defined in HDMI1.4b, should set VIC to 0
and use VSP HDMI_VIC to indicate the mode.

[How]
Use functions defined in drm to set up the VIC correspondingly.

Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:24:33 -05:00
Robin Singh
90d268741f drm/amd/display: Added pixel dynamic expansion control.
[Why]
To compare the crc of the framebuffer data at input of
display pipeline with the crc of the otg, we need to
disable pixel formatter's dynamic expansion feature during
crc capture and keep it enable in the normal operation.

[HOW]
Expose a new interface in DM and dc for pixel formatter
(fmt dynamic bitdepth expansion control). Interface control
the FMT_DYNAMIC_EXP_EN  bit, during crc capture keep
it disabled.

Signed-off-by: Robin Singh <robin.singh@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:24:26 -05:00
Oak Zeng
f81b86a043 drm/amdgpu: Enable gfx cache probing on HDP write for arcturus
This allows gfx cache to be probed and invalidated (for none-dirty cache lines)
on a HDP write (from either another GPU or CPU). This should work only for the
memory mapped as RW memory type newly added for arcturus, to achieve some cache
coherence b/t multiple memory clients.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Christian Konig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:24:19 -05:00
Oak Zeng
cb1545f710 drm/amdgpu: Clean up gmc_v9_0_gart_enable
Many logic in this function are HDP set up,
not gart set up. Moved those logic to gmc_v9_0_hw_init.
No functional change.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Christian konig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:24:12 -05:00
Marek Olšák
6f3bf46a7e drm/amdgpu: simplify gds_compute_max_wave_id computation
Use asic constants.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10 19:23:35 -05:00
Stephen Rothwell
1cd4d9eead drm/amdkfd: update for drmP.h removal
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-09 12:04:48 -05:00
Harish Kasiviswanathan
6b855f7b83 drm/amdkfd: Check against device cgroup
Participate in device cgroup. All kfd devices are exposed via /dev/kfd.
So use /dev/dri/renderN node.

Before exposing the device to a task check if it has permission to
access it. If the task (based on its cgroup) can access /dev/dri/renderN
then expose the device via kfd node.

If the task cannot access /dev/dri/renderN then process device data
(pdd) is not created. This will ensure that task cannot use the device.

In sysfs topology, all device nodes are visible irrespective of the task
cgroup. The sysfs node directories are created at driver load time and
cannot be changed dynamically. However, access to information inside
nodes is controlled based on the task's cgroup permissions.

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-07 15:11:38 -05:00
Alex Deucher
a3e520a25c drm/amdkfd: fix the build when CIK support is disabled
Add proper ifdefs around CIK code in kfd setup.

Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-07 15:11:32 -05:00
Krzysztof Kozlowski
23c61b4599 drm/amd: Fix Kconfig indentation
Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
    $ sed -e 's/^        /\t/' -i */Kconfig

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-07 15:11:17 -05:00
Ori Messinger
ad02e08e05 drm/amdgpu: Report vram vendor with sysfs (v3)
The vram vendor can be found as a separate sysfs file at:
/sys/class/drm/card[X]/device/mem_info_vram_vendor
The vram vendor is displayed as a string value.

v2: Use correct bit masking, and cache vram_vendor in gmc
v3: Drop unused functions for vram width, type, and vendor

Signed-off-by: Ori Messinger <ori.messinger@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-07 15:11:07 -05:00
Dan Carpenter
aa5e899de1 drm/amdkfd: Fix a && vs || typo
In the current code if "device_info" is ever NULL then the kernel will
Oops so probably || was intended instead of &&.

Fixes: e392c887df ("drm/amdkfd: Use array to probe kfd2kgd_calls")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-07 15:11:02 -05:00
Dan Carpenter
ea6d8811f1 drm/amd/powerplay: Fix error handling in smu_init_fb_allocations()
The error handling is off by one.  We should not free the first
"tables[i].bo" without decrementing "i" because that might result in a
double free.  The second problem is that when an error occurs, then the
zeroth element "tables[0].bo" isn't freed.

I had make "i" signed int for the error handling to work, so I just
updated "ret" as well as a clean up.

Fixes: f96357a991 ("drm/amd/powerplay: implement smu_init(fini)_fb_allocations function")
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-07 15:10:56 -05:00
Dan Carpenter
fa073f13a2 drm/amd/powerplay: unlock on error in smu_resume()
This function needs to drop the mutex before returning.

Fixes: f7e3a5776f ("drm/amd/powerplay: check SMU engine readiness before proceeding on S3 resume")
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-07 15:10:54 -05:00
zhengbin
6a1112da65 drm/amd/display: Remove set but not used variables 'pp_smu', 'old_pipe'
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c: In function dce110_enable_audio_stream:
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:949:23: warning: variable pp_smu set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c: In function dce110_disable_audio_stream:
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:983:23: warning: variable pp_smu set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c: In function dce110_program_front_end_for_pipe:
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:2429:19: warning: variable old_pipe set but not used [-Wunused-but-set-variable]

'pp_smu' is not used since commit 170a2398d2 ("drm/amd/display:
make clk_mgr call enable_pme_wa")

'old_pipe' is not used since commit 65d38262b3 ("drm/amd/display:
fbc state could not reach while enable fbc")

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-07 15:10:50 -05:00
zhengbin
adda1367a8 drm/amd/display: Remove set but not used variable 'pixel_width'
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c: In function dpp2_get_optimal_number_of_taps:
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c:359:11: warning: variable pixel_width set but not used [-Wunused-but-set-variable]

It is not used since commit f7de96ee8b ("drm/amd/display:
Add DCN2 DPP")

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-07 15:10:45 -05:00
zhengbin
2b0619c159 drm/amd/display: Remove set but not used variables 'h_ratio_chroma', 'v_ratio_chroma'
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c: In function dwb_program_horz_scalar:
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c:725:11: warning: variable h_ratio_chroma set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c: In function dwb_program_vert_scalar:
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c:806:11: warning: variable v_ratio_chroma set but not used [-Wunused-but-set-variable]

They are not used since commit 345429a67c ("drm/amd/display:
Add DCN2 DWB")

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-07 15:10:43 -05:00