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drm/amd/display: enable smu set dcfclk
[Why] SMU fixed this issue after version 0x370c00 [How] enable smu send message to set dcfclk after smu version 0x370c00 Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -124,7 +124,7 @@ int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int reque
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{
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int actual_dcfclk_set_mhz = -1;
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if (clk_mgr->smu_ver < 0xFFFFFFFF)
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if (clk_mgr->smu_ver < 0x370c00)
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return actual_dcfclk_set_mhz;
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actual_dcfclk_set_mhz = rn_vbios_smu_send_msg_with_param(
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@ -139,7 +139,7 @@ int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int
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{
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int actual_min_ds_dcfclk_mhz = -1;
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if (clk_mgr->smu_ver < 0xFFFFFFFF)
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if (clk_mgr->smu_ver < 0x370c00)
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return actual_min_ds_dcfclk_mhz;
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actual_min_ds_dcfclk_mhz = rn_vbios_smu_send_msg_with_param(
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