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drm/amd/display: add guard for SMU ver, for 48mhz clk

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[why]
dp_48m_refclk_driver_pwdn is persistent through S3 and S5.
This was worked arround in SMU FW 55.21.0. Earlier FW don't have this fix
so we will hang on reboot

[how]
add a guard for smu versions before SMU FW 55.21.0

Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Joseph Gravenor 2019-09-16 15:13:33 -04:00 committed by Alex Deucher
parent 57133a28bc
commit ac81c2a75b
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
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@ -649,7 +649,7 @@ void rn_clk_mgr_construct(
pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);
}
if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {
/* enable powerfeatures when displaycount goes to 0 */
rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
}