AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2025-02-05 03:25:26 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

drm/amd/display: check phy dpalt lane count config

Browse Source 
[Why]
Type-c PHY config is not align with dpcd lane count.
When those values didn't match, it cause driver do
link training with 4 lane but phy only can output 2 lane.
The link trainig always fail.

[How]
1. Modify get_max_link_cap function. According DPALT_DP4
to update max lane count.
2. Add dp_mst_verify_link_cap to handle MST case because
we didn't call dp_mst_verify_link_cap for MST case.

Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lewis Huang 2019-09-05 15:33:58 +08:00 committed by Alex Deucher
parent d832fc3b18
commit f537d474df
5 changed files with 26 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -872,7 +872,8 @@ bool dc_link_detect_helper(struct dc_link *link, enum dc_detect_reason reason)
* empty which leads to allocate_mst_payload() has "0"
* pbn_per_slot value leading to exception on dc_fixpt_div()
*/
link->verified_link_cap = link->reported_link_cap;
dp_verify_mst_link_cap(link);
if (prev_sink != NULL)
dc_sink_release(prev_sink);
return false;

16
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
View File

@ -1409,6 +1409,9 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link)
if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
max_link_cap.link_rate = LINK_RATE_HIGH3;
if (link->link_enc->funcs->get_max_link_cap)
link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
/* Lower link settings based on sink's link cap */
if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
max_link_cap.lane_count =
@ -1670,6 +1673,19 @@ bool dp_verify_link_cap_with_retries(
return success;
}
bool dp_verify_mst_link_cap(
struct dc_link *link)
{
struct dc_link_settings max_link_cap = {0};
max_link_cap = get_max_link_cap(link);
link->verified_link_cap = get_common_supported_link_settings(
link->reported_link_cap,
max_link_cap);
return true;
}
static struct dc_link_settings get_common_supported_link_settings(
struct dc_link_settings link_setting_a,
struct dc_link_settings link_setting_b)

1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
View File

@ -337,6 +337,7 @@ struct dcn10_link_enc_registers {
type RDPCS_TX_FIFO_ERROR_MASK;\
type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
type RDPCS_PHY_DPALT_DP4;\
type RDPCS_PHY_DPALT_DISABLE;\
type RDPCS_PHY_DPALT_DISABLE_ACK;\
type RDPCS_PHY_DP_MPLLB_V2I;\

3
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
View File

@ -43,6 +43,9 @@ bool dp_verify_link_cap_with_retries(
struct dc_link_settings *known_limit_link_setting,
int attempts);
bool dp_verify_mst_link_cap(
struct dc_link *link);
bool dp_validate_mode_timing(
struct dc_link *link,
const struct dc_crtc_timing *timing);

4
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
View File

@ -184,6 +184,10 @@ struct link_encoder_funcs {
bool (*fec_is_active)(struct link_encoder *enc);
#endif
bool (*is_in_alt_mode) (struct link_encoder *enc);
void (*get_max_link_cap)(struct link_encoder *enc,
struct dc_link_settings *link_settings);
enum signal_type (*get_dig_mode)(
struct link_encoder *enc);
};