Commit Graph

8802 Commits

Author SHA1 Message Date
Joerg Roedel
2f2fbfb71e Merge branches 'arm/renesas', 'arm/smmu', 'ppc/pamu', 'x86/vt-d', 'x86/amd' and 'core' into next 2018-10-10 18:09:37 +02:00
Shaokun Zhang
742fafa50b arm64: mm: Drop the unused cpu parameter
Cpu parameter is never used in flush_context, remove it.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-09 17:17:23 +01:00
Eric Biggers
7ff9036a62 crypto: arm64/aes - fix handling sub-block CTS-CBC inputs
In the new arm64 CTS-CBC implementation, return an error code rather
than crashing on inputs shorter than AES_BLOCK_SIZE bytes.  Also set
cra_blocksize to AES_BLOCK_SIZE (like is done in the cts template) to
indicate the minimum input size.

Fixes: dd597fb33f ("crypto: arm64/aes-blk - add support for CTS-CBC mode")
Signed-off-by: Eric Biggers <ebiggers@google.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-10-08 13:47:02 +08:00
Ingo Molnar
02678a5823 Merge branch 'core/core' into x86/build, to prevent conflicts
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2018-10-06 15:51:56 +02:00
Thomas Gleixner
a223464217 Merge tag 'irqchip-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier:

 - kexec/kdump support for EFI-based GICv3 platforms
 - Marvell SEI support
 - QC PDC fixes
 - GIC cleanups and optimizations
 - DT updates

[ tglx: Dropped the madera driver as it breaks the build ]
2018-10-06 15:45:07 +02:00
James Morse
e9ed821be4 arm64: mm: Use #ifdef for the __PAGETABLE_P?D_FOLDED defines
__is_defined(__PAGETABLE_P?D_FOLDED) doesn't quite work as intended
as these symbols are internal to asm-generic and aren't defined in the
way kconfig expects. This makes them always evaluate to false.
Switch to #ifdef.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-05 17:19:40 +01:00
Lokesh Vutla
d59c774496 arm64: defconfig: Enable SERIAL_8250_OMAP
Enabling CONFIG_SERIAL_8250_OMAP that is used by TI's
AM6 SoC.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-05 17:46:00 +02:00
Lokesh Vutla
41925a21cd arm64: defconfig: Enable TI_SCI related configs
Enable TI System Control Interface (TI_SCI) Message Protocol library
and it's relevant power management drivers using this library.

TI's AM6 SoC uses this TI_SCI library to communicate to its system
controller(DMSC). While at it, enable TI_MESSAGE_MANAGER mailbox driver
using which this communication happens.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-05 17:45:40 +02:00
Dinh Nguyen
74cad26d8d arm64: dts: stratix10: add ethernet aliases
Add ethernet<n> alias for all gmacs on the devkit.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: move ethernet aliases to board file
2018-10-05 10:29:13 -05:00
Arnd Bergmann
4e6a32e6eb mvebu dt64 for 4.20 (part 2)
- Add System Error Interrupt support to Armada SoCs (7K/8K)
  - Add CPU idle support on Armada 8K
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Merge tag 'mvebu-dt64-4.20-2' of git://git.infradead.org/linux-mvebu into next/dt

mvebu dt64 for 4.20 (part 2)

 - Add System Error Interrupt support to Armada SoCs (7K/8K)
 - Add CPU idle support on Armada 8K

* tag 'mvebu-dt64-4.20-2' of git://git.infradead.org/linux-mvebu:
  arm64: dts: clearfog-gt-8k: add PCIe slot description
  arm64: dts: marvell: add CP110 ICU SEI subnode
  arm64: dts: marvell: use new bindings for CP110 interrupts
  arm64: dts: marvell: add AP806 SEI subnode
  arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8K
  arm64: dts: marvell: Add node labels for the cpus

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-05 17:23:48 +02:00
Kyrylo Tkachov
0293c8ba80 arm64: Fix typo in a comment in arch/arm64/mm/kasan_init.c
"bellow" -> "below"

The recommendation from kegel.com/kerspell is to only fix the howlers.
"Bellow" is a synonym of "howl" so this should be appropriate.

Signed-off-by: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-05 11:49:32 +01:00
Rob Herring
4355151de4 Merge branch 'all-dtbs' into dt/next 2018-10-04 14:16:15 -05:00
Arnd Bergmann
afb8fb9ad9 Renesas ARM64 Based SoC SoC Updates for v4.20
* Add support for RZ/G2E (r8a774c0) and RZ/G2M (r8a774a1) SoCs
 * Enable Compare Match Timer (CMT) and Timer Unit (TMU)
   for Renesas SoCs
 * Remove no longer needed ARCH_SHMOBILE Kconfig symbol
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Merge tag 'renesas-arm64-soc-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Renesas ARM64 Based SoC SoC Updates for v4.20

* Add support for RZ/G2E (r8a774c0) and RZ/G2M (r8a774a1) SoCs
* Enable Compare Match Timer (CMT) and Timer Unit (TMU)
  for Renesas SoCs
* Remove no longer needed ARCH_SHMOBILE Kconfig symbol

* tag 'renesas-arm64-soc-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: Add Renesas R8A774C0 support
  arm64: Add Renesas R8A774A1 support
  arm64: enable CMT/TMU support for Renesas SoC
  arm64: renesas: Remove the ARCH_SHMOBILE Kconfig symbol

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-04 17:35:31 +02:00
Arnd Bergmann
de5c3ace8c Enablement of the newly added Innosilicon hdmiphy.
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Merge tag 'v4.20-rockchip-defconfig64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/defconfig

Enablement of the newly added Innosilicon hdmiphy.

* tag 'v4.20-rockchip-defconfig64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: defconfig: enable Rockchip Innosilicon hdmiphy

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-04 17:12:38 +02:00
Masahiro Yamada
b6f8c4769f arm64: defconfig: enable CONFIG_MMC_UNIPHIER
Enable the UniPhier SD controller driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-04 17:10:02 +02:00
Arnd Bergmann
b062e5b79c arm64: dts: Amlogic updates for v4.20, round 3
- AXG: fix eMMC
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Merge tag 'amlogic-dt64-3' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt

arm64: dts: Amlogic updates for v4.20, round 3
- AXG: fix eMMC

* tag 'amlogic-dt64-3' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  arm64: dts: meson-axg: s400: disable emmc
  arm64: dts: meson-axg: s400: add missing emmc pwrseq

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-04 17:08:52 +02:00
Arnd Bergmann
86dc4eaf12 UniPhier ARM SoC DT updates for v4.20
- Add more clocks to NAND controller nodes
 
 - Add SPI controller nodes
 
 - Add SD controller nodes
 
 - Add USB 3.0 and its PHY nodes
 
 - Add PHY nodes for USB 2.0
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Merge tag 'uniphier-dt-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt

UniPhier ARM SoC DT updates for v4.20

- Add more clocks to NAND controller nodes

- Add SPI controller nodes

- Add SD controller nodes

- Add USB 3.0 and its PHY nodes

- Add PHY nodes for USB 2.0

* tag 'uniphier-dt-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
  arm64: dts: uniphier: Add USB2 PHY nodes
  arm64: dts: uniphier: Add USB3 controller nodes
  ARM: dts: uniphier: Add USB2 PHY nodes
  ARM: dts: uniphier: Add USB3 controller nodes
  arm64: dts: uniphier: add SD controller nodes
  ARM: dts: uniphier: add SD/eMMC controller nodes
  arm64: dts: uniphier: add SPI node for LD20, LD11 and PXs3
  ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs
  ARM: dts: uniphier: add SPI pin-mux node
  arm64: uniphier: dts: add more clocks to Denali NAND controller node
  ARM: uniphier: dts: add more clocks to Denali NAND controller node

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-04 17:08:02 +02:00
Arnd Bergmann
22b9292141 Some additional new boards, the rk3399-based RockPro64 from Pine64, as well
as the Vamrs Rock960. Another big feature is display support including hdmi
 and the Innosilicon hdmiphy on the rk3328, right now enabled on the rock64.
 The rock64 also got its spi-nor and spdif enabled. On the px30 we can see
 dwc2-based usb support now and finally some misc fixes, like for a new dtc
 warning, missing address and size cells and microSD fix on sapphire.
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Merge tag 'v4.20-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Some additional new boards, the rk3399-based RockPro64 from Pine64, as well
as the Vamrs Rock960. Another big feature is display support including hdmi
and the Innosilicon hdmiphy on the rk3328, right now enabled on the rock64.
The rock64 also got its spi-nor and spdif enabled. On the px30 we can see
dwc2-based usb support now and finally some misc fixes, like for a new dtc
warning, missing address and size cells and microSD fix on sapphire.

* tag 'v4.20-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: enable display nodes on rk3328-rock64
  arm64: dts: rockchip: add rk3328 display nodes
  arm64: dts: rockchip: add Innosilicon hdmi phy node to rk3328
  arm64: dts: rockchip: add missing address and size cells for rk3399 mipi dsi
  arm64: dts: rockchip: Enable SPI NOR flash on Rock64
  arm64: dts: rockchip: add initial dts support for Rockpro64
  arm64: dts: rockchip: enable dwc2-based otg controller on px30-evb
  arm64: dts: rockchip: add dwc2 otg controller on px30
  dt-bindings: usb: dwc2: add description for px30
  arm64: dts: rockchip: Enable SD card detection for Rock960 boards
  arm64: dts: rockchip: Add support for Rock960 board
  dt-bindings: arm: rockchip: Add binding for Rock960 board
  arm64: dts: rockchip: Split out common nodes for Rock960 based boards
  arm64: dts: rockchip: add spdif sound node for rock64
  arm64: dts: rockchip: Fix microSD in rk3399 sapphire board
  arm64: dts: rockchip: Fix I2C bus unit-address error on rk3399-puma-haikou

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-04 16:19:47 +02:00
Kunihiko Hayashi
546cba0623 arm64: dts: uniphier: Add USB2 PHY nodes
Add nodes of USB2 physical layer for UniPhier SoC. This supports LD11.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-04 09:41:06 +09:00
Kunihiko Hayashi
d7b9beb830 arm64: dts: uniphier: Add USB3 controller nodes
Add USB3 controller nodes including usb-core, resets, regulator, ss-phy
and hs-phy. This supports for LD20, PXs3 and the boards. This includes
additional efuse nodes for obtaining PHY trimming values.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-04 09:41:06 +09:00
Jerome Brunet
59d925ac20 arm64: dts: meson-axg: s400: disable emmc
While it is possible to rework the s400 board to solder an eMMC on it,
it is not the default option and most boards are fitted with a NAND
instead.

Let's disable the emmc device by default to reflect this. The board
equipped with an eMMC will just have to alter the DT in the
bootloader, like we do for the reserved memory regions.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-10-03 08:52:04 -07:00
Jerome Brunet
087e9a465c arm64: dts: meson-axg: s400: add missing emmc pwrseq
eMMC pwrseq is defined in the s400 dts but not used in the emmc node.
This is probably just a copy/paste error

Fixes: 221cf34bac ("ARM64: dts: meson-axg: enable the eMMC controller")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-10-03 08:52:04 -07:00
Baruch Siach
91f84690b5 arm64: dts: clearfog-gt-8k: add PCIe slot description
This adds support for the PCIe interface on the CON4 mini-PCIe
connector.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-10-03 17:22:34 +02:00
Julien Thierry
b0506a8bbb arm64: xen: Use existing helper to check interrupt status
The status of interrupts might depend on more than just pstate. Use
interrupts_disabled() instead of raw_irqs_disabled_flags() to take the full
context into account.

Acked-by: Stefano Stabellini <sstabellini@kernel.org>
Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-03 16:14:11 +01:00
Julien Thierry
9a0c032825 arm64: Use daifflag_restore after bp_hardening
For EL0 entries requiring bp_hardening, daif status is kept at
DAIF_PROCCTX_NOIRQ until after hardening has been done. Then interrupts
are enabled through local_irq_enable().

Before using local_irq_* functions, daifflags should be properly restored
to a state where IRQs are enabled.

Enable IRQs by restoring DAIF_PROCCTX state after bp hardening.

Acked-by: James Morse <james.morse@arm.com>
Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-03 16:12:21 +01:00
Julien Thierry
f05692919b arm64: daifflags: Use irqflags functions for daifflags
Some of the work done in daifflags save/restore is already provided
by irqflags functions. Daifflags should always be a superset of irqflags
(it handles irq status + status of other flags). Modifying behaviour of
irqflags should alter the behaviour of daifflags.

Use irqflags_save/restore functions for the corresponding daifflags
operation.

Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-03 16:08:52 +01:00
Eric W. Biederman
f283801851 signal: Remove the need for __ARCH_SI_PREABLE_SIZE and SI_PAD_SIZE
Rework the defintion of struct siginfo so that the array padding
struct siginfo to SI_MAX_SIZE can be placed in a union along side of
the rest of the struct siginfo members.  The result is that we no
longer need the __ARCH_SI_PREAMBLE_SIZE or SI_PAD_SIZE definitions.

Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-10-03 16:46:43 +02:00
zhong jiang
f0725345e3 arm64: KVM: Remove some extra semicolon in kvm_target_cpu
There are some extra semicolon in kvm_target_cpu, remove it.

Signed-off-by: zhong jiang <zhongjiang@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-03 11:48:34 +01:00
Marc Zyngier
bca607ebc7 KVM: arm/arm64: Rename kvm_arm_config_vm to kvm_arm_setup_stage2
VM tends to be a very overloaded term in KVM, so let's keep it
to describe the virtual machine. For the virtual memory setup,
let's use the "stage2" suffix.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-03 11:45:29 +01:00
Suzuki K Poulose
233a7cb235 kvm: arm64: Allow tuning the physical address size for VM
Allow specifying the physical address size limit for a new
VM via the kvm_type argument for the KVM_CREATE_VM ioctl. This
allows us to finalise the stage2 page table as early as possible
and hence perform the right checks on the memory slots
without complication. The size is encoded as Log2(PA_Size) in
bits[7:0] of the type field. For backward compatibility the
value 0 is reserved and implies 40bits. Also, lift the limit
of the IPA to host limit and allow lower IPA sizes (e.g, 32).

The userspace could check the extension KVM_CAP_ARM_VM_IPA_SIZE
for the availability of this feature. The cap check returns the
maximum limit for the physical address shift supported by the host.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-03 11:45:20 +01:00
Suzuki K Poulose
58b3efc820 kvm: arm64: Limit the minimum number of page table levels
Since we are about to remove the lower limit on the IPA size,
make sure that we do not go to 1 level page table (e.g, with
32bit IPA on 64K host with concatenation) to avoid splitting
the host PMD huge pages at stage2.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-03 11:45:14 +01:00
Suzuki K Poulose
0f62f0e95b kvm: arm64: Set a limit on the IPA size
So far we have restricted the IPA size of the VM to the default
value (40bits). Now that we can manage the IPA size per VM and
support dynamic stage2 page tables, we can allow VMs to have
larger IPA. This patch introduces a the maximum IPA size
supported on the host. This is decided by the following factors :

 1) Maximum PARange supported by the CPUs - This can be inferred
    from the system wide safe value.
 2) Maximum PA size supported by the host kernel (48 vs 52)
 3) Number of levels in the host page table (as we base our
    stage2 tables on the host table helpers).

Since the stage2 page table code is dependent on the stage1
page table, we always ensure that :

  Number of Levels at Stage1 >= Number of Levels at Stage2

So we limit the IPA to make sure that the above condition
is satisfied. This will affect the following combinations
of VA_BITS and IPA for different page sizes.

  Host configuration | Unsupported IPA ranges
  39bit VA, 4K       | [44, 48]
  36bit VA, 16K      | [41, 48]
  42bit VA, 64K      | [47, 52]

Supporting the above combinations need independent stage2
page table manipulation code, which would need substantial
changes. We could purse the solution independently and
switch the page table code once we have it ready.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-03 11:44:55 +01:00
Arnd Bergmann
040f340134 arm64: arch_timer: avoid unused function warning
arm64_1188873_read_cntvct_el0() is protected by the correct
CONFIG_ARM64_ERRATUM_1188873 #ifdef, but the only reference to it is
also inside of an CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND section,
and causes a warning if that is disabled:

drivers/clocksource/arm_arch_timer.c:323:20: error: 'arm64_1188873_read_cntvct_el0' defined but not used [-Werror=unused-function]

Since the erratum requires that we always apply the workaround
in the timer driver, select that symbol as we do for SoC
specific errata.

Fixes: 95b861a4a6 ("arm64: arch_timer: Add workaround for ARM erratum 1188873")
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-03 11:41:34 +01:00
Miquel Raynal
b0e11e58c5 arm64: dts: marvell: add CP110 ICU SEI subnode
The ICU handles several interrupt groups, each of them being a subpart
of the ICU node.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-10-03 09:44:18 +02:00
Miquel Raynal
f21bb56e84 arm64: dts: marvell: use new bindings for CP110 interrupts
Create an ICU subnode for the NSR interrupts. This subnode becomes the
CP110 interrupt parent, removing the need for the ICU_GRP_NSR parameter.
Move all DT110 nodes to use these new bindings.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-10-03 09:44:09 +02:00
Masahiro Yamada
84a9c4d559 arm64: dts: uniphier: add SD controller nodes
Add SD controller nodes for LD20 and PXs3.
LD20 does not support the UHS mode, while PXs3 supports it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-03 08:21:27 +09:00
Miquel Raynal
b9a5950fc5 arm64: dts: marvell: add AP806 SEI subnode
Add the System Error Interrupt node, representing an IRQ chip which is
part of the GIC. The SEI node aggregates interrupts from the AP through
wired interrupts, and from the CPs through MSIs.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-10-02 16:46:53 +02:00
orenbh
8ed4636877 arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8K
This patch adds CPU deep Idle and Cluster deep Idle states BUT it defines
the idle state for each cpu (defined under cpu-idle-states parameter)
only for the quad version therefore it does NOT activate CPU Idle
capability for the other version.

[gregory: extract from a larger patch]
Signed-off-by: orenbh <orenbh@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-10-02 16:46:52 +02:00
Gregory CLEMENT
92e5d4e939 arm64: dts: marvell: Add node labels for the cpus
Aligned with what we have done for the others nodes. It will also allow
to easily modify the cpu configuration at board (or sub-SoC) level.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-10-02 16:46:52 +02:00
Rob Herring
37c8a5fafa kbuild: consolidate Devicetree dtb build rules
There is nothing arch specific about building dtb files other than their
location under /arch/*/boot/dts/. Keeping each arch aligned is a pain.
The dependencies and supported targets are all slightly different.
Also, a cross-compiler for each arch is needed, but really the host
compiler preprocessor is perfectly fine for building dtbs. Move the
build rules to a common location and remove the arch specific ones. This
is done in a single step to avoid warnings about overriding rules.

The build dependencies had been a mixture of 'scripts' and/or 'prepare'.
These pull in several dependencies some of which need a target compiler
(specifically devicetable-offsets.h) and aren't needed to build dtbs.
All that is really needed is dtc, so adjust the dependencies to only be
dtc.

This change enables support 'dtbs_install' on some arches which were
missing the target.

Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Paul Burton <paul.burton@mips.com>
Acked-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Michal Marek <michal.lkml@markovi.net>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Chris Zankel <chris@zankel.net>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: linux-kbuild@vger.kernel.org
Cc: linux-snps-arc@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: uclinux-h8-devel@lists.sourceforge.jp
Cc: linux-mips@linux-mips.org
Cc: nios2-dev@lists.rocketboards.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-xtensa@linux-xtensa.org
Signed-off-by: Rob Herring <robh@kernel.org>
2018-10-02 09:23:21 -05:00
Miquel Raynal
228197c569 arm64: marvell: Enable SEI driver
Enable the newly introduced Marvell SEI driver for the 64-bit Marvell
EBU platforms.

Suggested-by: Haim Boot <hayim@marvell.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-02 12:00:18 +01:00
Arnd Bergmann
16a1548013 Merge tag 'actions-arm64-soc-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/soc
Actions Semi arm64 SoC for v4.20

This updates and extends the MAINTAINERS entry, adding Mani.
It also selects PINCTRL in Kconfig.

* tag 'actions-arm64-soc-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions:
  arm64: actions: Enable PINCTRL in platforms Kconfig
  MAINTAINERS: Add entry for Actions Semi Owl SoCs DMA driver
  MAINTAINERS: Add entry for Actions Semiconductor Owl I2C driver
  MAINTAINERS: Update clock binding entry for Actions Semi Owl SoCs
  MAINTAINERS: Add Actions Semi S900 clk entries
  MAINTAINERS: Add reviewer for ACTIONS platforms

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-02 12:05:16 +02:00
Arnd Bergmann
e9a4dd9999 mvebu dt64 for 4.20 (part 1)
- Add watchdog node on Armada 37xx
  - Update PPv2 interrupts name
  - Add support for the SolidRun Clearfog GT 8K (Aramda 8040 based)
  - Add thermal-zone nodes for Aramda 7K/8K
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Merge tag 'mvebu-dt64-4.20-1' of git://git.infradead.org/linux-mvebu into next/dt

mvebu dt64 for 4.20 (part 1)

 - Add watchdog node on Armada 37xx
 - Update PPv2 interrupts name
 - Add support for the SolidRun Clearfog GT 8K (Aramda 8040 based)
 - Add thermal-zone nodes for Aramda 7K/8K

* tag 'mvebu-dt64-4.20-1' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: armada-37xx: add nodes to support watchdog
  arm64: dts: marvell: armada-cp110: describe more PPv2 interrupts
  arm64: dts: marvell: armada-cp110: change the PPv2 IRQ names
  arm64: dts: add support for SolidRun Clearfog GT 8K
  arm64: dts: marvell: add thermal-zone node in cp110 DTSI file
  arm64: dts: marvell: add macro to make distinction between node names
  arm64: dts: marvell: add thermal-zone node in ap806 DTSI file
  arm64: dts: marvell: move AP806/CP110 thermal nodes into a new syscon

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-02 11:53:19 +02:00
Arnd Bergmann
ca2fbd9ad4 Freescale arm64 device tree update for 4.20:
- Add the second Dual UART device for LS208xA SoCs.
  - Add necessary big-endian property for NOR device on LS104xA based
    boards, remove unneeded big-endian property from IFC controller.
  - DTC has new checks for I2C and SPI buses to land into 4.20.  A patch
    from Rob to fix the bus node names and warnings in unit-addresses.
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Merge tag 'imx-dt64-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

Freescale arm64 device tree update for 4.20:
 - Add the second Dual UART device for LS208xA SoCs.
 - Add necessary big-endian property for NOR device on LS104xA based
   boards, remove unneeded big-endian property from IFC controller.
 - DTC has new checks for I2C and SPI buses to land into 4.20.  A patch
   from Rob to fix the bus node names and warnings in unit-addresses.

* tag 'imx-dt64-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: fsl: Fix I2C and SPI bus warnings
  arm64: dts: ls208xa: add second duart
  arm64: dts: fsl: remove big-endian field from IFC controller
  arm64: dts: Add big-endian in nor node for ls104xa

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-02 11:41:59 +02:00
Arnd Bergmann
5908704d98 Qualcomm ARM64 Updates for v4.20
* Update Coresight for MSM8916
 * Switch to use mailbox for smp2p and smd on MSM8996
 * Add dispcc, dsp, USB, regulator, and other nodes for SDM845
 * Drop model/compatible from MSM8916 and MSM8996
 * Add compat for db820c
 * Add MSM8998 SoC and board support along with associated nodes
 * Add RESIN/PON for Qualcomm PM8916 and PM8994
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Merge tag 'qcom-arm64-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt

Qualcomm ARM64 Updates for v4.20

* Update Coresight for MSM8916
* Switch to use mailbox for smp2p and smd on MSM8996
* Add dispcc, dsp, USB, regulator, and other nodes for SDM845
* Drop model/compatible from MSM8916 and MSM8996
* Add compat for db820c
* Add MSM8998 SoC and board support along with associated nodes
* Add RESIN/PON for Qualcomm PM8916 and PM8994

* tag 'qcom-arm64-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (31 commits)
  Revert "dt-bindings: thermal: qcom-spmi-temp-alarm: Fix documentation of 'reg'"
  Revert "dt-bindings: iio: vadc: Fix documentation of 'reg'"
  arm64: dts: msm8916: Update coresight bindings for hardware ports
  arm64: dts: msm8996: Transition smp2p and smd to mailbox
  arm64: dts: qcom: pm8998: Add pm8998 thermal zone
  arm64: dts: qcom: pm8998: Add spmi-temp-alarm node
  dt-bindings: thermal: qcom-spmi-temp-alarm: Fix documentation of 'reg'
  arm64: dts: sdm845: Add dispcc node
  arm64: dts: qcom: sdm845: Add adsp, cdsp and slpi smp2p
  arm64: dts: qcom: sdm845-mtp: Add nodes for USB
  arm64: dts: qcom: sdm845-mtp: Add RPMh VRM/XOB regulators
  arm64: dts: qcom: sdm845: Add USB-related nodes
  arm64: dts: qcom: Add AOSS reset driver node for SDM845
  arm64: dts: msm8996: Drop model
  arm64: dts: msm8916: Drop model and compatible
  arm64: dts: db820c: Add qcom,apq8096 to compatible string
  arm64: dts: qcom: Populate pm8998 with additional nodes
  arm64: dts: qcom: msm8998: Add smp2p nodes
  arm64: dts: qcom: msm8998: Add the qfprom node
  arm64: dts: qcom: msm8998: Add firmware node
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-02 11:31:49 +02:00
Arnd Bergmann
6a11b1804a Actions Semi arm64 based SoC DT for v4.20
This updates SPDX headers for remaining files.
 
 For S900 it adds clock, pinctrl, i2c and dma nodes.
 S900 SPS is added via topic branch (shared with driver).
 
 For S700 it adds clock nodes.
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Merge tag 'actions-arm64-dt-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/dt

Actions Semi arm64 based SoC DT for v4.20

This updates SPDX headers for remaining files.

For S900 it adds clock, pinctrl, i2c and dma nodes.
S900 SPS is added via topic branch (shared with driver).

For S700 it adds clock nodes.

* tag 'actions-arm64-dt-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions:
  arm64: dts: actions: s700: Set UART clock references from CMU
  arm64: dts: actions: s700: Add Clock Management Unit
  arm64: dts: actions: s900: Add DMA Controller
  arm64: dts: actions: s900-bubblegum-96: Enable I2C1 and I2C2
  arm64: dts: actions: s900: Add I2C controller nodes
  arm64: dts: actions: s900-bubblegum-96: Add gpio line names
  arm64: dts: actions: s900: Add gpio properties to pinctrl node
  arm64: dts: actions: s900: Add pinctrl node
  arm64: dts: actions: s900: Add SPS node
  arm64: dts: actions: s900: Source CMU clock for UARTs
  arm64: dts: actions: s900: Add Clock Management Unit nodes
  dt-bindings: power: Add Actions Semi S900 SPS
  arm64: dts: actions: Convert to new-style SPDX license identifiers

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-02 11:19:36 +02:00
Arnd Bergmann
508b330b82 mt2712 - add spi slave node
mt7622:
 - add timer node
 - add CCI node
 - add PMU node
 - add bluetooth node
 - add SPI slave node
 - fix reference board (rfb1) memory and sort node alphabetically
 - add support for Bananapi-R64
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Merge tag 'v4.19-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt

mt2712 - add spi slave node

mt7622:
- add timer node
- add CCI node
- add PMU node
- add bluetooth node
- add SPI slave node
- fix reference board (rfb1) memory and sort node alphabetically
- add support for Bananapi-R64

* tag 'v4.19-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: dts: Add spi slave dts
  arm64: dts: mt7622: add bananapi BPI-R64 board
  arm64: dts: mt7622: fix ram size for rfb1
  arm64: dts: mt7622: add a bluetooth 5 device node
  arm64: dts: mt7622: add timer, CCI-400 and PMU nodes

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-02 11:15:38 +02:00
Arnd Bergmann
f6cfb90582 Allwinner arm64 DT changes for 4.20
Our usual set of DT changes for the arm64 Allwinner SoCs.
 
 The most notable things are:
   - HDMI support on the A64
   - New boards: OrangePi One Plus
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Merge tag 'sunxi-dt64-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

Allwinner arm64 DT changes for 4.20

Our usual set of DT changes for the arm64 Allwinner SoCs.

The most notable things are:
  - HDMI support on the A64
  - New boards: OrangePi One Plus

* tag 'sunxi-dt64-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (28 commits)
  arm64: dts: allwinner: a64: a64-olinuxino: set the PHY TX delay
  arm64: dts: allwinner: a64: Enable HDMI output on A64 boards w/ HDMI
  arm64: dts: allwinner: a64: Add display pipeline
  arm64: dts: allwinner: h6: add system controller device tree node
  arm64: dts: allwinner: h6: Add OrangePi One Plus initial support
  arm64: dts: allwinner: a64: Rename r_i2c_pins_a label to r_i2c_pl89_pins
  arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins
  arm64: dts: allwinner: a64: Split out data strobe pin from mmc2 pinmux
  arm64: dts: allwinner: a64: NanoPi-A64: Add blue status LED
  arm64: dts: allwinner: a64: NanoPi-A64: Add Wifi chip
  arm64: dts: allwinner: a64: NanoPi-A64: Add Ethernet
  arm64: dts: allwinner: a64: NanoPi-A64: Fix DCDC1 voltage
  arm64: dts: allwinner: a64: Olinuxino: enable USB
  arm64: dts: allwinner: a64: Olinuxino: add Ethernet nodes
  arm64: dts: allwinner: a64: Olinuxino: fix DRAM voltage
  arm64: dts: allwinner: a64: Orange Pi Win: Adjust CSI power rails
  arm64: dts: allwinner: a64: Orange Pi Win: Add SPI flash node
  arm64: dts: allwinner: a64: Orange Pi Win: Add SDIO node
  arm64: dts: allwinner: a64: Orange Pi Win: Add LED node
  arm64: dts: allwinner: a64: Orange Pi Win: Add UARTs
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-02 10:28:23 +02:00
Arnd Bergmann
8bdc2e5686 Allwinner H3 and H5 DT additions for 4.20
This is our usual H3/H5 pull request
 
 The most notable changes are:
   - the video decoding / encoding unit is finally enabled on the H3
   - Mali support for the H5
   - New boards: BananaPi M2+ v1.2, Orange Pi Zero Plus 2 H3 support
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Merge tag 'sunxi-h3-h5-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

Allwinner H3 and H5 DT additions for 4.20

This is our usual H3/H5 pull request

The most notable changes are:
  - the video decoding / encoding unit is finally enabled on the H3
  - Mali support for the H5
  - New boards: BananaPi M2+ v1.2, Orange Pi Zero Plus 2 H3 support

* tag 'sunxi-h3-h5-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device trees
  ARM: dts: sun8i-h3: Add Video Engine and reserved memory nodes
  arm64: dts: allwinner: h5: Add device tree for Bananapi M2 Plus H5
  ARM: dts: sun8i: h3: Split out non-SoC-specific parts of Bananapi M2 Plus
  ARM: dts: sun8i: h3: bpi-m2-plus: Fix address for external RGMII Ethernet PHY
  ARM: dts: sun8i: h3-h5: ir register size should be the whole memory block
  arm64: dts: allwinner: h5: Add device node for Mali-450 GPU
  ARM: dts: sun8i: Add initial Orangepi Zero Plus 2 H3 support
  nvmem: sunxi-sid: add support for H5's SID controller

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-02 10:24:41 +02:00
Arnd Bergmann
965a2dc757 Allwinner arm64 config changes for 4.20
Here is a single config change to enable the DRM driver in the arm64
 defconfig.
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Merge tag 'sunxi-config64-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/defconfig

Allwinner arm64 config changes for 4.20

Here is a single config change to enable the DRM driver in the arm64
defconfig.

* tag 'sunxi-config64-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: defconfig: Enable CONFIG_DRM_SUN4I

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-02 09:52:25 +02:00
Ingo Molnar
b429f71bca Merge branch 'sched/urgent' into sched/core, to pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2018-10-02 09:43:39 +02:00
Kunihiko Hayashi
633da3f425 arm64: defconfig: Enable USB phys for UniPhier SoCs
Enable the USB3 and USB2 phys implemented in UniPhier SoCs.
These phys are necessary for dwc3 and ehci controllers driving
the USB ports on arm64 UniPhier SoCs.

Since the USB host drivers are already built-in, so only the phy
driver are missing to allow booting with USB devices.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-01 18:04:29 +02:00
Arnd Bergmann
4f5688908f Qualcomm ARM64 Based defconfig Updates for v4.20
* Enable Qualcomm QRTR driver
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Merge tag 'qcom-arm64-defconfig-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/defconfig

Qualcomm ARM64 Based defconfig Updates for v4.20

* Enable Qualcomm QRTR driver

* tag 'qcom-arm64-defconfig-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
  arm64: defconfig: Enable Qualcomm QRTR

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-10-01 17:59:42 +02:00
Marc Zyngier
c219bc4e92 arm64: Trap WFI executed in userspace
It recently came to light that userspace can execute WFI, and that
the arm64 kernel doesn't trap this event. This sounds rather benign,
but the kernel should decide when it wants to wait for an interrupt,
and not userspace.

Let's trap WFI and immediately return after having skipped the
instruction. This effectively makes WFI a rather expensive NOP.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 16:52:24 +01:00
Jens Axboe
c0aac682fa This is the 4.19-rc6 release
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Merge tag 'v4.19-rc6' into for-4.20/block

Merge -rc6 in, for two reasons:

1) Resolve a trivial conflict in the blk-mq-tag.c documentation
2) A few important regression fixes went into upstream directly, so
   they aren't in the 4.20 branch.

Signed-off-by: Jens Axboe <axboe@kernel.dk>

* tag 'v4.19-rc6': (780 commits)
  Linux 4.19-rc6
  MAINTAINERS: fix reference to moved drivers/{misc => auxdisplay}/panel.c
  cpufreq: qcom-kryo: Fix section annotations
  perf/core: Add sanity check to deal with pinned event failure
  xen/blkfront: correct purging of persistent grants
  Revert "xen/blkfront: When purging persistent grants, keep them in the buffer"
  selftests/powerpc: Fix Makefiles for headers_install change
  blk-mq: I/O and timer unplugs are inverted in blktrace
  dax: Fix deadlock in dax_lock_mapping_entry()
  x86/boot: Fix kexec booting failure in the SEV bit detection code
  bcache: add separate workqueue for journal_write to avoid deadlock
  drm/amd/display: Fix Edid emulation for linux
  drm/amd/display: Fix Vega10 lightup on S3 resume
  drm/amdgpu: Fix vce work queue was not cancelled when suspend
  Revert "drm/panel: Add device_link from panel device to DRM device"
  xen/blkfront: When purging persistent grants, keep them in the buffer
  clocksource/drivers/timer-atmel-pit: Properly handle error cases
  block: fix deadline elevator drain for zoned block devices
  ACPI / hotplug / PCI: Don't scan for non-hotplug bridges if slot is not bridge
  drm/syncobj: Don't leak fences when WAIT_FOR_SUBMIT is set
  ...

Signed-off-by: Jens Axboe <axboe@kernel.dk>
2018-10-01 08:58:57 -06:00
Marc Zyngier
2a3f93459d arm64: KVM: Sanitize PSTATE.M when being set from userspace
Not all execution modes are valid for a guest, and some of them
depend on what the HW actually supports. Let's verify that what
userspace provides is compatible with both the VM settings and
the HW capabilities.

Cc: <stable@vger.kernel.org>
Fixes: 0d854a60b1 ("arm64: KVM: enable initialization of a 32bit vcpu")
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-10-01 14:38:26 +01:00
Dave Martin
d26c25a9d1 arm64: KVM: Tighten guest core register access from userspace
We currently allow userspace to access the core register file
in about any possible way, including straddling multiple
registers and doing unaligned accesses.

This is not the expected use of the ABI, and nobody is actually
using it that way. Let's tighten it by explicitly checking
the size and alignment for each field of the register file.

Cc: <stable@vger.kernel.org>
Fixes: 2f4a07c5f9 ("arm64: KVM: guest one-reg interface")
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
[maz: rewrote Dave's initial patch to be more easily backported]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-10-01 14:38:05 +01:00
zhong jiang
2ba0dacbae arm64/kprobes: remove an extra semicolon in arch_prepare_kprobe
There is an extra semicolon in arch_prepare_kprobe, remove it.

Signed-off-by: zhong jiang <zhongjiang@huawei.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 14:36:49 +01:00
Suzuki K Poulose
bc1d7de8c5 kvm: arm64: Add 52bit support for PAR to HPFAR conversoin
Add support for handling 52bit addresses in PAR to HPFAR
conversion. Instead of hardcoding the address limits, we
now use PHYS_MASK_SHIFT.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-01 13:50:32 +01:00
Suzuki K Poulose
13ac4bbcc4 kvm: arm64: Switch to per VM IPA limit
Now that we can manage the stage2 page table per VM, switch the
configuration details to per VM instance. The VTCR is updated
with the values specific to the VM based on the configuration.
We store the IPA size and the number of stage2 page table levels
for the guest already in VTCR. Decode it back from the vtcr
field wherever we need it.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-01 13:50:32 +01:00
Suzuki K Poulose
7e8130456e kvm: arm64: Configure VTCR_EL2.SL0 per VM
VTCR_EL2 holds the following key stage2 translation table
parameters:
  SL0  - Entry level in the page table lookup.
  T0SZ - Denotes the size of the memory addressed by the table.

We have been using fixed values for the SL0 depending on the
page size as we have a fixed IPA size. But since we are about
to make it dynamic, we need to calculate the SL0 at runtime
per VM. This patch adds a helper to compute the value of SL0
for a VM based on the IPA size.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-01 13:50:31 +01:00
Suzuki K Poulose
5955833064 kvm: arm64: Dynamic configuration of VTTBR mask
On arm64 VTTBR_EL2:BADDR holds the base address for the stage2
translation table. The Arm ARM mandates that the bits BADDR[x-1:0]
should be 0, where 'x' is defined for a given IPA Size and the
number of levels for a translation granule size. It is defined
using some magical constants. This patch is a reverse engineered
implementation to calculate the 'x' at runtime for a given ipa and
number of page table levels. See patch for more details.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-01 13:50:31 +01:00
Suzuki K Poulose
61fa5a867b kvm: arm64: Make stage2 page table layout dynamic
Switch to dynamic stage2 page table layout based on the given
VM. So far we had a common stage2 table layout determined at
compile time. Make decision based on the VM instance depending
on the IPA limit for the VM. Adds helpers to compute the stage2
parameters based on the guest's IPA and uses them to make the decisions.

The IPA limit is still fixed to 40bits and the build time check
to ensure the stage2 doesn't exceed the host kernels page table
levels is retained. Also make sure that we use the pud/pmd level
helpers from the host only when they are not folded.

Cc: Christoffer Dall <cdall@kernel.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-01 13:50:31 +01:00
Suzuki K Poulose
865b30cdd9 kvm: arm64: Prepare for dynamic stage2 page table layout
Our stage2 page table helpers are statically defined based
on the fixed IPA of 40bits and the host page size. As we are
about to add support for configurable IPA size for VMs, we
need to make the page table checks for each VM. This patch
prepares the stage2 helpers to make the transition to a VM
dependent table layout easier. Instead of statically defining
the table helpers based on the page table levels, we now
check the page table levels in the helpers to do the right
thing. In effect, it simply converts the macros to static
inline functions.

Cc: Eric Auger <eric.auger@redhat.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-01 13:50:30 +01:00
Suzuki K Poulose
e55cac5bf2 kvm: arm/arm64: Prepare for VM specific stage2 translations
Right now the stage2 page table for a VM is hard coded, assuming
an IPA of 40bits. As we are about to add support for per VM IPA,
prepare the stage2 page table helpers to accept the kvm instance
to make the right decision for the VM. No functional changes.
Adds stage2_pgd_size(kvm) to replace S2_PGD_SIZE. Also, moves
some of the definitions in arm32 to align with the arm64.
Also drop the _AC() specifier constants wherever possible.

Cc: Christoffer Dall <cdall@kernel.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-01 13:50:30 +01:00
Suzuki K Poulose
7665f3a849 kvm: arm64: Configure VTCR_EL2 per VM
Add support for setting the VTCR_EL2 per VM, rather than hard
coding a value at boot time per CPU. This would allow us to tune
the stage2 page table parameters per VM in the later changes.

We compute the VTCR fields based on the system wide sanitised
feature registers, except for the hardware management of Access
Flags (VTCR_EL2.HA). It is fine to run a system with a mix of
CPUs that may or may not update the page table Access Flags.
Since the bit is RES0 on CPUs that don't support it, the bit
should be ignored on them.

Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <cdall@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-01 13:50:29 +01:00
Suzuki K Poulose
5b6c6742b5 kvm: arm/arm64: Allow arch specific configurations for VM
Allow the arch backends to perform VM specific initialisation.
This will be later used to handle IPA size configuration and per-VM
VTCR configuration on arm64.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-01 13:50:29 +01:00
Suzuki K Poulose
b2df44ffba kvm: arm64: Clean up VTCR_EL2 initialisation
Use the new helper for converting the parange to the physical shift.
Also, add the missing definitions for the VTCR_EL2 register fields
and use them instead of hard coding numbers.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-01 13:50:29 +01:00
Suzuki K Poulose
ce00e3cb4f arm64: Add a helper for PARange to physical shift conversion
On arm64, ID_AA64MMFR0_EL1.PARange encodes the maximum Physical
Address range supported by the CPU. Add a helper to decode this
to actual physical shift. If we hit an unallocated value, return
the maximum range supported by the kernel.
This will be used by KVM to set the VTCR_EL2.T0SZ, as it
is about to move its place. Having this helper keeps the code
movement cleaner.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Christoffer Dall <cdall@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-01 13:50:15 +01:00
Anshuman Khandual
52338088ef arm64/numa: Unify common error path in numa_init()
At present numa_free_distance() is being called before numa_distance is
even initialized with numa_alloc_distance() which is really pointless.
Instead lets call numa_free_distance() on the common error path inside
numa_init() after numa_alloc_distance() has been successful.

Fixes: 1a2db30034 ("arm64, numa: Add NUMA support for arm64 platforms")
Acked-by: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 13:49:52 +01:00
Anshuman Khandual
77cfe95090 arm64/numa: Report correct memblock range for the dummy node
The dummy node ID is marked into all memory ranges on the system. So the
dummy node really extends the entire memblock.memory. Hence report correct
extent information for the dummy node using memblock range helper functions
instead of the range [0LLU, PFN_PHYS(max_pfn) - 1)].

Fixes: 1a2db30034 ("arm64, numa: Add NUMA support for arm64 platforms")
Acked-by: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 13:48:54 +01:00
Anshuman Khandual
359048f91d arm64/mm: Define esr_to_debug_fault_info()
fault_info[] and debug_fault_info[] are static arrays defining memory abort
exception handling functions looking into ESR fault status code encodings.
As esr_to_fault_info() is already available providing fault_info[] array
lookup, it really makes sense to have a corresponding debug_fault_info[]
array lookup function as well. This just adds an equivalent helper function
esr_to_debug_fault_info().

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 13:48:23 +01:00
Anshuman Khandual
dbfe3828a6 arm64/mm: Reorganize arguments for is_el1_permission_fault()
Most memory abort exception handling related functions have the arguments
in the order (addr, esr, regs) except is_el1_permission_fault(). This
changes the argument order in this function as (addr, esr, regs) like
others.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 13:47:31 +01:00
Anshuman Khandual
00bbd5d901 arm64/mm: Use ESR_ELx_FSC macro while decoding fault exception
Just replace hard code value of 63 (0x111111) with an existing macro
ESR_ELx_FSC when parsing for the status code during fault exception.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 13:47:12 +01:00
Marc Zyngier
95b861a4a6 arm64: arch_timer: Add workaround for ARM erratum 1188873
When running on Cortex-A76, a timer access from an AArch32 EL0
task may end up with a corrupted value or register. The workaround for
this is to trap these accesses at EL1/EL2 and execute them there.

This only affects versions r0p0, r1p0 and r2p0 of the CPU.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 13:38:47 +01:00
Marc Zyngier
32a3e635fb arm64: compat: Add CNTFRQ trap handler
Just like CNTVCT, we need to handle userspace trapping into the
kernel if we're decided that the timer wasn't fit for purpose...
64bit userspace is already dealt with, but we're missing the
equivalent compat handling.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 13:36:03 +01:00
Marc Zyngier
50de013d22 arm64: compat: Add CNTVCT trap handler
Since people seem to make a point in breaking the userspace visible
counter, we have no choice but to trap the access. We already do this
for 64bit userspace, but this is lacking for compat. Let's provide
the required handler.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 13:36:01 +01:00
Marc Zyngier
2a8905e18c arm64: compat: Add cp15_32 and cp15_64 handler arrays
We're now ready to start handling CP15 access. Let's add (empty)
arrays for both 32 and 64bit accessors, and the code that deals
with them.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 13:35:59 +01:00
Marc Zyngier
1f1c014035 arm64: compat: Add condition code checks and IT advance
Here's a /really nice/ part of the architecture: a CP15 access is
allowed to trap even if it fails its condition check, and SW must
handle it. This includes decoding the IT state if this happens in
am IT block. As a consequence, SW must also deal with advancing
the IT state machine.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 13:35:56 +01:00
Marc Zyngier
70c63cdfd6 arm64: compat: Add separate CP15 trapping hook
Instead of directly generating an UNDEF when trapping a CP15 access,
let's add a new entry point to that effect (which only generates an
UNDEF for now).

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 13:35:53 +01:00
Marc Zyngier
bd7ac140b8 arm64: Add decoding macros for CP15_32 and CP15_64 traps
So far, we don't have anything to help decoding ESR_ELx when dealing
with ESR_ELx_EC_CP15_{32,64}. As we're about to handle some of those,
let's add some useful macros.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 13:35:50 +01:00
Suzuki K Poulose
9f98ddd668 kvm: arm64: Add helper for loading the stage2 setting for a VM
We load the stage2 context of a guest for different operations,
including running the guest and tlb maintenance on behalf of the
guest. As of now only the vttbr is private to the guest, but this
is about to change with IPA per VM. Add a helper to load the stage2
configuration for a VM, which could do the right thing with the
future changes.

Cc: Christoffer Dall <cdall@kernel.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-10-01 13:08:41 +01:00
Ard Biesheuvel
9376b1e7b6 arm64: remove unused asm/compiler.h header file
arm64 does not define CONFIG_HAVE_ARCH_COMPILER_H, nor does it keep
anything useful in its copy of asm/compiler.h, so let's remove it
before anybody starts using it.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 11:57:04 +01:00
Will Deacon
24951465cb arm64: compat: Provide definition for COMPAT_SIGMINSTKSZ
arch/arm/ defines a SIGMINSTKSZ of 2k, so we should use the same value
for compat tasks.

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Dominik Brodowski <linux@dominikbrodowski.net>
Cc: "Eric W. Biederman" <ebiederm@xmission.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Cc: Oleg Nesterov <oleg@redhat.com>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Reported-by: Steve McIntyre <steve.mcintyre@arm.com>
Tested-by: Steve McIntyre <93sam@debian.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-10-01 11:44:02 +01:00
Manivannan Sadhasivam
e0c27a1066 arm64: actions: Enable PINCTRL in platforms Kconfig
Select PINCTRL for Actions Semi SoCs.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30 19:11:33 +02:00
Saravanan Sekar
01463ac63b arm64: dts: actions: s700: Set UART clock references from CMU
Remove fixed clock in Cubieboard 7 and use Clock Management Unit clocks
for all UART nodes in Actions Semi S700 SoC.

Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Signed-off-by: Saravanan Sekar <sravanhome@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[AF: Moved/added to SoC]
Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30 18:57:23 +02:00
Saravanan Sekar
8ba92cf593 arm64: dts: actions: s700: Add Clock Management Unit
Add Clock Management Unit for Actions Semi S700 SoC.

Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Signed-off-by: Saravanan Sekar <sravanhome@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30 18:55:22 +02:00
Manivannan Sadhasivam
c432aaa2b2 arm64: dts: actions: s900: Add DMA Controller
Add DMA controller node for Actions Semi S900 SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30 18:53:29 +02:00
Manivannan Sadhasivam
07b308eee0 arm64: dts: actions: s900-bubblegum-96: Enable I2C1 and I2C2
Add pinctrl definitions for Actions Semiconductor S900 I2C controllers.
Pinctrl definitions are only available for I2C0, I2C1, and I2C2.
Enable I2C1 and I2C2 exposed on the low speed expansion connector in
Bubblegum-96 board.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[AF: Squashed]
Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30 18:50:42 +02:00
Manivannan Sadhasivam
5eb76e8a29 arm64: dts: actions: s900: Add I2C controller nodes
Add I2C controller nodes for Actions Semiconductor S900 SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[AF: Squashed/added clocks, dropped pinctrl properties for now]
Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30 18:47:13 +02:00
Manivannan Sadhasivam
29ea7bae20 arm64: dts: actions: s900-bubblegum-96: Add gpio line names
Add gpio line names to Actions Semi S900 based Bubblegum-96 board.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30 18:46:07 +02:00
Manivannan Sadhasivam
48d4c88471 arm64: dts: actions: s900: Add gpio properties to pinctrl node
Add gpio properties to pinctrl node for Actions Semi S900 SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30 18:45:56 +02:00
Manivannan Sadhasivam
a1d8219f97 arm64: dts: actions: s900: Add pinctrl node
Add pinctrl nodes for Actions Semi S900 SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30 18:45:37 +02:00
Manivannan Sadhasivam
6bd9ad12a3 arm64: dts: actions: s900: Add SPS node
Add Actions Semi S900 Smart Power System (SPS) node.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30 18:45:27 +02:00
Manivannan Sadhasivam
d3105e47b5 arm64: dts: actions: s900: Source CMU clock for UARTs
Remove fixed clock in Bubblegum-96 board and source CMU (Clock
Management Unit) clock for UART nodes in Actions Semi S900 SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[AF: Move/add clocks to SoC]
Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30 18:42:48 +02:00
Manivannan Sadhasivam
4db4a57fe0 arm64: dts: actions: s900: Add Clock Management Unit nodes
Add Actions Semi S900 Clock Management Unit (CMU) nodes.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-09-30 17:13:11 +02:00
Chen-Yu Tsai
6eeb4180d4
ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device trees
Bananapi released an updated revision of the H3/H5 based Bananapi M2+.
Version 1.2 enables voltage control for the CPU's regulator by using
a GPIO line to toggle a MOSFET that can change the effective resistance
value in the regulator's feedback network.

This patch adds a common .dtsi file for this new revision, which
includes the original common sunxi-bananapi-m2-plus.dtsi file, and
adds the GPIO-controlled regulator and a cpu-supply reference. H3
and H5 variant dts files are added as well.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-09-29 15:58:38 +02:00
Chen-Yu Tsai
80c21c8c8b
arm64: dts: allwinner: h5: Add device tree for Bananapi M2 Plus H5
The Bananapi M2 Plus H5 is a variant of the original Bananapi M2 Plus,
with the H3 SoC replaced with an H5. Everything else is the same.

Add a stub device tree incorporating the shared bananapi-m2-plus dtsi
file.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-09-29 15:57:46 +02:00
Chen-Yu Tsai
bb39ed07e5
arm64: dts: allwinner: h5: Add device node for Mali-450 GPU
The H5 has a Mali-450 GPU with 4 Pixel Processor cores.

Interestingly, while the datasheet lists an interrupt line for the GPU's
PMU, the hardware block itself doesn't seem to have it. Reads from the
PMU address range all return zero, and writes are ignored.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-09-29 15:57:42 +02:00
Leilk Liu
3c2ac5b3eb arm64: dts: Add spi slave dts
This patch adds MT2712 spi slave into device tree.

Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-28 23:05:26 +02:00
Rob Herring
de76e70a8d arm64: use for_each_of_cpu_node iterator
Use the for_each_of_cpu_node iterator to iterate over cpu nodes. This
has the side effect of defaulting to iterating using "cpu" node names in
preference to the deprecated (for FDT) device_type == "cpu".

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2018-09-28 14:25:58 -05:00
Arnd Bergmann
d314e6e26d Renesas ARM64 Based SoC Defconfig Updates for v4.20
* Enable recently upstreamed RZ/G2E (r8a774c0) and RZ/G2M (r8a774a1) SoCs
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Merge tag 'renesas-arm64-defconfig-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/defconfig

Renesas ARM64 Based SoC Defconfig Updates for v4.20

* Enable recently upstreamed RZ/G2E (r8a774c0) and RZ/G2M (r8a774a1) SoCs

* tag 'renesas-arm64-defconfig-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: defconfig: enable R8A774C0 SoC
  arm64: defconfig: enable R8A774A1 SoC

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28 18:02:53 +02:00
Arnd Bergmann
0526b92e3a Second Round of Renesas ARM64 Based SoC DT Updates for v4.20
* Remove unneeded status from thermal nodes
 
 * R-Car Gen 3 SoCs:
   - Use 400kHz for I2C DVFS bus
   - Revise USB2.0 properties
 * R-Car Gen 3 SoC based ULCB boards: Add default bootargs
 * R-Car M3-N (r8a77965) SoC based boards: Enable audio with DMA
 
 * R-Car V3M (r8a77970 and V3H (r8a77980) SoCs:
   - Add compare match timer (CMT) support
   - Add timer pulse unit (TPU) support
 * R-Car V3H (r8a77980) and E3 (r8a77990) SoCs:
   - Attach the SYS-DMAC to the IPMMU
 * E3 (r8a77990) SoC: Add display output support
 * R-Car E3 (r8a77990) based Ebisu board:
   - Enable HDMI and CVBS input, and VGA and HDMI display output
 
 * R-Car D3 (r8a77995) SoC: Add LVDS support
 * R-Car D3 (r8a77995) based Draak board: Enable HDMI display output
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Merge tag 'renesas-arm64-dt2-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Second Round of Renesas ARM64 Based SoC DT Updates for v4.20

* Remove unneeded status from thermal nodes

* R-Car Gen 3 SoCs:
  - Use 400kHz for I2C DVFS bus
  - Revise USB2.0 properties
* R-Car Gen 3 SoC based ULCB boards: Add default bootargs
* R-Car M3-N (r8a77965) SoC based boards: Enable audio with DMA

* R-Car V3M (r8a77970 and V3H (r8a77980) SoCs:
  - Add compare match timer (CMT) support
  - Add timer pulse unit (TPU) support
* R-Car V3H (r8a77980) and E3 (r8a77990) SoCs:
  - Attach the SYS-DMAC to the IPMMU
* E3 (r8a77990) SoC: Add display output support
* R-Car E3 (r8a77990) based Ebisu board:
  - Enable HDMI and CVBS input, and VGA and HDMI display output

* R-Car D3 (r8a77995) SoC: Add LVDS support
* R-Car D3 (r8a77995) based Draak board: Enable HDMI display output

* tag 'renesas-arm64-dt2-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: renesas: r8a77965: Add Sound and Audio DMAC device nodes
  arm64: dts: renesas: r8a77995: draak: Enable HDMI display output
  arm64: dts: renesas: r8a77990: ebisu: Enable VGA and HDMI outputs
  arm64: dts: renesas: r8a77995: Add LVDS support
  arm64: dts: renesas: r8a77990: Add display output support
  arm64: dts: renesas: r8a779{7|8}0: add TPU support
  arm64: dts: renesas: revise properties for R-Car Gen3 SoCs' usb 2.0
  arm64: dts: renesas: ulcb: add default bootargs
  arm64: dts: renesas: r8a779{7|8}0: add CMT support
  arm64: dts: renesas: gen3: use 400kHz for I2C DVFS bus
  arm64: dts: renesas: r8a77980: Attach the SYS-DMAC to the IPMMU
  arm64: dts: renesas: r8a77990: Attach the SYS-DMAC to the IPMMU
  arm64: dts: renesas: ebisu: Add HDMI and CVBS input
  arm64: dts: renesas: Remove unneeded status from thermal nodes

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28 17:42:26 +02:00
Arnd Bergmann
f62309c873 arm64: tegra: Device tree changes for v4.20-rc1
This contains mostly device tree changes to support faster SDHCI modes
 on Tegra210 and Tegra186.
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Merge tag 'tegra-for-4.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt

arm64: tegra: Device tree changes for v4.20-rc1

This contains mostly device tree changes to support faster SDHCI modes
on Tegra210 and Tegra186.

* tag 'tegra-for-4.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: I2C on Tegra194 is not compatible with Tegra114
  arm64: dts: tegra186: Enable HS400
  arm64: dts: tegra210: Enable HS400
  arm64: dts: tegra186: Add SDMMC4 DQS trim value
  arm64: dts: tegra210: Add SDMMC4 DQS trim value
  arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4
  arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4
  arm64: dts: tegra186: Add SDHCI tap and trim values
  arm64: dts: tegra210: Add SDHCI tap and trim values
  arm64: dts: tegra186: Add sdmmc pad auto calibration offsets
  arm64: dts: tegra210: Add sdmmc pad auto calibration offsets
  arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1
  arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply
  arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V
  arm64: dts: Add Tegra186 sdmmc pinctrl voltage states
  arm64: dts: Add Tegra210 sdmmc pinctrl voltage states

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28 17:41:26 +02:00
Heiko Stuebner
9485107ae8 arm64: defconfig: enable Rockchip Innosilicon hdmiphy
The rk3228 and rk3328 socs use an MMIO-connected hdmi-phy from Innosilicon.
So enable the necessary driver as module.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-28 13:19:57 +02:00
Heiko Stuebner
e78d53c7b2 arm64: dts: rockchip: enable display nodes on rk3328-rock64
Enable necessary nodes to get output on the hdmi port of the board.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-28 13:18:37 +02:00
Heiko Stuebner
725e351c26 arm64: dts: rockchip: add rk3328 display nodes
Add the chain of display nodes from the core display-subsystem
through the one vop to the dw-hdmi output.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Robin Murphy <robin.murphy@arm.com>

changes in v3:
- drop reg from hdmi-in-port
changes in v2:
- remove trailing 0 from vop irq
2018-09-28 13:16:30 +02:00
Heiko Stuebner
6c69dfe2af arm64: dts: rockchip: add Innosilicon hdmi phy node to rk3328
The rk3328 uses a hdmiphy from Innosilicon, so add the necessary node
to the rk3328 soc devicetree.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Robin Murphy <robin.murphy@arm.com>
2018-09-28 13:16:23 +02:00
Arnd Bergmann
4bef2317b4 Amlogic ARM64 DT updates for v4.20, round 2
- new SoC support: basic support for G12A family
 - new board: Amlogic U200 board, using G12A SoC
 - fix SPI bus warnings from new dtc updates
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Merge tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt

Amlogic ARM64 DT updates for v4.20, round 2
- new SoC support: basic support for G12A family
- new board: Amlogic U200 board, using G12A SoC
- fix SPI bus warnings from new dtc updates

* tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support
  dt-bindings: arm: amlogic: Add Meson G12A binding
  arm64: dts: meson: Fix erroneous SPI bus warnings

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28 12:48:34 +02:00
Arnd Bergmann
262c083d13 Berlin64 DT changes for v4.20
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Merge tag 'berlin64-dt-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux-berlin into next/dt

Berlin64 DT changes for v4.20

* tag 'berlin64-dt-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux-berlin:
  arm64: dts: synaptics: add dtsi file for Synaptics AS370 SoC
  dt-bindings: arm: syna: add support for the AS370 SoC
  dt-bindings: arm: move berlin binding documentation to syna.txt

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28 12:37:18 +02:00
Rob Herring
09bae3b64c arm64: dts: lg: Fix SPI controller node names
SPI controller nodes should be named 'spi' rather than 'ssp'. Fixing the
name enables dtc SPI bus checks.

Cc: Chanho Min <chanho.min@lge.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28 12:33:21 +02:00
Rob Herring
e9f0878c4b arm64: dts: amd: Fix SPI bus warnings
dtc has new checks for SPI buses. Fix the warnings in node names.

arch/arm64/boot/dts/amd/amd-overdrive.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'
arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'
arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'

Cc: Brijesh Singh <brijeshkumar.singh@amd.com>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28 12:32:51 +02:00
Marek Behún
620cfb31ba arm64: dts: marvell: armada-37xx: add nodes to support watchdog
This adds the system controller node for CPU Miscellaneous Registers
(which is needed for the watchdog node) and the watchdog node.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-09-28 10:00:17 +02:00
Eric W. Biederman
c852680959 signal/arm64: Use send_sig_fault where appropriate
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27 21:55:23 +02:00
Eric W. Biederman
f3a900b341 signal/arm64: Add and use arm64_force_sig_ptrace_errno_trap
Add arm64_force_sig_ptrace_errno_trap for consistency with
arm64_force_sig_fault and use it where appropriate.

This adds the show_signal logic to the force_sig_errno_trap case,
where it was apparently overlooked earlier.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27 21:55:15 +02:00
Eric W. Biederman
2627f0347c signal/arm64: In ptrace_hbptriggered name the signal description string
This will let the description be reused shortly.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27 21:55:08 +02:00
Eric W. Biederman
009f608ab2 signal/arm64: Remove arm64_force_sig_info
The function has no more callers so remove it.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27 21:55:00 +02:00
Eric W. Biederman
b4d5557caa signal/arm64: Add and use arm64_force_sig_mceerr as appropriate
Add arm64_force_sig_mceerr for consistency with arm64_force_sig_fault,
and use it in the one location that can take advantage of it.

This removes the fiddly filling out of siginfo before sending a signal
reporting an memory error to userspace.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27 21:54:51 +02:00
Eric W. Biederman
feca355b3d signal/arm64: Add and use arm64_force_sig_fault where appropriate
Wrap force_sig_fault with a helper that calls arm64_show_signal
and call arm64_force_sig_fault where appropraite.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
2018-09-27 21:54:43 +02:00
Eric W. Biederman
559d8d91a8 signal/arm64: Only call set_thread_esr once in do_page_fault
This code is truly common between the signal sending cases so share it.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
2018-09-27 21:54:33 +02:00
Eric W. Biederman
2d2837fab5 signal/arm64: Only perform one esr_to_fault_info call in do_page_fault
As this work is truly common between all of the signal sending cases
there is no need to repeat it between the different cases.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
2018-09-27 21:54:26 +02:00
Eric W. Biederman
effb093ad2 signal/arm64: Expand __do_user_fault and remove it
Not all of the signals passed to __do_user_fault can be handled
the same way so expand the now tiny __do_user_fault in it's callers
and remove it.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27 21:54:18 +02:00
Eric W. Biederman
aefab2b4c0 signal/arm64: For clarity separate the 3 signal sending cases in do_page_fault
It gets easy to confuse what is going on when some code is shared and some not
so stop sharing the trivial bits of signal generation to make future updates
easier to understand.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27 21:54:10 +02:00
Eric W. Biederman
9ea3a9743c signal/arm64: Consolidate the two hwpoison cases in do_page_fault
These two cases are practically the same and use siginfo differently
from the other signals sent from do_page_fault.  So consolidate them
to make future changes easier.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27 21:54:02 +02:00
Eric W. Biederman
f29ad209e4 signal/arm64: Factor set_thread_esr out of __do_user_fault
This pepares for sending signals with something other than
arm64_force_sig_info.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27 21:53:54 +02:00
Eric W. Biederman
1628a7cc85 signal/arm64: Factor out arm64_show_signal from arm64_force_sig_info
Filling in siginfo is error prone and so it is wise to use more
specialized helpers to do that work.  Factor out the arm specific
unhandled signal reporting from the work of delivering a signal so
the code can be modified to use functions that take the information
to fill out siginfo as parameters.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27 21:53:46 +02:00
Eric W. Biederman
24b8f79dd8 signal/arm64: Remove unneeded tsk parameter from arm64_force_sig_info
Every caller passes in current for tsk so there is no need to pass
tsk.  Instead make tsk a local variable initialized to current.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27 21:53:35 +02:00
Eric W. Biederman
6fa998e83e signal/arm64: Push siginfo generation into arm64_notify_die
Instead of generating a struct siginfo before calling arm64_notify_die
pass the signal number, tne sicode and the fault address into
arm64_notify_die and have it call force_sig_fault instead of
force_sig_info to let the generic code generate the struct siginfo.

This keeps code passing just the needed information into
siginfo generating code, making it easier to see what
is happening and harder to get wrong.  Further by letting
the generic code handle the generation of struct siginfo
it reduces the number of sites generating struct siginfo
making it possible to review them and verify that all
of the fiddly details for a structure passed to userspace
are handled properly.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-09-27 21:52:54 +02:00
Borislav Petkov
d913e8966a Merge branch 'tip-x86-hygon' into edac-for-4.20
... to pick up a dependent commit and share it with the tip tree, branch
tip:x86/cpu.

Signed-off-by: Borislav Petkov <bp@suse.de>
2018-09-27 18:36:24 +02:00
Ard Biesheuvel
c296146c05 arm64/kernel: jump_label: Switch to relative references
On a randomly chosen distro kernel build for arm64, vmlinux.o shows the
following sections, containing jump label entries, and the associated
RELA relocation records, respectively:

  ...
  [38088] __jump_table      PROGBITS         0000000000000000  00e19f30
       000000000002ea10  0000000000000000  WA       0     0     8
  [38089] .rela__jump_table RELA             0000000000000000  01fd8bb0
       000000000008be30  0000000000000018   I      38178   38088     8
  ...

In other words, we have 190 KB worth of 'struct jump_entry' instances,
and 573 KB worth of RELA entries to relocate each entry's code, target
and key members. This means the RELA section occupies 10% of the .init
segment, and the two sections combined represent 5% of vmlinux's entire
memory footprint.

So let's switch from 64-bit absolute references to 32-bit relative
references for the code and target field, and a 64-bit relative
reference for the 'key' field (which may reside in another module or the
core kernel, which may be more than 4 GB way on arm64 when running with
KASLR enable): this reduces the size of the __jump_table by 33%, and
gets rid of the RELA section entirely.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-s390@vger.kernel.org
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Jessica Yu <jeyu@kernel.org>
Link: https://lkml.kernel.org/r/20180919065144.25010-4-ard.biesheuvel@linaro.org
2018-09-27 17:56:47 +02:00
Thor Thayer
74121b9aa3 arm64: dts: stratix10: Correct System Manager register size
Correct the register size of the System Manager node.

Cc: stable@vger.kernel.org
Fixes: 78cd6a9d8e ("arm64: dts: Add base stratix 10 dtsi")
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-09-27 09:33:24 -05:00
Rodrigo Exterckötter Tjäder
679294497b arm64: dts: allwinner: a64: a64-olinuxino: set the PHY TX delay
The PHY found on the A64-OLinuXino requires a TX delay in order to
operate properly. Olimex uses a 600ps second delay in their BSP, and
that has been found to work, so let's use that value in the current
DT.

Signed-off-by: Rodrigo Exterckötter Tjäder <rodrigo@tjader.xyz>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-09-27 18:20:35 +08:00
Jisheng Zhang
087682f5a7 arm64: dts: synaptics: add dtsi file for Synaptics AS370 SoC
Add initial dtsi file to support Synaptics AS370 SoC with quad
Cortex-A53 CPUs.

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
2018-09-27 14:48:43 +08:00
Suzuki K Poulose
70a39be676 arm64: dts: msm8916: Update coresight bindings for hardware ports
Switch to updated coresight bindings for hw ports

Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-26 11:59:36 -05:00
Arnd Bergmann
ba61ab1a23 arm64: zynqmp: SoC changes for v4.20
- Adding firmware API for SoC with debugfs interface
   Firmware driver communicates to Platform Management Unit (PMU) by using
   SMC instructions routed to Arm Trusted Firmware (ATF). Initial version
   adds support for base firmware driver with query and clock APIs.
 
   EEMI spec is available here:
   https://www.xilinx.com/support/documentation/user_guides/ug1200-eemi-api.pdf
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Merge tag 'zynqmp-soc-for-v4.20-v2' of https://github.com/Xilinx/linux-xlnx into next/drivers

arm64: zynqmp: SoC changes for v4.20

- Adding firmware API for SoC with debugfs interface
  Firmware driver communicates to Platform Management Unit (PMU) by using
  SMC instructions routed to Arm Trusted Firmware (ATF). Initial version
  adds support for base firmware driver with query and clock APIs.

  EEMI spec is available here:
  https://www.xilinx.com/support/documentation/user_guides/ug1200-eemi-api.pdf

* tag 'zynqmp-soc-for-v4.20-v2' of https://github.com/Xilinx/linux-xlnx:
  firmware: xilinx: Add debugfs for query data API
  firmware: xilinx: Add debugfs interface
  firmware: xilinx: Add clock APIs
  firmware: xilinx: Add query data API
  firmware: xilinx: Add Zynqmp firmware driver
  dt-bindings: firmware: Add bindings for ZynqMP firmware

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-26 17:18:53 +02:00
Christoph Hellwig
3cfa210bf3 xen: don't include <xen/xen.h> from <asm/io.h> and <asm/dma-mapping.h>
Nothing Xen specific in these headers, which get included from a lot
of code in the kernel.  So prune the includes and move them to the
Xen-specific files that actually use them instead.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
2018-09-26 08:45:18 -06:00
Christoph Hellwig
c39ae60dfb block: remove ARCH_BIOVEC_PHYS_MERGEABLE
Take the Xen check into the core code instead of delegating it to
the architectures.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
2018-09-26 08:45:11 -06:00
Christoph Hellwig
20e3267601 xen: provide a prototype for xen_biovec_phys_mergeable in xen.h
Having multiple externs in arch headers is not a good way to provide
a common interface.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
2018-09-26 08:45:10 -06:00
Thierry Reding
d9fd22447b arm64: tegra: I2C on Tegra194 is not compatible with Tegra114
Tegra194 contains a version of the I2C controller that is no longer
compatible with the version found in Tegra114.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26 15:50:59 +02:00
Antoine Tenart
dd0da407bb arm64: dts: marvell: armada-cp110: describe more PPv2 interrupts
This patch describes 3 additional interrupts per PPv2 port. Those
interrupts will be used later in future versions of the Marvell PPv2
driver, and now the device tree description matches the hardware
capabilities.

Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-09-26 14:29:46 +02:00
Antoine Tenart
eeee84f7a6 arm64: dts: marvell: armada-cp110: change the PPv2 IRQ names
This patch changes the PPv2 IRQ names in the CP110 device tree to match
a corresponding change in the Marvell PPv2 driver. The reason this was
updated is the IRQ where names after Tx/Rx interrupts, but this is not
true and can be configured. A following patch will add more of them and
the names wouldn't make sense.

Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-09-26 14:29:23 +02:00
Baruch Siach
a612083327 arm64: dts: add support for SolidRun Clearfog GT 8K
The SolidRun Clearfog GT-8K is based on Marvell Armada 8040 SoC.

  https://wiki.solid-run.com/doku.php?id=products:a8040:clearfoggt8k

The following devices were tested with this DT on top of kernel
v4.19-rc4:

  * 1GB Ethernet WAN

  * 4 ports 1GB Ethernet switch (2.5GB uplink)

  * SFP port

  * SATA on CON3 PCIe slot

  * USB3 type A port

  * SD card and eMMC

  * 2 LEDs

  * 2 push buttons

[gregory: fix block comment alignement]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-09-26 14:23:59 +02:00
Heiko Stuebner
91e75bde63 arm64: dts: rockchip: add missing address and size cells for rk3399 mipi dsi
DSI controllers are also the hosts of their dsi bus and therefore contain
nodes describing the attached panels with their reg properties containing
the virtual ids.

The dsi controller nodes on rk3399 lacked the #address-cells and #size-cells
for these subnodes, so add them.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-26 13:39:18 +02:00
Chen-Yu Tsai
cd7ab133db arm64: dts: rockchip: Enable SPI NOR flash on Rock64
The Pine64 Rock64 board comes with a GigaDevice GD25Q128CSIG
or GD25Q127CSIG chip, which is a 128 Mbit SPI NOR flash chip
that supports the JEDEC read-ID command.

This patch enables the SPI controller and adds a device node
for the flash chip using the generic "jedec,spi-nor" comaptible.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-26 13:37:52 +02:00
Akash Gajjar
e4f3fb4909 arm64: dts: rockchip: add initial dts support for Rockpro64
Rockpro64 is a rockchip RK3399 based board from pine64.org.
This patch adds basic device node support for Rockpro64 board and make it able
to bring up.

Peripheral Works
- Sdcard
- USB 2.0, 3.0
- Leds
- Ethernet
- Debug console

Not working:
- USB Type-C

Signed-off-by: Akash Gajjar <Akash_Gajjar@mentor.com>
Acked-by: Deepak Das <Deepak_Das@mentor.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-09-26 13:31:55 +02:00
Takeshi Kihara
158928f38e arm64: dts: renesas: r8a77965: Add Sound and Audio DMAC device nodes
Based on a similar patch of the R8A7796 device tree
by Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-26 12:31:04 +02:00
Ulrich Hecht
bcf3003438 arm64: dts: renesas: r8a77995: draak: Enable HDMI display output
Adds LVDS decoder, HDMI encoder and connector for the Draak board.

The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and
EXTAL externals clocks. Two of them are provided to the SoC on the Draak
board, hook them up in DT.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-26 11:16:41 +02:00
Laurent Pinchart
74fe39abbf arm64: dts: renesas: r8a77990: ebisu: Enable VGA and HDMI outputs
Add the LVDS decoder, HDMI encoder, VGA encoder and HDMI and VGA
connectors, and wire up the display-related nodes with clocks, pinmux
and regulators.

The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and
EXTAL externals clocks. Two of them are provided to the SoC on the Ebisu
board, hook them up in DT.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-26 11:14:22 +02:00
Kieran Bingham
0dc733988b arm64: dts: renesas: r8a77995: Add LVDS support
The r8a77995 D3 platform has 2 LVDS channels connected to the DU.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
[uli: moved lvds* into the soc node, added PM domains, resets]
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-26 11:13:39 +02:00
Jianxin Pan
9c8c52f7cb arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support
Try to add basic DT support for the Amlogic's Meson-G12A S905D2 SoC,
which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.

Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-26 02:04:58 -07:00