DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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/*
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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* Copyright (c) 2007-2008 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef __INTEL_DRV_H__
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#define __INTEL_DRV_H__
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2014-05-29 04:39:03 +07:00
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#include <linux/async.h>
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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#include <linux/i2c.h>
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2013-08-07 02:32:18 +07:00
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#include <linux/hdmi.h>
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2017-02-01 22:36:40 +07:00
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#include <linux/sched/clock.h>
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2012-10-03 00:01:07 +07:00
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#include <drm/i915_drm.h>
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2009-09-11 05:28:06 +07:00
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#include "i915_drv.h"
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2012-10-03 00:01:07 +07:00
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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2016-11-29 01:51:09 +07:00
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#include <drm/drm_encoder.h>
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2012-10-03 00:01:07 +07:00
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#include <drm/drm_fb_helper.h>
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2016-05-03 02:08:23 +07:00
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#include <drm/drm_dp_dual_mode_helper.h>
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2014-05-02 11:02:48 +07:00
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#include <drm/drm_dp_mst_helper.h>
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2014-09-06 03:04:46 +07:00
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#include <drm/drm_rect.h>
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2015-03-20 21:18:01 +07:00
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#include <drm/drm_atomic.h>
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2010-08-07 17:01:35 +07:00
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2013-03-28 06:03:25 +07:00
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/**
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* _wait_for - magic (register) wait macro
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*
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* Does the right thing for modeset paths when run under kdgb or similar atomic
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* contexts. Note that it's important that we check the condition again after
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* having timed out, since the timeout could be due to preemption or similar and
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* we've never had a chance to check the condition before the timeout.
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*/
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2017-11-24 20:00:30 +07:00
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#define _wait_for(COND, US, Wmin, Wmax) ({ \
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2016-03-03 21:36:41 +07:00
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unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
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2017-11-24 20:00:30 +07:00
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long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
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2016-09-14 19:10:33 +07:00
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int ret__; \
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2017-11-15 04:56:55 +07:00
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might_sleep(); \
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2016-09-14 19:10:33 +07:00
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for (;;) { \
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bool expired__ = time_after(jiffies, timeout__); \
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if (COND) { \
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ret__ = 0; \
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break; \
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} \
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if (expired__) { \
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ret__ = -ETIMEDOUT; \
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2010-08-07 17:01:35 +07:00
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break; \
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} \
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2017-11-24 20:00:30 +07:00
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usleep_range(wait__, wait__ * 2); \
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if (wait__ < (Wmax)) \
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wait__ <<= 1; \
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2010-08-07 17:01:35 +07:00
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} \
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ret__; \
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})
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2017-11-24 20:00:30 +07:00
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#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
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2016-03-03 21:36:41 +07:00
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2016-03-03 23:21:27 +07:00
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/* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
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#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
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2016-06-29 18:27:22 +07:00
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# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
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2016-03-03 23:21:27 +07:00
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#else
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2016-06-29 18:27:22 +07:00
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# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
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2016-03-03 23:21:27 +07:00
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#endif
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2016-06-29 18:27:22 +07:00
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#define _wait_for_atomic(COND, US, ATOMIC) \
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({ \
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int cpu, ret, timeout = (US) * 1000; \
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u64 base; \
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_WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
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if (!(ATOMIC)) { \
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preempt_disable(); \
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cpu = smp_processor_id(); \
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} \
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base = local_clock(); \
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for (;;) { \
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u64 now = local_clock(); \
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if (!(ATOMIC)) \
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preempt_enable(); \
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if (COND) { \
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ret = 0; \
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break; \
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} \
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if (now - base >= timeout) { \
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ret = -ETIMEDOUT; \
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2016-03-03 23:21:27 +07:00
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break; \
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} \
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cpu_relax(); \
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2016-06-29 18:27:22 +07:00
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if (!(ATOMIC)) { \
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preempt_disable(); \
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if (unlikely(cpu != smp_processor_id())) { \
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timeout -= now - base; \
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cpu = smp_processor_id(); \
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base = local_clock(); \
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} \
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} \
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2016-03-03 23:21:27 +07:00
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} \
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2016-06-29 18:27:22 +07:00
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ret; \
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})
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#define wait_for_us(COND, US) \
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({ \
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int ret__; \
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BUILD_BUG_ON(!__builtin_constant_p(US)); \
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if ((US) > 10) \
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2017-11-24 20:00:30 +07:00
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ret__ = _wait_for((COND), (US), 10, 10); \
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2016-06-29 18:27:22 +07:00
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else \
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ret__ = _wait_for_atomic((COND), (US), 0); \
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2016-03-03 23:21:27 +07:00
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ret__; \
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})
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2017-04-18 17:52:11 +07:00
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#define wait_for_atomic_us(COND, US) \
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({ \
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BUILD_BUG_ON(!__builtin_constant_p(US)); \
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BUILD_BUG_ON((US) > 50000); \
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_wait_for_atomic((COND), (US), 1); \
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})
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#define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
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2010-08-23 23:43:35 +07:00
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2014-01-10 22:10:20 +07:00
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#define KHz(x) (1000 * (x))
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#define MHz(x) KHz(1000 * (x))
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2010-09-08 02:54:59 +07:00
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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/*
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* Display related stuff
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*/
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/* store information about an Ixxx DVO */
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/* The i830->i865 use multiple DVOs with multiple i2cs */
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/* the i915, i945 have a single sDVO i2c bus - which is different */
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#define MAX_OUTPUTS 6
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/* maximum connectors per crtcs in the mode set */
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2014-03-10 18:36:23 +07:00
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/* Maximum cursor sizes */
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#define GEN2_CURSOR_WIDTH 64
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#define GEN2_CURSOR_HEIGHT 64
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2014-03-28 21:17:49 +07:00
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#define MAX_CURSOR_WIDTH 256
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#define MAX_CURSOR_HEIGHT 256
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2014-03-10 18:36:23 +07:00
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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#define INTEL_I2C_BUS_DVO 1
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#define INTEL_I2C_BUS_SDVO 2
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/* these are outputs from the chip - integrated only
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external chips are via DVO or SDVO output */
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2014-10-28 02:47:52 +07:00
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enum intel_output_type {
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INTEL_OUTPUT_UNUSED = 0,
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INTEL_OUTPUT_ANALOG = 1,
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INTEL_OUTPUT_DVO = 2,
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INTEL_OUTPUT_SDVO = 3,
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INTEL_OUTPUT_LVDS = 4,
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INTEL_OUTPUT_TVOUT = 5,
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INTEL_OUTPUT_HDMI = 6,
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2016-06-23 01:57:06 +07:00
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INTEL_OUTPUT_DP = 7,
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2014-10-28 02:47:52 +07:00
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INTEL_OUTPUT_EDP = 8,
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INTEL_OUTPUT_DSI = 9,
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2017-10-28 02:31:24 +07:00
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INTEL_OUTPUT_DDI = 10,
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2014-10-28 02:47:52 +07:00
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INTEL_OUTPUT_DP_MST = 11,
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};
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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#define INTEL_DVO_CHIP_NONE 0
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#define INTEL_DVO_CHIP_LVDS 1
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#define INTEL_DVO_CHIP_TMDS 2
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#define INTEL_DVO_CHIP_TVOUT 4
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2014-04-14 12:48:24 +07:00
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#define INTEL_DSI_VIDEO_MODE 0
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#define INTEL_DSI_COMMAND_MODE 1
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2013-08-27 19:12:17 +07:00
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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struct intel_framebuffer {
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struct drm_framebuffer base;
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2010-11-09 02:18:58 +07:00
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struct drm_i915_gem_object *obj;
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2016-02-16 03:54:47 +07:00
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struct intel_rotation_info rot_info;
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drm/i915: Rewrite fb rotation GTT handling
Redo the fb rotation handling in order to:
- eliminate the NV12 special casing
- handle fb->offsets[] properly
- make the rotation handling easier for the plane code
To achieve these goals we reduce intel_rotation_info to only contain
(for each plane) the rotated view width,height,stride in tile units,
and the page offset into the object where the plane starts. Each plane
is handled exactly the same way, no special casing for NV12 or other
formats. We then store the computed rotation_info under
intel_framebuffer so that we don't have to recompute it again.
To handle fb->offsets[] we treat them as a linear offsets and convert
them to x/y offsets from the start of the relevant GTT mapping (either
normal or rotated). We store the x/y offsets under intel_framebuffer,
and for some extra convenience we also store the rotated pitch (ie.
tile aligned plane height). So for each plane we have the normal
x/y offsets, rotated x/y offsets, and the rotated pitch. The normal
pitch is available already in fb->pitches[].
While we're gathering up all that extra information, we can also easily
compute the storage requirements for the framebuffer, so that we can
check that the object is big enough to hold it.
When it comes time to deal with the plane source coordinates, we first
rotate the clipped src coordinates to match the relevant GTT view
orientation, then add to them the fb x/y offsets. Next we compute
the aligned surface page offset, and as a result we're left with some
residual x/y offsets. Finally, if required by the hardware, we convert
the remaining x/y offsets into a linear offset.
For gen2/3 we simply skip computing the final page offset, and just
convert the src+fb x/y offsets directly into a linear offset since
that's what the hardware wants.
After this all platforms, incluing SKL+, compute these things in exactly
the same way (excluding alignemnt differences).
v2: Use BIT(DRM_ROTATE_270) instead of ROTATE_270 when rotating
plane src coordinates
Drop some spurious changes that got left behind during
development
v3: Split out more changes to prep patches (Daniel)
s/intel_fb->plane[].foo.bar/intel_fb->foo[].bar/ for brevity
Rename intel_surf_gtt_offset to intel_fb_gtt_offset
Kill the pointless 'plane' parameter from intel_fb_gtt_offset()
v4: Fix alignment vs. alignment-1 when calling
_intel_compute_tile_offset() from intel_fill_fb_info()
Pass the pitch in tiles in
stad of pixels to intel_adjust_tile_offset() from intel_fill_fb_info()
Pass the full width/height of the rotated area to
drm_rect_rotate() for clarity
Use u32 for more offsets
v5: Preserve the upper_32_bits()/lower_32_bits() handling for the
fb ggtt offset (Sivakumar)
v6: Rebase due to drm_plane_state src/dst rects
Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470821001-25272-2-git-send-email-ville.syrjala@linux.intel.com
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-09-15 17:16:41 +07:00
|
|
|
|
|
|
|
/* for each plane in the normal GTT view */
|
|
|
|
struct {
|
|
|
|
unsigned int x, y;
|
|
|
|
} normal[2];
|
|
|
|
/* for each plane in the rotated GTT view */
|
|
|
|
struct {
|
|
|
|
unsigned int x, y;
|
|
|
|
unsigned int pitch; /* pixels */
|
|
|
|
} rotated[2];
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
};
|
|
|
|
|
2010-08-26 04:45:57 +07:00
|
|
|
struct intel_fbdev {
|
|
|
|
struct drm_fb_helper helper;
|
2014-02-08 03:10:38 +07:00
|
|
|
struct intel_framebuffer *fb;
|
2016-08-15 16:49:06 +07:00
|
|
|
struct i915_vma *vma;
|
2016-06-21 15:16:54 +07:00
|
|
|
async_cookie_t cookie;
|
2014-03-07 23:57:51 +07:00
|
|
|
int preferred_bpp;
|
2010-08-26 04:45:57 +07:00
|
|
|
};
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
|
2010-03-26 01:11:14 +07:00
|
|
|
struct intel_encoder {
|
2010-09-09 21:14:28 +07:00
|
|
|
struct drm_encoder base;
|
drm/i915: stage modeset output changes
This is the core of the new modeset logic.
The current code which is based upon the crtc helper code first
updates all the link of the new display pipeline and then calls the
lower-level set_mode function to execute the required callbacks to get
there. The issue with this approach is that for disabling we need to
know the _current_ display pipe state, not the new one.
Hence we need to stage the new state of the display pipe and only
update it once we have disabled the current configuration and before we
start to update the hw registers with the new configuration.
This patch here just prepares the ground by switching the new output
state computation to these staging pointers. To make it clearer,
rename the old update_output_state function to stage_output_state.
A few peculiarities:
- We're also calling the set_mode function at various places to update
properties. Hence after a successfule modeset we need to stage the
current configuration (for otherwise we might fall back again). This
happens automatically because as part of the (successful) modeset we
need to copy the staged state to the real one. But for the hw
readout code we need to make sure that this happens, too.
- Teach the new staged output state computation code the required
smarts to handle the disabling of outputs. The current code handles
this in a special case, but to better handle global modeset changes
covering more than one crtc, we want to do this all in the same
low-level modeset code.
- The actual modeset code is still a bit ugly and wants to know the new
crtc->enabled state a bit early. Follow-on patches will clean that
up, for now we have to apply the staged output configuration early,
outside of the set_mode functions.
- Improve/add comments in stage_output_state.
Essentially all that is left to do now is move the disabling code into
set_mode and then move the staged state update code also into
set_mode, at the right place between disabling things and calling the
mode_set callbacks for the new configuration.
v2: Disabling a crtc works by passing in a NULL mode or fb, userspace
doesn't hand in the list of connectors. We therefore need to detect
this case manually and tear down all the output links.
v3: Properly update the output staging pointers after having read out
the hw state.
v4: Simplify the code, add more DRM_DEBUG_KMS output and check a few
assumptions with WARN_ON. Essentially all things that I've noticed
while debugging issues in other places of the code.
v4: Correctly disable the old set of connectors when enabling an
already enabled crtc on a new set of crtc. Reported by Paulo Zanoni.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-07-06 03:34:27 +07:00
|
|
|
|
2014-10-28 02:47:52 +07:00
|
|
|
enum intel_output_type type;
|
2016-09-20 08:24:38 +07:00
|
|
|
enum port port;
|
2014-03-03 21:15:28 +07:00
|
|
|
unsigned int cloneable;
|
2010-03-26 01:11:14 +07:00
|
|
|
void (*hot_plug)(struct intel_encoder *);
|
2017-10-28 02:31:24 +07:00
|
|
|
enum intel_output_type (*compute_output_type)(struct intel_encoder *,
|
|
|
|
struct intel_crtc_state *,
|
|
|
|
struct drm_connector_state *);
|
2013-03-27 06:44:52 +07:00
|
|
|
bool (*compute_config)(struct intel_encoder *,
|
2016-08-09 22:04:05 +07:00
|
|
|
struct intel_crtc_state *,
|
|
|
|
struct drm_connector_state *);
|
2016-08-09 22:04:04 +07:00
|
|
|
void (*pre_pll_enable)(struct intel_encoder *,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *,
|
|
|
|
const struct drm_connector_state *);
|
2016-08-09 22:04:04 +07:00
|
|
|
void (*pre_enable)(struct intel_encoder *,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *,
|
|
|
|
const struct drm_connector_state *);
|
2016-08-09 22:04:04 +07:00
|
|
|
void (*enable)(struct intel_encoder *,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *,
|
|
|
|
const struct drm_connector_state *);
|
2016-08-09 22:04:04 +07:00
|
|
|
void (*disable)(struct intel_encoder *,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *,
|
|
|
|
const struct drm_connector_state *);
|
2016-08-09 22:04:04 +07:00
|
|
|
void (*post_disable)(struct intel_encoder *,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *,
|
|
|
|
const struct drm_connector_state *);
|
2016-08-09 22:04:04 +07:00
|
|
|
void (*post_pll_disable)(struct intel_encoder *,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *,
|
|
|
|
const struct drm_connector_state *);
|
2012-07-02 18:10:34 +07:00
|
|
|
/* Read out the current hw state of this connector, returning true if
|
|
|
|
* the encoder is active. If the encoder is enabled it also set the pipe
|
|
|
|
* it is connected to in the pipe parameter. */
|
|
|
|
bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
|
2013-05-15 07:08:26 +07:00
|
|
|
/* Reconstructs the equivalent mode flags for the current hardware
|
2013-06-12 16:47:24 +07:00
|
|
|
* state. This must be called _after_ display->get_pipe_config has
|
2013-06-28 11:59:06 +07:00
|
|
|
* pre-filled the pipe config. Note that intel_encoder->base.crtc must
|
|
|
|
* be set correctly before calling this function. */
|
2013-05-15 07:08:26 +07:00
|
|
|
void (*get_config)(struct intel_encoder *,
|
2015-01-15 19:55:21 +07:00
|
|
|
struct intel_crtc_state *pipe_config);
|
2017-02-24 21:19:59 +07:00
|
|
|
/* Returns a mask of power domains that need to be referenced as part
|
|
|
|
* of the hardware state readout code. */
|
|
|
|
u64 (*get_power_domains)(struct intel_encoder *encoder);
|
2014-08-18 18:42:45 +07:00
|
|
|
/*
|
|
|
|
* Called during system suspend after all pending requests for the
|
|
|
|
* encoder are flushed (for example for DP AUX transactions) and
|
|
|
|
* device interrupts are disabled.
|
|
|
|
*/
|
|
|
|
void (*suspend)(struct intel_encoder *);
|
2009-08-24 12:50:24 +07:00
|
|
|
int crtc_mask;
|
2013-02-26 00:06:49 +07:00
|
|
|
enum hpd_pin hpd_pin;
|
2017-02-22 13:34:27 +07:00
|
|
|
enum intel_display_power_domain power_domain;
|
2016-09-20 08:24:40 +07:00
|
|
|
/* for communication with audio component; protected by av_mutex */
|
|
|
|
const struct drm_connector *audio_connector;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
};
|
|
|
|
|
2012-10-19 18:51:49 +07:00
|
|
|
struct intel_panel {
|
2012-10-19 18:51:50 +07:00
|
|
|
struct drm_display_mode *fixed_mode;
|
2017-08-10 02:48:53 +07:00
|
|
|
struct drm_display_mode *alt_fixed_mode;
|
2013-12-10 15:07:36 +07:00
|
|
|
struct drm_display_mode *downclock_mode;
|
2013-11-08 21:48:54 +07:00
|
|
|
|
|
|
|
/* backlight */
|
|
|
|
struct {
|
2013-11-08 21:48:55 +07:00
|
|
|
bool present;
|
2013-11-08 21:48:54 +07:00
|
|
|
u32 level;
|
2014-06-24 22:27:40 +07:00
|
|
|
u32 min;
|
2013-11-08 21:48:56 +07:00
|
|
|
u32 max;
|
2013-11-08 21:48:54 +07:00
|
|
|
bool enabled;
|
2013-11-08 21:49:02 +07:00
|
|
|
bool combination_mode; /* gen 2/4 only */
|
|
|
|
bool active_low_pwm;
|
2016-09-19 17:35:25 +07:00
|
|
|
bool alternate_pwm_increment; /* lpt+ */
|
2015-06-26 16:02:10 +07:00
|
|
|
|
|
|
|
/* PWM chip */
|
2015-10-01 00:04:57 +07:00
|
|
|
bool util_pin_active_low; /* bxt+ */
|
|
|
|
u8 controller; /* bxt+ only */
|
2015-06-26 16:02:10 +07:00
|
|
|
struct pwm_device *pwm;
|
|
|
|
|
2013-11-08 21:48:54 +07:00
|
|
|
struct backlight_device *device;
|
2014-08-13 16:10:12 +07:00
|
|
|
|
2015-09-14 18:03:48 +07:00
|
|
|
/* Connector and platform specific backlight functions */
|
|
|
|
int (*setup)(struct intel_connector *connector, enum pipe pipe);
|
|
|
|
uint32_t (*get)(struct intel_connector *connector);
|
2017-06-12 17:21:15 +07:00
|
|
|
void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
|
|
|
|
void (*disable)(const struct drm_connector_state *conn_state);
|
|
|
|
void (*enable)(const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state);
|
2015-09-14 18:03:48 +07:00
|
|
|
uint32_t (*hz_to_pwm)(struct intel_connector *connector,
|
|
|
|
uint32_t hz);
|
|
|
|
void (*power)(struct intel_connector *, bool enable);
|
|
|
|
} backlight;
|
2012-10-19 18:51:49 +07:00
|
|
|
};
|
|
|
|
|
2010-03-30 13:39:28 +07:00
|
|
|
struct intel_connector {
|
|
|
|
struct drm_connector base;
|
drm/i915: stage modeset output changes
This is the core of the new modeset logic.
The current code which is based upon the crtc helper code first
updates all the link of the new display pipeline and then calls the
lower-level set_mode function to execute the required callbacks to get
there. The issue with this approach is that for disabling we need to
know the _current_ display pipe state, not the new one.
Hence we need to stage the new state of the display pipe and only
update it once we have disabled the current configuration and before we
start to update the hw registers with the new configuration.
This patch here just prepares the ground by switching the new output
state computation to these staging pointers. To make it clearer,
rename the old update_output_state function to stage_output_state.
A few peculiarities:
- We're also calling the set_mode function at various places to update
properties. Hence after a successfule modeset we need to stage the
current configuration (for otherwise we might fall back again). This
happens automatically because as part of the (successful) modeset we
need to copy the staged state to the real one. But for the hw
readout code we need to make sure that this happens, too.
- Teach the new staged output state computation code the required
smarts to handle the disabling of outputs. The current code handles
this in a special case, but to better handle global modeset changes
covering more than one crtc, we want to do this all in the same
low-level modeset code.
- The actual modeset code is still a bit ugly and wants to know the new
crtc->enabled state a bit early. Follow-on patches will clean that
up, for now we have to apply the staged output configuration early,
outside of the set_mode functions.
- Improve/add comments in stage_output_state.
Essentially all that is left to do now is move the disabling code into
set_mode and then move the staged state update code also into
set_mode, at the right place between disabling things and calling the
mode_set callbacks for the new configuration.
v2: Disabling a crtc works by passing in a NULL mode or fb, userspace
doesn't hand in the list of connectors. We therefore need to detect
this case manually and tear down all the output links.
v3: Properly update the output staging pointers after having read out
the hw state.
v4: Simplify the code, add more DRM_DEBUG_KMS output and check a few
assumptions with WARN_ON. Essentially all things that I've noticed
while debugging issues in other places of the code.
v4: Correctly disable the old set of connectors when enabling an
already enabled crtc on a new set of crtc. Reported by Paulo Zanoni.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-07-06 03:34:27 +07:00
|
|
|
/*
|
|
|
|
* The fixed encoder this connector is connected to.
|
|
|
|
*/
|
2010-09-09 22:20:55 +07:00
|
|
|
struct intel_encoder *encoder;
|
drm/i915: stage modeset output changes
This is the core of the new modeset logic.
The current code which is based upon the crtc helper code first
updates all the link of the new display pipeline and then calls the
lower-level set_mode function to execute the required callbacks to get
there. The issue with this approach is that for disabling we need to
know the _current_ display pipe state, not the new one.
Hence we need to stage the new state of the display pipe and only
update it once we have disabled the current configuration and before we
start to update the hw registers with the new configuration.
This patch here just prepares the ground by switching the new output
state computation to these staging pointers. To make it clearer,
rename the old update_output_state function to stage_output_state.
A few peculiarities:
- We're also calling the set_mode function at various places to update
properties. Hence after a successfule modeset we need to stage the
current configuration (for otherwise we might fall back again). This
happens automatically because as part of the (successful) modeset we
need to copy the staged state to the real one. But for the hw
readout code we need to make sure that this happens, too.
- Teach the new staged output state computation code the required
smarts to handle the disabling of outputs. The current code handles
this in a special case, but to better handle global modeset changes
covering more than one crtc, we want to do this all in the same
low-level modeset code.
- The actual modeset code is still a bit ugly and wants to know the new
crtc->enabled state a bit early. Follow-on patches will clean that
up, for now we have to apply the staged output configuration early,
outside of the set_mode functions.
- Improve/add comments in stage_output_state.
Essentially all that is left to do now is move the disabling code into
set_mode and then move the staged state update code also into
set_mode, at the right place between disabling things and calling the
mode_set callbacks for the new configuration.
v2: Disabling a crtc works by passing in a NULL mode or fb, userspace
doesn't hand in the list of connectors. We therefore need to detect
this case manually and tear down all the output links.
v3: Properly update the output staging pointers after having read out
the hw state.
v4: Simplify the code, add more DRM_DEBUG_KMS output and check a few
assumptions with WARN_ON. Essentially all things that I've noticed
while debugging issues in other places of the code.
v4: Correctly disable the old set of connectors when enabling an
already enabled crtc on a new set of crtc. Reported by Paulo Zanoni.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-07-06 03:34:27 +07:00
|
|
|
|
drm/i915: make i915 the source of acpi device ids for _DOD
The graphics driver is supposed to define the DIDL, which are used for
_DOD, not the BIOS. Restore that behaviour.
This is basically a revert of
commit 3143751ff51a163b77f7efd389043e038f3e008e
Author: Zhang Rui <rui.zhang@intel.com>
Date: Mon Mar 29 15:12:16 2010 +0800
drm/i915: set DIDL using the ACPI video output device _ADR method return.
which went out of its way to cater to a specific BIOS, setting up DIDL
based on _ADR method. Perhaps that approach worked on that specific
machine, but on the machines I checked the _ADR method invents the
device identifiers out of thin air if DIDL has not been set. The source
for _ADR is also supposed to be the DIDL set by the driver, not the
other way around.
With this, we'll also limit the number of outputs to what the driver
actually has.
A side effect of this change is that the DIDL, and by proxy CADL, will
be initialized in the order of the connector list. That, in turn, has
internal panels in front, ensuring they're included in the DIDL and CADL
lists. Hopefully this ensures the BIOS does not block backlight hotkey
events, thinking the internal panel is off.
v2: do not set ACPI_DEVICE_ID_SCHEME in the device id (Peter Wu)
v3: Rebase
Cc: Peter Wu <peter@lekensteyn.nl>
Cc: Rainer Koenig <Rainer.Koenig@ts.fujitsu.com>
Cc: Jan-Marek Glogowski <glogow@fbihome.de>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Marcos Paulo de Souza <marcos.souza.org@gmail.com>
Cc: Paolo Stivanin <paolostivanin@fastmail.fm>
Tested-by: Rainer Koenig <Rainer.Koenig@ts.fujitsu.com>
Tested-by: Paolo Stivanin <paolostivanin@fastmail.fm>
Tested-by: Marcos Paulo de Souza <marcos.souza.org@gmail.com>
Reviewed-and-tested-by: Peter Wu <peter@lekensteyn.nl>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/9660d29cf310c17bbf4d58c0e09d5b047446e2d5.1479295490.git.jani.nikula@intel.com
2016-11-16 18:29:56 +07:00
|
|
|
/* ACPI device id for ACPI and driver cooperation */
|
|
|
|
u32 acpi_device_id;
|
|
|
|
|
2012-07-02 18:10:34 +07:00
|
|
|
/* Reads out the current hw, returning true if the connector is enabled
|
|
|
|
* and active (i.e. dpms ON state). */
|
|
|
|
bool (*get_hw_state)(struct intel_connector *);
|
2012-10-19 18:51:49 +07:00
|
|
|
|
|
|
|
/* Panel info for eDP and LVDS */
|
|
|
|
struct intel_panel panel;
|
2012-10-19 18:51:52 +07:00
|
|
|
|
|
|
|
/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
|
|
|
|
struct edid *edid;
|
2014-09-03 02:04:00 +07:00
|
|
|
struct edid *detect_edid;
|
2013-04-16 18:36:55 +07:00
|
|
|
|
|
|
|
/* since POLL and HPD connectors may use the same HPD line keep the native
|
|
|
|
state of connector->polled in case hotplug storm detection changes it */
|
|
|
|
u8 polled;
|
2014-05-02 11:02:48 +07:00
|
|
|
|
|
|
|
void *port; /* store this opaque as its illegal to dereference it */
|
|
|
|
|
|
|
|
struct intel_dp *mst_port;
|
2017-04-06 20:44:19 +07:00
|
|
|
|
|
|
|
/* Work struct to schedule a uevent on link train failure */
|
|
|
|
struct work_struct modeset_retry_work;
|
2010-03-30 13:39:28 +07:00
|
|
|
};
|
|
|
|
|
2017-05-01 20:37:57 +07:00
|
|
|
struct intel_digital_connector_state {
|
|
|
|
struct drm_connector_state base;
|
|
|
|
|
|
|
|
enum hdmi_force_audio force_audio;
|
|
|
|
int broadcast_rgb;
|
|
|
|
};
|
|
|
|
|
|
|
|
#define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
|
|
|
|
|
2016-05-04 16:11:57 +07:00
|
|
|
struct dpll {
|
2013-04-19 18:36:51 +07:00
|
|
|
/* given values */
|
|
|
|
int n;
|
|
|
|
int m1, m2;
|
|
|
|
int p1, p2;
|
|
|
|
/* derived values */
|
|
|
|
int dot;
|
|
|
|
int vco;
|
|
|
|
int m;
|
|
|
|
int p;
|
2016-05-04 16:11:57 +07:00
|
|
|
};
|
2013-04-19 18:36:51 +07:00
|
|
|
|
2015-06-04 15:21:28 +07:00
|
|
|
struct intel_atomic_state {
|
|
|
|
struct drm_atomic_state base;
|
|
|
|
|
2017-01-21 01:21:59 +07:00
|
|
|
struct {
|
|
|
|
/*
|
|
|
|
* Logical state of cdclk (used for all scaling, watermark,
|
|
|
|
* etc. calculations and checks). This is computed as if all
|
|
|
|
* enabled crtcs were active.
|
|
|
|
*/
|
|
|
|
struct intel_cdclk_state logical;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Actual state of cdclk, can be different from the logical
|
|
|
|
* state only when all crtc's are DPMS off.
|
|
|
|
*/
|
|
|
|
struct intel_cdclk_state actual;
|
|
|
|
} cdclk;
|
2015-12-03 20:31:06 +07:00
|
|
|
|
2015-12-10 18:33:57 +07:00
|
|
|
bool dpll_set, modeset;
|
|
|
|
|
2016-05-12 21:06:00 +07:00
|
|
|
/*
|
|
|
|
* Does this transaction change the pipes that are active? This mask
|
|
|
|
* tracks which CRTC's have changed their active state at the end of
|
|
|
|
* the transaction (not counting the temporary disable during modesets).
|
|
|
|
* This mask should only be non-zero when intel_state->modeset is true,
|
|
|
|
* but the converse is not necessarily true; simply changing a mode may
|
|
|
|
* not flip the final active status of any CRTC's
|
|
|
|
*/
|
|
|
|
unsigned int active_pipe_changes;
|
|
|
|
|
2015-12-10 18:33:57 +07:00
|
|
|
unsigned int active_crtcs;
|
2017-08-31 01:57:03 +07:00
|
|
|
/* minimum acceptable cdclk for each pipe */
|
|
|
|
int min_cdclk[I915_MAX_PIPES];
|
2017-10-24 16:52:14 +07:00
|
|
|
/* minimum acceptable voltage level for each pipe */
|
|
|
|
u8 min_voltage_level[I915_MAX_PIPES];
|
2015-12-10 18:33:57 +07:00
|
|
|
|
2016-12-29 22:22:09 +07:00
|
|
|
struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 08:20:13 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Current watermarks can't be trusted during hardware readout, so
|
|
|
|
* don't bother calculating intermediate watermarks.
|
|
|
|
*/
|
|
|
|
bool skip_intermediate_wm;
|
2016-05-12 21:06:03 +07:00
|
|
|
|
|
|
|
/* Gen9+ only */
|
2016-05-13 05:11:40 +07:00
|
|
|
struct skl_wm_values wm_results;
|
2016-10-28 19:58:45 +07:00
|
|
|
|
|
|
|
struct i915_sw_fence commit_ready;
|
2017-01-24 04:29:39 +07:00
|
|
|
|
|
|
|
struct llist_node freed;
|
2015-06-04 15:21:28 +07:00
|
|
|
};
|
|
|
|
|
2014-09-06 03:04:46 +07:00
|
|
|
struct intel_plane_state {
|
2014-12-02 06:40:13 +07:00
|
|
|
struct drm_plane_state base;
|
2017-01-16 22:21:27 +07:00
|
|
|
struct i915_vma *vma;
|
2014-12-24 22:59:06 +07:00
|
|
|
|
2016-01-28 21:53:54 +07:00
|
|
|
struct {
|
|
|
|
u32 offset;
|
|
|
|
int x, y;
|
|
|
|
} main;
|
2016-01-28 21:30:28 +07:00
|
|
|
struct {
|
|
|
|
u32 offset;
|
|
|
|
int x, y;
|
|
|
|
} aux;
|
2016-01-28 21:53:54 +07:00
|
|
|
|
2017-03-24 02:27:09 +07:00
|
|
|
/* plane control register */
|
|
|
|
u32 ctl;
|
|
|
|
|
2017-11-14 01:11:28 +07:00
|
|
|
/* plane color control register */
|
|
|
|
u32 color_ctl;
|
|
|
|
|
2015-04-08 05:28:36 +07:00
|
|
|
/*
|
|
|
|
* scaler_id
|
|
|
|
* = -1 : not using a scaler
|
|
|
|
* >= 0 : using a scalers
|
|
|
|
*
|
|
|
|
* plane requiring a scaler:
|
|
|
|
* - During check_plane, its bit is set in
|
|
|
|
* crtc_state->scaler_state.scaler_users by calling helper function
|
2015-06-22 14:50:32 +07:00
|
|
|
* update_scaler_plane.
|
2015-04-08 05:28:36 +07:00
|
|
|
* - scaler_id indicates the scaler it got assigned.
|
|
|
|
*
|
|
|
|
* plane doesn't require a scaler:
|
|
|
|
* - this can happen when scaling is no more required or plane simply
|
|
|
|
* got disabled.
|
|
|
|
* - During check_plane, corresponding bit is reset in
|
|
|
|
* crtc_state->scaler_state.scaler_users by calling helper function
|
2015-06-22 14:50:32 +07:00
|
|
|
* update_scaler_plane.
|
2015-04-08 05:28:36 +07:00
|
|
|
*/
|
|
|
|
int scaler_id;
|
2015-06-15 17:33:54 +07:00
|
|
|
|
|
|
|
struct drm_intel_sprite_colorkey ckey;
|
2014-09-06 03:04:46 +07:00
|
|
|
};
|
|
|
|
|
2015-01-20 19:51:52 +07:00
|
|
|
struct intel_initial_plane_config {
|
2015-02-06 00:22:18 +07:00
|
|
|
struct intel_framebuffer *fb;
|
2015-01-20 19:51:44 +07:00
|
|
|
unsigned int tiling;
|
2014-03-07 23:57:48 +07:00
|
|
|
int size;
|
|
|
|
u32 base;
|
|
|
|
};
|
|
|
|
|
2015-04-08 05:28:36 +07:00
|
|
|
#define SKL_MIN_SRC_W 8
|
|
|
|
#define SKL_MAX_SRC_W 4096
|
|
|
|
#define SKL_MIN_SRC_H 8
|
2015-04-28 03:48:39 +07:00
|
|
|
#define SKL_MAX_SRC_H 4096
|
2015-04-08 05:28:36 +07:00
|
|
|
#define SKL_MIN_DST_W 8
|
|
|
|
#define SKL_MAX_DST_W 4096
|
|
|
|
#define SKL_MIN_DST_H 8
|
2015-04-28 03:48:39 +07:00
|
|
|
#define SKL_MAX_DST_H 4096
|
2015-04-08 05:28:36 +07:00
|
|
|
|
|
|
|
struct intel_scaler {
|
|
|
|
int in_use;
|
|
|
|
uint32_t mode;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct intel_crtc_scaler_state {
|
|
|
|
#define SKL_NUM_SCALERS 2
|
|
|
|
struct intel_scaler scalers[SKL_NUM_SCALERS];
|
|
|
|
|
|
|
|
/*
|
|
|
|
* scaler_users: keeps track of users requesting scalers on this crtc.
|
|
|
|
*
|
|
|
|
* If a bit is set, a user is using a scaler.
|
|
|
|
* Here user can be a plane or crtc as defined below:
|
|
|
|
* bits 0-30 - plane (bit position is index from drm_plane_index)
|
|
|
|
* bit 31 - crtc
|
|
|
|
*
|
|
|
|
* Instead of creating a new index to cover planes and crtc, using
|
|
|
|
* existing drm_plane_index for planes which is well less than 31
|
|
|
|
* planes and bit 31 for crtc. This should be fine to cover all
|
|
|
|
* our platforms.
|
|
|
|
*
|
|
|
|
* intel_atomic_setup_scalers will setup available scalers to users
|
|
|
|
* requesting scalers. It will gracefully fail if request exceeds
|
|
|
|
* avilability.
|
|
|
|
*/
|
|
|
|
#define SKL_CRTC_INDEX 31
|
|
|
|
unsigned scaler_users;
|
|
|
|
|
|
|
|
/* scaler used by crtc for panel fitting purpose */
|
|
|
|
int scaler_id;
|
|
|
|
};
|
|
|
|
|
2015-07-15 19:15:51 +07:00
|
|
|
/* drm_mode->private_flags */
|
|
|
|
#define I915_MODE_FLAG_INHERITED 1
|
2017-09-25 20:56:01 +07:00
|
|
|
/* Flag to get scanline using frame time stamps */
|
|
|
|
#define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
|
2015-07-15 19:15:51 +07:00
|
|
|
|
2015-09-25 05:53:15 +07:00
|
|
|
struct intel_pipe_wm {
|
|
|
|
struct intel_wm_level wm[5];
|
|
|
|
uint32_t linetime;
|
|
|
|
bool fbc_wm_enabled;
|
|
|
|
bool pipe_enabled;
|
|
|
|
bool sprites_enabled;
|
|
|
|
bool sprites_scaled;
|
|
|
|
};
|
|
|
|
|
2016-10-05 01:28:20 +07:00
|
|
|
struct skl_plane_wm {
|
2015-09-25 05:53:15 +07:00
|
|
|
struct skl_wm_level wm[8];
|
|
|
|
struct skl_wm_level trans_wm;
|
2016-10-05 01:28:20 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
struct skl_pipe_wm {
|
|
|
|
struct skl_plane_wm planes[I915_MAX_PLANES];
|
2015-09-25 05:53:15 +07:00
|
|
|
uint32_t linetime;
|
|
|
|
};
|
|
|
|
|
2017-03-03 00:14:54 +07:00
|
|
|
enum vlv_wm_level {
|
|
|
|
VLV_WM_LEVEL_PM2,
|
|
|
|
VLV_WM_LEVEL_PM5,
|
|
|
|
VLV_WM_LEVEL_DDR_DVFS,
|
|
|
|
NUM_VLV_WM_LEVELS,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct vlv_wm_state {
|
2017-04-22 01:14:21 +07:00
|
|
|
struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
|
|
|
|
struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
|
2017-03-03 00:14:54 +07:00
|
|
|
uint8_t num_levels;
|
|
|
|
bool cxsr;
|
|
|
|
};
|
|
|
|
|
2017-03-03 00:14:55 +07:00
|
|
|
struct vlv_fifo_state {
|
|
|
|
u16 plane[I915_MAX_PLANES];
|
|
|
|
};
|
|
|
|
|
2017-04-22 01:14:29 +07:00
|
|
|
enum g4x_wm_level {
|
|
|
|
G4X_WM_LEVEL_NORMAL,
|
|
|
|
G4X_WM_LEVEL_SR,
|
|
|
|
G4X_WM_LEVEL_HPLL,
|
|
|
|
NUM_G4X_WM_LEVELS,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct g4x_wm_state {
|
|
|
|
struct g4x_pipe_wm wm;
|
|
|
|
struct g4x_sr_wm sr;
|
|
|
|
struct g4x_sr_wm hpll;
|
|
|
|
bool cxsr;
|
|
|
|
bool hpll_en;
|
|
|
|
bool fbc_en;
|
|
|
|
};
|
|
|
|
|
2016-05-12 21:05:55 +07:00
|
|
|
struct intel_crtc_wm_state {
|
|
|
|
union {
|
|
|
|
struct {
|
|
|
|
/*
|
|
|
|
* Intermediate watermarks; these can be
|
|
|
|
* programmed immediately since they satisfy
|
|
|
|
* both the current configuration we're
|
|
|
|
* switching away from and the new
|
|
|
|
* configuration we're switching to.
|
|
|
|
*/
|
|
|
|
struct intel_pipe_wm intermediate;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Optimal watermarks, programmed post-vblank
|
|
|
|
* when this state is committed.
|
|
|
|
*/
|
|
|
|
struct intel_pipe_wm optimal;
|
|
|
|
} ilk;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
/* gen9+ only needs 1-step wm programming */
|
|
|
|
struct skl_pipe_wm optimal;
|
2016-09-15 21:46:35 +07:00
|
|
|
struct skl_ddb_entry ddb;
|
2016-05-12 21:05:55 +07:00
|
|
|
} skl;
|
2017-03-03 00:14:54 +07:00
|
|
|
|
|
|
|
struct {
|
2017-03-03 00:14:56 +07:00
|
|
|
/* "raw" watermarks (not inverted) */
|
2017-04-22 01:14:21 +07:00
|
|
|
struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
|
2017-03-03 00:14:59 +07:00
|
|
|
/* intermediate watermarks (inverted) */
|
|
|
|
struct vlv_wm_state intermediate;
|
2017-03-03 00:14:54 +07:00
|
|
|
/* optimal watermarks (inverted) */
|
|
|
|
struct vlv_wm_state optimal;
|
2017-03-03 00:14:55 +07:00
|
|
|
/* display FIFO split */
|
|
|
|
struct vlv_fifo_state fifo_state;
|
2017-03-03 00:14:54 +07:00
|
|
|
} vlv;
|
2017-04-22 01:14:29 +07:00
|
|
|
|
|
|
|
struct {
|
|
|
|
/* "raw" watermarks */
|
|
|
|
struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
|
|
|
|
/* intermediate watermarks */
|
|
|
|
struct g4x_wm_state intermediate;
|
|
|
|
/* optimal watermarks */
|
|
|
|
struct g4x_wm_state optimal;
|
|
|
|
} g4x;
|
2016-05-12 21:05:55 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Platforms with two-step watermark programming will need to
|
|
|
|
* update watermark programming post-vblank to switch from the
|
|
|
|
* safe intermediate watermarks to the optimal final
|
|
|
|
* watermarks.
|
|
|
|
*/
|
|
|
|
bool need_postvbl_update;
|
|
|
|
};
|
|
|
|
|
2015-01-15 19:55:21 +07:00
|
|
|
struct intel_crtc_state {
|
2015-01-15 19:55:22 +07:00
|
|
|
struct drm_crtc_state base;
|
|
|
|
|
2013-06-06 19:55:52 +07:00
|
|
|
/**
|
|
|
|
* quirks - bitfield with hw state readout quirks
|
|
|
|
*
|
|
|
|
* For various reasons the hw state readout code might not be able to
|
|
|
|
* completely faithfully read out the current state. These cases are
|
|
|
|
* tracked with quirk flags so that fastboot and state checker can act
|
|
|
|
* accordingly.
|
|
|
|
*/
|
2014-04-13 17:00:33 +07:00
|
|
|
#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
|
2013-06-06 19:55:52 +07:00
|
|
|
unsigned long quirks;
|
|
|
|
|
2016-03-09 16:35:44 +07:00
|
|
|
unsigned fb_bits; /* framebuffers to flip */
|
2015-11-19 22:07:14 +07:00
|
|
|
bool update_pipe; /* can a fast modeset be performed? */
|
|
|
|
bool disable_cxsr;
|
2016-03-10 00:07:25 +07:00
|
|
|
bool update_wm_pre, update_wm_post; /* watermarks are updated */
|
2016-02-24 17:24:26 +07:00
|
|
|
bool fb_changed; /* fb on any of the planes is changed */
|
2017-03-03 00:14:58 +07:00
|
|
|
bool fifo_changed; /* FIFO split is changed */
|
2015-08-27 20:44:05 +07:00
|
|
|
|
2013-09-04 22:25:28 +07:00
|
|
|
/* Pipe source size (ie. panel fitter input size)
|
|
|
|
* All planes will be positioned inside this space,
|
|
|
|
* and get clipped at the edges. */
|
|
|
|
int pipe_src_w, pipe_src_h;
|
|
|
|
|
2017-01-27 02:50:31 +07:00
|
|
|
/*
|
|
|
|
* Pipe pixel rate, adjusted for
|
|
|
|
* panel fitter/pipe scaler downscaling.
|
|
|
|
*/
|
|
|
|
unsigned int pixel_rate;
|
|
|
|
|
2013-03-27 06:44:55 +07:00
|
|
|
/* Whether to set up the PCH/FDI. Note that we never allow sharing
|
|
|
|
* between pch encoders and cpu encoders. */
|
|
|
|
bool has_pch_encoder;
|
2013-03-27 06:44:56 +07:00
|
|
|
|
2014-11-06 05:26:08 +07:00
|
|
|
/* Are we sending infoframes on the attached port */
|
|
|
|
bool has_infoframe;
|
|
|
|
|
2013-04-18 01:15:07 +07:00
|
|
|
/* CPU Transcoder for the pipe. Currently this can only differ from the
|
2016-03-18 22:05:42 +07:00
|
|
|
* pipe on Haswell and later (where we have a special eDP transcoder)
|
|
|
|
* and Broxton (where we have special DSI transcoders). */
|
2013-04-18 01:15:07 +07:00
|
|
|
enum transcoder cpu_transcoder;
|
|
|
|
|
2013-03-27 06:44:56 +07:00
|
|
|
/*
|
|
|
|
* Use reduced/limited/broadcast rbg range, compressing from the full
|
|
|
|
* range fed into the crtcs.
|
|
|
|
*/
|
|
|
|
bool limited_color_range;
|
|
|
|
|
2016-06-23 01:57:01 +07:00
|
|
|
/* Bitmask of encoder types (enum intel_output_type)
|
|
|
|
* driven by the pipe.
|
|
|
|
*/
|
|
|
|
unsigned int output_types;
|
|
|
|
|
2014-04-25 04:54:47 +07:00
|
|
|
/* Whether we should send NULL infoframes. Required for audio. */
|
|
|
|
bool has_hdmi_sink;
|
|
|
|
|
2014-04-25 04:54:52 +07:00
|
|
|
/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
|
|
|
|
* has_dp_encoder is set. */
|
|
|
|
bool has_audio;
|
|
|
|
|
2013-04-25 22:54:44 +07:00
|
|
|
/*
|
|
|
|
* Enable dithering, used when the selected pipe bpp doesn't match the
|
|
|
|
* plane bpp.
|
|
|
|
*/
|
2013-03-27 06:44:57 +07:00
|
|
|
bool dither;
|
2013-03-28 16:42:02 +07:00
|
|
|
|
2017-01-24 23:21:49 +07:00
|
|
|
/*
|
|
|
|
* Dither gets enabled for 18bpp which causes CRC mismatch errors for
|
|
|
|
* compliance video pattern tests.
|
|
|
|
* Disable dither only if it is a compliance test request for
|
|
|
|
* 18bpp.
|
|
|
|
*/
|
|
|
|
bool dither_force_disable;
|
|
|
|
|
2013-03-28 16:42:02 +07:00
|
|
|
/* Controls for the clock computation, to override various stages. */
|
|
|
|
bool clock_set;
|
|
|
|
|
2013-04-30 19:01:45 +07:00
|
|
|
/* SDVO TV has a bunch of special case. To make multifunction encoders
|
|
|
|
* work correctly, we need to track this at runtime.*/
|
|
|
|
bool sdvo_tv_clock;
|
|
|
|
|
drm/i915: implement fdi auto-dithering
So on a bunch of setups we only have 2 fdi lanes available, e.g. hsw
VGA or 3 pipes on ivb. And seemingly a lot of modes don't quite fit
into this, among them the default 1080p mode.
The solution is to dither down the pipe a bit so that everything fits,
which this patch implements.
But ports compute their state under the assumption that the bpp they
pick will be the one selected, e.g. the display port bw computations
won't work otherwise. Now we could adjust our code to again up-dither
to the computed DP link parameters, but that's pointless.
So instead when the pipe needs to adjust parameters we need to retry
the pipe_config computation at the encoder stage. Furthermore we need
to inform encoders that they should not increase bandwidth
requirements if possible. This is required for the hdmi code, which
prefers the pipe to up-dither to either of the two possible hdmi bpc
values.
LVDS has a similar requirement, although that's probably only
theoretical in nature: It's unlikely that we'll ever see an 8bpc
high-res lvds panel (which is required to hit the 2 fdi lane limit).
eDP is the only thing which could increase the pipe_bpp setting again,
even when in the retry-loop. This could hit the WARN. Two reasons for
not bothering:
- On many eDP panels we'll get a black screen if the bpp settings
don't match vbt. So failing the modeset is the right thing to do.
But since that also means it's the only way to light up the panel,
it should work. So we shouldn't be able to hit this WARN.
- There are still opens around the eDP panel handling, and maybe we
need additional tricks. Before that happens it's imo no use trying
to be too clever.
Worst case we just need to kill that WARN or maybe fail the compute
config stage if the eDP connector can't get the bpp setting it wants.
And since this can only happen with an fdi link in between and so for
pch eDP panels it's rather unlikely to blow up, if ever.
v2: Rebased on top of a bikeshed from Paulo.
v3: Improve commit message around eDP handling with the stuff
things with Imre.
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-02-21 06:00:16 +07:00
|
|
|
/*
|
|
|
|
* crtc bandwidth limit, don't increase pipe bpp or clock if not really
|
|
|
|
* required. This is set in the 2nd loop of calling encoder's
|
|
|
|
* ->compute_config if the first pick doesn't work out.
|
|
|
|
*/
|
|
|
|
bool bw_constrained;
|
|
|
|
|
2013-03-28 16:42:02 +07:00
|
|
|
/* Settings for the intel dpll used on pretty much everything but
|
|
|
|
* haswell. */
|
2013-04-19 18:36:51 +07:00
|
|
|
struct dpll dpll;
|
2013-03-28 16:42:02 +07:00
|
|
|
|
2016-03-08 22:46:18 +07:00
|
|
|
/* Selected dpll when shared or NULL. */
|
|
|
|
struct intel_shared_dpll *shared_dpll;
|
2013-06-08 04:10:32 +07:00
|
|
|
|
2013-06-05 18:34:20 +07:00
|
|
|
/* Actual register state of the dpll, for shared dpll cross-checking. */
|
|
|
|
struct intel_dpll_hw_state dpll_hw_state;
|
|
|
|
|
2016-04-13 02:14:35 +07:00
|
|
|
/* DSI PLL registers */
|
|
|
|
struct {
|
|
|
|
u32 ctrl, div;
|
|
|
|
} dsi_pll;
|
|
|
|
|
2013-03-27 06:44:57 +07:00
|
|
|
int pipe_bpp;
|
drm/i915: clear up the fdi/dp set_m_n confusion
There's a rather decent confusion going on around transcoder m_n
values. So let's clarify:
- All dp encoders need this, either on the pch transcoder if it's a
pch port, or on the cpu transcoder/pipe if it's a cpu port.
- fdi links need to have the right m_n values for the fdi link set in
the cpu transcoder.
To handle the pch vs transcoder stuff a bit better, extract transcoder
set_m_n helpers. To make them simpler, set intel_crtc->cpu_transcoder
als in ironlake_crtc_mode_set, so that gen5+ (where the cpu m_n
registers are all at the same offset) can use it.
Haswell modeset is decently confused about dp vs. edp vs. fdi. dp vs.
edp works exactly the same as dp (since there's no pch dp any more),
so use that as a check. And only set up the fdi m_n values if we
really have a pch encoder present (which means we have a VGA encoder).
On ilk+ we've called ironlake_set_m_n both for cpu_edp and for pch
encoders. Now that dp_set_m_n handles all dp links (thanks to the
pch encoder check), we can ditch the cpu_edp stuff from the
fdi_set_m_n function.
Since the dp_m_n values are not readily available, we need to
carefully coax the edp values out of the encoder. Hence we can't (yet)
kill this superflous complexity.
v2: Rebase on top of the ivb fdi B/C check patch - we need to properly
clear intel_crtc->fdi_lane, otherwise those checks will misfire.
v3: Rebased on top of a s/IS_HASWELL/HAS_DDI/ patch from Paulo Zanoni.
v4: Drop the addition of has_dp_encoder, it's in the wrong patch (Jesse).
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-03 04:38:10 +07:00
|
|
|
struct intel_link_m_n dp_m_n;
|
2013-06-01 22:16:21 +07:00
|
|
|
|
2014-04-05 13:43:28 +07:00
|
|
|
/* m2_n2 for eDP downclock */
|
|
|
|
struct intel_link_m_n dp_m2_n2;
|
2014-08-05 21:51:22 +07:00
|
|
|
bool has_drrs;
|
2014-04-05 13:43:28 +07:00
|
|
|
|
2017-10-12 20:02:01 +07:00
|
|
|
bool has_psr;
|
|
|
|
bool has_psr2;
|
|
|
|
|
2013-06-01 22:16:21 +07:00
|
|
|
/*
|
|
|
|
* Frequence the dpll for the port should run at. Differs from the
|
2013-09-07 03:28:59 +07:00
|
|
|
* adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
|
|
|
|
* already multiplied by pixel_multiplier.
|
2013-03-28 16:41:58 +07:00
|
|
|
*/
|
2013-06-01 22:16:21 +07:00
|
|
|
int port_clock;
|
|
|
|
|
2013-03-27 06:44:53 +07:00
|
|
|
/* Used by SDVO (and if we ever fix it, HDMI). */
|
|
|
|
unsigned pixel_multiplier;
|
2013-04-26 02:55:01 +07:00
|
|
|
|
2015-07-06 20:39:15 +07:00
|
|
|
uint8_t lane_count;
|
|
|
|
|
2016-06-13 20:44:35 +07:00
|
|
|
/*
|
|
|
|
* Used by platforms having DP/HDMI PHY with programmable lane
|
|
|
|
* latency optimization.
|
|
|
|
*/
|
|
|
|
uint8_t lane_lat_optim_mask;
|
|
|
|
|
2017-10-24 16:52:14 +07:00
|
|
|
/* minimum acceptable voltage level */
|
|
|
|
u8 min_voltage_level;
|
|
|
|
|
2013-04-26 02:55:01 +07:00
|
|
|
/* Panel fitter controls for gen2-gen4 + VLV */
|
2013-04-26 02:55:02 +07:00
|
|
|
struct {
|
|
|
|
u32 control;
|
|
|
|
u32 pgm_ratios;
|
2013-04-26 03:52:16 +07:00
|
|
|
u32 lvds_border_bits;
|
2013-04-26 02:55:02 +07:00
|
|
|
} gmch_pfit;
|
|
|
|
|
|
|
|
/* Panel fitter placement and size for Ironlake+ */
|
|
|
|
struct {
|
|
|
|
u32 pos;
|
|
|
|
u32 size;
|
2013-08-27 23:04:17 +07:00
|
|
|
bool enabled;
|
2014-05-29 19:10:22 +07:00
|
|
|
bool force_thru;
|
2013-04-26 02:55:02 +07:00
|
|
|
} pch_pfit;
|
2013-02-14 00:04:45 +07:00
|
|
|
|
2013-02-14 22:54:22 +07:00
|
|
|
/* FDI configuration, only valid if has_pch_encoder is set. */
|
2013-02-14 00:04:45 +07:00
|
|
|
int fdi_lanes;
|
2013-02-14 22:54:22 +07:00
|
|
|
struct intel_link_m_n fdi_m_n;
|
2013-06-01 02:33:22 +07:00
|
|
|
|
|
|
|
bool ips_enabled;
|
2017-08-17 21:55:09 +07:00
|
|
|
bool ips_force_disable;
|
2013-09-04 22:30:02 +07:00
|
|
|
|
2016-01-19 20:35:50 +07:00
|
|
|
bool enable_fbc;
|
|
|
|
|
2013-09-04 22:30:02 +07:00
|
|
|
bool double_wide;
|
2014-05-02 11:02:48 +07:00
|
|
|
|
|
|
|
int pbn;
|
2015-04-08 05:28:36 +07:00
|
|
|
|
|
|
|
struct intel_crtc_scaler_state scaler_state;
|
2015-06-01 17:50:09 +07:00
|
|
|
|
|
|
|
/* w/a for waiting 2 vblanks during crtc enable */
|
|
|
|
enum pipe hsw_workaround_pipe;
|
2015-09-25 05:53:12 +07:00
|
|
|
|
|
|
|
/* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
|
|
|
|
bool disable_lp_wm;
|
2015-09-25 05:53:15 +07:00
|
|
|
|
2016-05-12 21:05:55 +07:00
|
|
|
struct intel_crtc_wm_state wm;
|
2016-03-16 17:57:15 +07:00
|
|
|
|
|
|
|
/* Gamma mode programmed on the pipe */
|
|
|
|
uint32_t gamma_mode;
|
2017-03-03 00:14:51 +07:00
|
|
|
|
|
|
|
/* bitmask of visible planes (enum plane_id) */
|
|
|
|
u8 active_planes;
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 18:24:03 +07:00
|
|
|
|
|
|
|
/* HDMI scrambling status */
|
|
|
|
bool hdmi_scrambling;
|
|
|
|
|
|
|
|
/* HDMI High TMDS char rate ratio */
|
|
|
|
bool hdmi_high_tmds_clock_ratio;
|
2017-07-21 22:25:04 +07:00
|
|
|
|
|
|
|
/* output format is YCBCR 4:2:0 */
|
|
|
|
bool ycbcr420;
|
2013-03-27 06:44:50 +07:00
|
|
|
};
|
|
|
|
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
struct intel_crtc {
|
|
|
|
struct drm_crtc base;
|
2009-09-11 05:28:06 +07:00
|
|
|
enum pipe pipe;
|
2012-07-02 16:43:47 +07:00
|
|
|
/*
|
|
|
|
* Whether the crtc and the connected output pipeline is active. Implies
|
|
|
|
* that crtc->enabled is set, i.e. the current mode configuration has
|
|
|
|
* some outputs connected to this crtc.
|
|
|
|
*/
|
|
|
|
bool active;
|
2016-11-22 23:01:57 +07:00
|
|
|
u8 plane_ids_mask;
|
2017-02-09 16:31:21 +07:00
|
|
|
unsigned long long enabled_power_domains;
|
2009-09-16 03:57:34 +07:00
|
|
|
struct intel_overlay *overlay;
|
2010-07-09 14:45:04 +07:00
|
|
|
|
2015-01-15 19:55:25 +07:00
|
|
|
struct intel_crtc_state *config;
|
2013-03-27 06:44:50 +07:00
|
|
|
|
2016-09-09 20:11:47 +07:00
|
|
|
/* global reset count when the last flip was submitted */
|
|
|
|
unsigned int reset_count;
|
2016-05-24 22:13:53 +07:00
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-13 03:57:57 +07:00
|
|
|
/* Access to these should be protected by dev_priv->irq_lock. */
|
|
|
|
bool cpu_fifo_underrun_disabled;
|
|
|
|
bool pch_fifo_underrun_disabled;
|
2013-10-09 23:17:55 +07:00
|
|
|
|
|
|
|
/* per-pipe watermark state */
|
|
|
|
struct {
|
|
|
|
/* watermarks currently being used */
|
2015-09-25 05:53:15 +07:00
|
|
|
union {
|
|
|
|
struct intel_pipe_wm ilk;
|
2017-03-03 00:14:53 +07:00
|
|
|
struct vlv_wm_state vlv;
|
2017-04-22 01:14:29 +07:00
|
|
|
struct g4x_wm_state g4x;
|
2015-09-25 05:53:15 +07:00
|
|
|
} active;
|
2013-10-09 23:17:55 +07:00
|
|
|
} wm;
|
2014-04-29 17:35:46 +07:00
|
|
|
|
2014-05-16 00:23:23 +07:00
|
|
|
int scanline_offset;
|
2014-12-24 22:59:06 +07:00
|
|
|
|
2015-09-16 04:19:32 +07:00
|
|
|
struct {
|
|
|
|
unsigned start_vbl_count;
|
|
|
|
ktime_t start_vbl_time;
|
|
|
|
int min_vbl, max_vbl;
|
|
|
|
int scanline_start;
|
|
|
|
} debug;
|
2015-09-01 17:15:33 +07:00
|
|
|
|
2015-04-08 05:28:36 +07:00
|
|
|
/* scalers available on this crtc */
|
|
|
|
int num_scalers;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
};
|
|
|
|
|
2011-12-14 04:19:38 +07:00
|
|
|
struct intel_plane {
|
|
|
|
struct drm_plane base;
|
2017-11-18 02:19:10 +07:00
|
|
|
enum i9xx_plane_id i9xx_plane;
|
2016-11-22 23:01:56 +07:00
|
|
|
enum plane_id id;
|
2011-12-14 04:19:38 +07:00
|
|
|
enum pipe pipe;
|
2012-10-23 00:19:27 +07:00
|
|
|
bool can_scale;
|
2011-12-14 04:19:38 +07:00
|
|
|
int max_downscale;
|
2015-06-25 01:59:34 +07:00
|
|
|
uint32_t frontbuffer_bit;
|
2013-05-24 21:59:18 +07:00
|
|
|
|
2017-03-28 01:55:35 +07:00
|
|
|
struct {
|
|
|
|
u32 base, cntl, size;
|
|
|
|
} cursor;
|
|
|
|
|
2015-01-22 07:35:41 +07:00
|
|
|
/*
|
|
|
|
* NOTE: Do not place new plane state fields here (e.g., when adding
|
|
|
|
* new plane properties). New runtime state should now be placed in
|
2016-01-07 17:54:06 +07:00
|
|
|
* the intel_plane_state structure and accessed via plane_state.
|
2015-01-22 07:35:41 +07:00
|
|
|
*/
|
|
|
|
|
2017-03-28 01:55:33 +07:00
|
|
|
void (*update_plane)(struct intel_plane *plane,
|
2016-01-07 17:54:06 +07:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct intel_plane_state *plane_state);
|
2017-03-28 01:55:33 +07:00
|
|
|
void (*disable_plane)(struct intel_plane *plane,
|
|
|
|
struct intel_crtc *crtc);
|
2017-11-18 02:19:08 +07:00
|
|
|
bool (*get_hw_state)(struct intel_plane *plane);
|
2017-03-28 01:55:33 +07:00
|
|
|
int (*check_plane)(struct intel_plane *plane,
|
2015-06-15 17:33:46 +07:00
|
|
|
struct intel_crtc_state *crtc_state,
|
2014-12-02 06:40:16 +07:00
|
|
|
struct intel_plane_state *state);
|
2011-12-14 04:19:38 +07:00
|
|
|
};
|
|
|
|
|
2012-04-17 08:20:35 +07:00
|
|
|
struct intel_watermark_params {
|
2016-10-13 17:09:25 +07:00
|
|
|
u16 fifo_size;
|
|
|
|
u16 max_wm;
|
|
|
|
u8 default_wm;
|
|
|
|
u8 guard_size;
|
|
|
|
u8 cacheline_size;
|
2012-04-17 08:20:35 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
struct cxsr_latency {
|
2016-10-14 20:55:02 +07:00
|
|
|
bool is_desktop : 1;
|
|
|
|
bool is_ddr3 : 1;
|
2016-10-13 17:09:23 +07:00
|
|
|
u16 fsb_freq;
|
|
|
|
u16 mem_freq;
|
|
|
|
u16 display_sr;
|
|
|
|
u16 display_hpll_disable;
|
|
|
|
u16 cursor_sr;
|
|
|
|
u16 cursor_hpll_disable;
|
2012-04-17 08:20:35 +07:00
|
|
|
};
|
|
|
|
|
2015-06-04 15:21:28 +07:00
|
|
|
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
|
2015-03-20 21:18:01 +07:00
|
|
|
#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
|
2010-03-30 13:39:28 +07:00
|
|
|
#define to_intel_connector(x) container_of(x, struct intel_connector, base)
|
2010-09-09 21:14:28 +07:00
|
|
|
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
|
2011-12-14 04:19:38 +07:00
|
|
|
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
|
2014-12-24 01:41:52 +07:00
|
|
|
#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
|
2014-07-08 08:21:47 +07:00
|
|
|
#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
|
2012-05-10 01:37:30 +07:00
|
|
|
struct intel_hdmi {
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t hdmi_reg;
|
2012-05-10 01:37:30 +07:00
|
|
|
int ddc_bus;
|
2016-05-03 02:08:23 +07:00
|
|
|
struct {
|
|
|
|
enum drm_dp_dual_mode_type type;
|
|
|
|
int max_tmds_clock;
|
|
|
|
} dp_dual_mode;
|
2012-05-10 01:37:30 +07:00
|
|
|
bool has_hdmi_sink;
|
|
|
|
bool has_audio;
|
2013-01-17 21:31:31 +07:00
|
|
|
bool rgb_quant_range_selectable;
|
2015-09-04 20:26:11 +07:00
|
|
|
struct intel_connector *attached_connector;
|
2012-05-10 01:37:30 +07:00
|
|
|
};
|
|
|
|
|
2014-05-02 11:02:48 +07:00
|
|
|
struct intel_dp_mst_encoder;
|
2012-09-18 21:58:49 +07:00
|
|
|
#define DP_MAX_DOWNSTREAM_PORTS 0x10
|
2012-06-30 02:03:35 +07:00
|
|
|
|
2015-02-13 17:02:59 +07:00
|
|
|
/*
|
|
|
|
* enum link_m_n_set:
|
|
|
|
* When platform provides two set of M_N registers for dp, we can
|
|
|
|
* program them and switch between them incase of DRRS.
|
|
|
|
* But When only one such register is provided, we have to program the
|
|
|
|
* required divider value on that registers itself based on the DRRS state.
|
|
|
|
*
|
|
|
|
* M1_N1 : Program dp_m_n on M1_N1 registers
|
|
|
|
* dp_m2_n2 on M2_N2 registers (If supported)
|
|
|
|
*
|
|
|
|
* M2_N2 : Program dp_m2_n2 on M1_N1 registers
|
|
|
|
* M2_N2 registers are not supported
|
|
|
|
*/
|
|
|
|
|
|
|
|
enum link_m_n_set {
|
|
|
|
/* Sets the m1_n1 and m2_n2 */
|
|
|
|
M1_N1 = 0,
|
|
|
|
M2_N2
|
|
|
|
};
|
|
|
|
|
2016-12-10 07:22:50 +07:00
|
|
|
struct intel_dp_compliance_data {
|
|
|
|
unsigned long edid;
|
2017-01-24 23:21:49 +07:00
|
|
|
uint8_t video_pattern;
|
|
|
|
uint16_t hdisplay, vdisplay;
|
|
|
|
uint8_t bpc;
|
2016-12-10 07:22:50 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
struct intel_dp_compliance {
|
|
|
|
unsigned long test_type;
|
|
|
|
struct intel_dp_compliance_data test_data;
|
|
|
|
bool test_active;
|
2017-01-24 23:16:34 +07:00
|
|
|
int test_link_rate;
|
|
|
|
u8 test_lane_count;
|
2016-12-10 07:22:50 +07:00
|
|
|
};
|
|
|
|
|
2012-06-30 02:03:35 +07:00
|
|
|
struct intel_dp {
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
|
|
|
i915_reg_t output_reg;
|
|
|
|
i915_reg_t aux_ch_ctl_reg;
|
|
|
|
i915_reg_t aux_ch_data_reg[5];
|
2012-06-30 02:03:35 +07:00
|
|
|
uint32_t DP;
|
2015-08-17 22:05:12 +07:00
|
|
|
int link_rate;
|
|
|
|
uint8_t lane_count;
|
2016-03-30 19:35:25 +07:00
|
|
|
uint8_t sink_count;
|
2016-07-28 21:50:39 +07:00
|
|
|
bool link_mst;
|
2012-06-30 02:03:35 +07:00
|
|
|
bool has_audio;
|
2016-03-30 19:35:23 +07:00
|
|
|
bool detect_done;
|
2016-09-02 05:08:15 +07:00
|
|
|
bool channel_eq_status;
|
2017-02-08 07:54:11 +07:00
|
|
|
bool reset_link_params;
|
2012-06-30 02:03:35 +07:00
|
|
|
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
|
2013-07-12 04:44:56 +07:00
|
|
|
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
|
2012-09-18 21:58:49 +07:00
|
|
|
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
|
2016-04-05 21:10:51 +07:00
|
|
|
uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
|
2017-03-28 21:59:04 +07:00
|
|
|
/* source rates */
|
|
|
|
int num_source_rates;
|
|
|
|
const int *source_rates;
|
2017-03-28 21:59:05 +07:00
|
|
|
/* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
|
|
|
|
int num_sink_rates;
|
2015-03-14 00:40:31 +07:00
|
|
|
int sink_rates[DP_MAX_SUPPORTED_RATES];
|
2017-03-28 21:59:05 +07:00
|
|
|
bool use_rate_select;
|
2017-04-06 20:44:10 +07:00
|
|
|
/* intersection of source and sink rates */
|
|
|
|
int num_common_rates;
|
|
|
|
int common_rates[DP_MAX_SUPPORTED_RATES];
|
2017-04-06 20:44:12 +07:00
|
|
|
/* Max lane count for the current link */
|
|
|
|
int max_link_lane_count;
|
|
|
|
/* Max rate for the current link */
|
|
|
|
int max_link_rate;
|
2016-10-25 20:12:39 +07:00
|
|
|
/* sink or branch descriptor */
|
2017-05-18 18:10:23 +07:00
|
|
|
struct drm_dp_desc desc;
|
2014-03-14 21:51:15 +07:00
|
|
|
struct drm_dp_aux aux;
|
2017-02-22 13:34:26 +07:00
|
|
|
enum intel_display_power_domain aux_power_domain;
|
2012-06-30 02:03:35 +07:00
|
|
|
uint8_t train_set[4];
|
|
|
|
int panel_power_up_delay;
|
|
|
|
int panel_power_down_delay;
|
|
|
|
int panel_power_cycle_delay;
|
|
|
|
int backlight_on_delay;
|
|
|
|
int backlight_off_delay;
|
|
|
|
struct delayed_work panel_vdd_work;
|
|
|
|
bool want_panel_vdd;
|
2013-12-19 23:29:40 +07:00
|
|
|
unsigned long last_power_on;
|
|
|
|
unsigned long last_backlight_off;
|
2016-01-23 08:39:04 +07:00
|
|
|
ktime_t panel_power_off_time;
|
2014-08-05 06:04:59 +07:00
|
|
|
|
2014-07-08 03:01:46 +07:00
|
|
|
struct notifier_block edp_notifier;
|
|
|
|
|
2014-09-04 18:54:20 +07:00
|
|
|
/*
|
|
|
|
* Pipe whose power sequencer is currently locked into
|
|
|
|
* this port. Only relevant on VLV/CHV.
|
|
|
|
*/
|
|
|
|
enum pipe pps_pipe;
|
2016-12-15 01:00:23 +07:00
|
|
|
/*
|
|
|
|
* Pipe currently driving the port. Used for preventing
|
|
|
|
* the use of the PPS for any pipe currentrly driving
|
|
|
|
* external DP as that will mess things up on VLV.
|
|
|
|
*/
|
|
|
|
enum pipe active_pipe;
|
2016-06-16 20:37:20 +07:00
|
|
|
/*
|
|
|
|
* Set if the sequencer may be reset due to a power transition,
|
|
|
|
* requiring a reinitialization. Only relevant on BXT.
|
|
|
|
*/
|
|
|
|
bool pps_reset;
|
2014-10-17 01:27:30 +07:00
|
|
|
struct edp_power_seq pps_delays;
|
2014-09-04 18:54:20 +07:00
|
|
|
|
2014-05-02 11:02:48 +07:00
|
|
|
bool can_mst; /* this port supports mst */
|
|
|
|
bool is_mst;
|
2016-08-05 23:05:42 +07:00
|
|
|
int active_mst_links;
|
2014-05-02 11:02:48 +07:00
|
|
|
/* connector directly attached - won't be use for modeset in mst world */
|
2012-10-19 18:51:50 +07:00
|
|
|
struct intel_connector *attached_connector;
|
2014-01-21 20:35:39 +07:00
|
|
|
|
2014-05-02 11:02:48 +07:00
|
|
|
/* mst connector list */
|
|
|
|
struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
|
|
|
|
struct drm_dp_mst_topology_mgr mst_mgr;
|
|
|
|
|
2014-01-21 20:35:39 +07:00
|
|
|
uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
|
2014-01-21 20:37:15 +07:00
|
|
|
/*
|
|
|
|
* This function returns the value we have to program the AUX_CTL
|
|
|
|
* register with to kick off an AUX transaction.
|
|
|
|
*/
|
|
|
|
uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
|
|
|
|
bool has_aux_irq,
|
|
|
|
int send_bytes,
|
|
|
|
uint32_t aux_clock_divider);
|
2015-10-23 17:01:49 +07:00
|
|
|
|
|
|
|
/* This is called before a link training is starterd */
|
|
|
|
void (*prepare_link_retrain)(struct intel_dp *intel_dp);
|
|
|
|
|
2015-04-15 22:38:38 +07:00
|
|
|
/* Displayport compliance testing */
|
2016-12-10 07:22:50 +07:00
|
|
|
struct intel_dp_compliance compliance;
|
2012-06-30 02:03:35 +07:00
|
|
|
};
|
|
|
|
|
2016-10-14 21:26:49 +07:00
|
|
|
struct intel_lspcon {
|
|
|
|
bool active;
|
|
|
|
enum drm_lspcon_mode mode;
|
|
|
|
};
|
|
|
|
|
2012-10-27 04:05:46 +07:00
|
|
|
struct intel_digital_port {
|
|
|
|
struct intel_encoder base;
|
2013-07-13 03:54:41 +07:00
|
|
|
u32 saved_port_bits;
|
2012-10-27 04:05:46 +07:00
|
|
|
struct intel_dp dp;
|
|
|
|
struct intel_hdmi hdmi;
|
2016-10-14 21:26:49 +07:00
|
|
|
struct intel_lspcon lspcon;
|
2015-01-23 12:00:31 +07:00
|
|
|
enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
|
drm/i915: Trick CL2 into life on CHV when using pipe B with port B
Normmally the common lane in a PHY channel gets powered up when some
of the data lanes get powered up. But when we're driving port B with
pipe B we don't want to enabled any of the data lanes, and just want
the DPLL in the common lane to be active.
To make that happens we have to temporarily enable some data lanes
after which we can access the DPLL registers in the common lane. Once
the pipe is up and running we can drop the power override on the data
lanes allowing them to shut down. From this point forward the common
lane will in fact stay powered on until the data lanes in the other
channel get powered down.
Ville's extended explanation from the review thread:
On Wed, Aug 19, 2015 at 07:47:41AM +0530, Deepak wrote:
> One Q, why only for port B? Port C is also in same common lane right?
Port B is in the first PHY channel which also houses CL1. CL1 always
powers up whenever any lanes in either PHY channel are powered up.
CL2 only powers up if lanes in the second channel (ie. the one with
port C) powers up.
So in this scenario (pipe B->port B) we want the DPLL from CL2, but
ideally we only want to power up the lanes for port B. Powering up
port B lanes will only power up CL1, but as we need CL2 instead we
need to, temporarily, power up some lanes in port C as well.
Crossing the streams the other way (pipe A->port C) is not a problem
since CL1 powers up whenever anything else powers up. So powering up
some port C lanes is enough on its own to make the CL1 DPLL
operational, even though CL1 and the lanes live in separate channels.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
[danvet: Amend commit message with extended explanation.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-09 03:45:55 +07:00
|
|
|
bool release_cl2_override;
|
2015-12-09 00:59:38 +07:00
|
|
|
uint8_t max_lanes;
|
2017-02-24 21:19:59 +07:00
|
|
|
enum intel_display_power_domain ddi_io_power_domain;
|
2017-08-18 20:49:54 +07:00
|
|
|
|
|
|
|
void (*write_infoframe)(struct drm_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
2017-10-14 02:40:51 +07:00
|
|
|
unsigned int type,
|
2017-08-18 20:49:54 +07:00
|
|
|
const void *frame, ssize_t len);
|
|
|
|
void (*set_infoframes)(struct drm_encoder *encoder,
|
|
|
|
bool enable,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state);
|
|
|
|
bool (*infoframe_enabled)(struct drm_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *pipe_config);
|
2012-10-27 04:05:46 +07:00
|
|
|
};
|
|
|
|
|
2014-05-02 11:02:48 +07:00
|
|
|
struct intel_dp_mst_encoder {
|
|
|
|
struct intel_encoder base;
|
|
|
|
enum pipe pipe;
|
|
|
|
struct intel_digital_port *primary;
|
2016-03-09 08:14:38 +07:00
|
|
|
struct intel_connector *connector;
|
2014-05-02 11:02:48 +07:00
|
|
|
};
|
|
|
|
|
2015-07-09 03:45:53 +07:00
|
|
|
static inline enum dpio_channel
|
2013-04-19 04:51:36 +07:00
|
|
|
vlv_dport_to_channel(struct intel_digital_port *dport)
|
|
|
|
{
|
2017-11-09 22:24:34 +07:00
|
|
|
switch (dport->base.port) {
|
2013-04-19 04:51:36 +07:00
|
|
|
case PORT_B:
|
2014-04-09 17:28:15 +07:00
|
|
|
case PORT_D:
|
2013-11-06 13:36:35 +07:00
|
|
|
return DPIO_CH0;
|
2013-04-19 04:51:36 +07:00
|
|
|
case PORT_C:
|
2013-11-06 13:36:35 +07:00
|
|
|
return DPIO_CH1;
|
2013-04-19 04:51:36 +07:00
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-07-09 03:45:53 +07:00
|
|
|
static inline enum dpio_phy
|
|
|
|
vlv_dport_to_phy(struct intel_digital_port *dport)
|
|
|
|
{
|
2017-11-09 22:24:34 +07:00
|
|
|
switch (dport->base.port) {
|
2015-07-09 03:45:53 +07:00
|
|
|
case PORT_B:
|
|
|
|
case PORT_C:
|
|
|
|
return DPIO_PHY0;
|
|
|
|
case PORT_D:
|
|
|
|
return DPIO_PHY1;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline enum dpio_channel
|
2014-04-09 17:28:16 +07:00
|
|
|
vlv_pipe_to_channel(enum pipe pipe)
|
|
|
|
{
|
|
|
|
switch (pipe) {
|
|
|
|
case PIPE_A:
|
|
|
|
case PIPE_C:
|
|
|
|
return DPIO_CH0;
|
|
|
|
case PIPE_B:
|
|
|
|
return DPIO_CH1;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-11-01 03:37:05 +07:00
|
|
|
static inline struct intel_crtc *
|
2016-11-01 03:37:09 +07:00
|
|
|
intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
|
2010-09-09 21:44:14 +07:00
|
|
|
{
|
|
|
|
return dev_priv->pipe_to_crtc_mapping[pipe];
|
|
|
|
}
|
|
|
|
|
2016-11-01 03:37:05 +07:00
|
|
|
static inline struct intel_crtc *
|
2017-11-18 02:19:10 +07:00
|
|
|
intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
|
2011-01-19 22:04:42 +07:00
|
|
|
{
|
|
|
|
return dev_priv->plane_to_crtc_mapping[plane];
|
|
|
|
}
|
|
|
|
|
2013-09-24 23:52:53 +07:00
|
|
|
struct intel_load_detect_pipe {
|
2016-02-17 15:18:35 +07:00
|
|
|
struct drm_atomic_state *restore_state;
|
2013-09-24 23:52:53 +07:00
|
|
|
};
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
|
2013-09-24 23:52:53 +07:00
|
|
|
static inline struct intel_encoder *
|
|
|
|
intel_attached_encoder(struct drm_connector *connector)
|
2010-09-09 22:20:55 +07:00
|
|
|
{
|
|
|
|
return to_intel_connector(connector)->encoder;
|
|
|
|
}
|
|
|
|
|
2012-10-27 04:05:46 +07:00
|
|
|
static inline struct intel_digital_port *
|
|
|
|
enc_to_dig_port(struct drm_encoder *encoder)
|
|
|
|
{
|
2017-02-24 21:18:45 +07:00
|
|
|
struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
|
|
|
|
|
|
|
|
switch (intel_encoder->type) {
|
2017-10-28 02:31:24 +07:00
|
|
|
case INTEL_OUTPUT_DDI:
|
2017-02-24 21:18:45 +07:00
|
|
|
WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
|
|
|
|
case INTEL_OUTPUT_DP:
|
|
|
|
case INTEL_OUTPUT_EDP:
|
|
|
|
case INTEL_OUTPUT_HDMI:
|
|
|
|
return container_of(encoder, struct intel_digital_port,
|
|
|
|
base.base);
|
|
|
|
default:
|
|
|
|
return NULL;
|
|
|
|
}
|
2013-05-08 17:14:02 +07:00
|
|
|
}
|
|
|
|
|
2014-05-02 11:02:48 +07:00
|
|
|
static inline struct intel_dp_mst_encoder *
|
|
|
|
enc_to_mst(struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
return container_of(encoder, struct intel_dp_mst_encoder, base.base);
|
|
|
|
}
|
|
|
|
|
2013-05-08 17:14:02 +07:00
|
|
|
static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
return &enc_to_dig_port(encoder)->dp;
|
2012-10-27 04:05:46 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct intel_digital_port *
|
|
|
|
dp_to_dig_port(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
return container_of(intel_dp, struct intel_digital_port, dp);
|
|
|
|
}
|
|
|
|
|
2016-11-22 02:15:05 +07:00
|
|
|
static inline struct intel_lspcon *
|
|
|
|
dp_to_lspcon(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
return &dp_to_dig_port(intel_dp)->lspcon;
|
|
|
|
}
|
|
|
|
|
2012-10-27 04:05:46 +07:00
|
|
|
static inline struct intel_digital_port *
|
|
|
|
hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
|
|
|
|
{
|
|
|
|
return container_of(intel_hdmi, struct intel_digital_port, hdmi);
|
2012-10-16 01:51:29 +07:00
|
|
|
}
|
|
|
|
|
2017-08-23 22:22:23 +07:00
|
|
|
static inline struct intel_plane_state *
|
|
|
|
intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
|
|
|
|
struct intel_plane *plane)
|
|
|
|
{
|
|
|
|
return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
|
|
|
|
&plane->base));
|
|
|
|
}
|
|
|
|
|
2017-08-23 22:22:22 +07:00
|
|
|
static inline struct intel_crtc_state *
|
|
|
|
intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
|
|
|
|
struct intel_crtc *crtc)
|
|
|
|
{
|
|
|
|
return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
|
|
|
|
&crtc->base));
|
|
|
|
}
|
|
|
|
|
2017-08-23 22:22:21 +07:00
|
|
|
static inline struct intel_crtc_state *
|
|
|
|
intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
|
|
|
|
struct intel_crtc *crtc)
|
|
|
|
{
|
|
|
|
return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
|
|
|
|
&crtc->base));
|
|
|
|
}
|
|
|
|
|
2014-09-30 15:56:46 +07:00
|
|
|
/* intel_fifo_underrun.c */
|
2014-09-30 15:56:47 +07:00
|
|
|
bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
|
2013-09-25 01:48:31 +07:00
|
|
|
enum pipe pipe, bool enable);
|
2014-09-30 15:56:47 +07:00
|
|
|
bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
|
2017-07-18 01:14:03 +07:00
|
|
|
enum pipe pch_transcoder,
|
2013-09-25 01:48:31 +07:00
|
|
|
bool enable);
|
2014-09-30 15:56:48 +07:00
|
|
|
void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe);
|
|
|
|
void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
|
2017-07-18 01:14:03 +07:00
|
|
|
enum pipe pch_transcoder);
|
2015-10-31 00:22:21 +07:00
|
|
|
void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
|
2014-09-30 15:56:46 +07:00
|
|
|
|
|
|
|
/* i915_irq.c */
|
2014-07-16 14:49:40 +07:00
|
|
|
void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
|
|
|
|
void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
|
2016-10-12 23:24:30 +07:00
|
|
|
void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
|
|
|
|
void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
|
2016-05-10 20:10:04 +07:00
|
|
|
void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
|
2016-05-06 20:48:28 +07:00
|
|
|
void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
|
|
|
|
void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
|
2017-03-12 20:54:26 +07:00
|
|
|
|
|
|
|
static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
|
|
|
|
u32 mask)
|
|
|
|
{
|
2017-10-11 04:30:06 +07:00
|
|
|
return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
|
2017-03-12 20:54:26 +07:00
|
|
|
}
|
|
|
|
|
2014-09-30 15:56:44 +07:00
|
|
|
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
|
2014-06-20 23:29:20 +07:00
|
|
|
static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* We only use drm_irq_uninstall() at unload and VT switch, so
|
|
|
|
* this is the only thing we need to check.
|
|
|
|
*/
|
2017-10-11 04:30:04 +07:00
|
|
|
return dev_priv->runtime_pm.irqs_enabled;
|
2014-06-20 23:29:20 +07:00
|
|
|
}
|
|
|
|
|
2014-04-29 17:35:45 +07:00
|
|
|
int intel_get_crtc_scanline(struct intel_crtc *crtc);
|
2015-03-07 01:50:48 +07:00
|
|
|
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
|
2017-07-12 22:54:13 +07:00
|
|
|
u8 pipe_mask);
|
2016-02-20 01:47:30 +07:00
|
|
|
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
|
2017-07-12 22:54:13 +07:00
|
|
|
u8 pipe_mask);
|
2016-10-12 23:24:31 +07:00
|
|
|
void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
|
|
|
|
void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
|
|
|
|
void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
|
2013-09-24 23:52:53 +07:00
|
|
|
|
|
|
|
/* intel_crt.c */
|
2016-11-23 21:21:44 +07:00
|
|
|
void intel_crt_init(struct drm_i915_private *dev_priv);
|
2016-06-22 04:03:42 +07:00
|
|
|
void intel_crt_reset(struct drm_encoder *encoder);
|
2013-09-24 23:52:53 +07:00
|
|
|
|
|
|
|
/* intel_ddi.c */
|
2016-08-23 21:18:08 +07:00
|
|
|
void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state);
|
2017-03-02 19:58:54 +07:00
|
|
|
void hsw_fdi_link_train(struct intel_crtc *crtc,
|
|
|
|
const struct intel_crtc_state *crtc_state);
|
2016-11-23 21:21:44 +07:00
|
|
|
void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
|
2013-09-25 01:48:31 +07:00
|
|
|
bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
|
2017-03-02 19:58:56 +07:00
|
|
|
void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
|
2013-09-25 01:48:31 +07:00
|
|
|
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
|
|
|
|
enum transcoder cpu_transcoder);
|
2017-03-02 19:58:56 +07:00
|
|
|
void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
|
|
|
|
void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
|
2017-03-23 01:58:45 +07:00
|
|
|
struct intel_encoder *
|
|
|
|
intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
|
2017-03-02 19:58:56 +07:00
|
|
|
void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
|
2015-10-23 17:01:49 +07:00
|
|
|
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
|
2013-09-25 01:48:31 +07:00
|
|
|
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
|
|
|
|
void intel_ddi_get_config(struct intel_encoder *encoder,
|
2015-01-15 19:55:21 +07:00
|
|
|
struct intel_crtc_state *pipe_config);
|
2013-09-24 23:52:53 +07:00
|
|
|
|
2017-03-02 19:58:56 +07:00
|
|
|
void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
|
|
|
|
bool state);
|
2017-10-24 16:52:14 +07:00
|
|
|
void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_crtc_state *crtc_state);
|
2017-08-30 06:22:24 +07:00
|
|
|
u32 bxt_signal_levels(struct intel_dp *intel_dp);
|
2015-06-25 15:11:03 +07:00
|
|
|
uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
|
2017-02-24 00:49:01 +07:00
|
|
|
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
|
|
|
|
|
2017-03-08 02:42:06 +07:00
|
|
|
unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
|
|
|
|
int plane, unsigned int height);
|
2014-09-19 23:27:27 +07:00
|
|
|
|
2014-10-27 21:26:43 +07:00
|
|
|
/* intel_audio.c */
|
2016-03-16 18:38:53 +07:00
|
|
|
void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
|
2016-11-08 19:55:38 +07:00
|
|
|
void intel_audio_codec_enable(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state);
|
2017-10-31 01:46:53 +07:00
|
|
|
void intel_audio_codec_disable(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state);
|
2015-01-08 22:54:14 +07:00
|
|
|
void i915_audio_component_init(struct drm_i915_private *dev_priv);
|
|
|
|
void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
|
2017-01-25 05:57:49 +07:00
|
|
|
void intel_audio_init(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_audio_deinit(struct drm_i915_private *dev_priv);
|
2014-10-27 21:26:43 +07:00
|
|
|
|
2017-02-08 01:33:05 +07:00
|
|
|
/* intel_cdclk.c */
|
2017-08-31 01:57:03 +07:00
|
|
|
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
|
2017-02-22 04:23:27 +07:00
|
|
|
void skl_init_cdclk(struct drm_i915_private *dev_priv);
|
|
|
|
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
|
2017-06-10 05:26:00 +07:00
|
|
|
void cnl_init_cdclk(struct drm_i915_private *dev_priv);
|
|
|
|
void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
|
2017-02-22 04:23:27 +07:00
|
|
|
void bxt_init_cdclk(struct drm_i915_private *dev_priv);
|
|
|
|
void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
|
2017-02-08 01:33:05 +07:00
|
|
|
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_update_cdclk(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_update_rawclk(struct drm_i915_private *dev_priv);
|
2017-10-24 16:52:08 +07:00
|
|
|
bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
|
2017-02-08 01:33:45 +07:00
|
|
|
const struct intel_cdclk_state *b);
|
2017-10-24 16:52:08 +07:00
|
|
|
bool intel_cdclk_changed(const struct intel_cdclk_state *a,
|
|
|
|
const struct intel_cdclk_state *b);
|
2017-01-27 02:52:01 +07:00
|
|
|
void intel_set_cdclk(struct drm_i915_private *dev_priv,
|
|
|
|
const struct intel_cdclk_state *cdclk_state);
|
2017-10-24 16:52:16 +07:00
|
|
|
void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
|
|
|
|
const char *context);
|
2017-02-08 01:33:05 +07:00
|
|
|
|
2014-09-19 23:27:27 +07:00
|
|
|
/* intel_display.c */
|
2017-06-01 21:36:16 +07:00
|
|
|
void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
|
|
|
|
void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
|
2017-07-18 01:14:03 +07:00
|
|
|
enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
|
2016-04-27 21:43:22 +07:00
|
|
|
void intel_update_rawclk(struct drm_i915_private *dev_priv);
|
2017-02-08 01:33:45 +07:00
|
|
|
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
|
2016-03-05 02:43:02 +07:00
|
|
|
int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
|
|
|
|
const char *name, u32 reg, int ref_freq);
|
2017-02-08 01:33:05 +07:00
|
|
|
int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
|
|
|
|
const char *name, u32 reg);
|
2016-08-23 21:18:08 +07:00
|
|
|
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
|
|
|
|
void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
|
2016-03-16 18:38:53 +07:00
|
|
|
void intel_init_display_hooks(struct drm_i915_private *dev_priv);
|
drm/i915: Rewrite fb rotation GTT handling
Redo the fb rotation handling in order to:
- eliminate the NV12 special casing
- handle fb->offsets[] properly
- make the rotation handling easier for the plane code
To achieve these goals we reduce intel_rotation_info to only contain
(for each plane) the rotated view width,height,stride in tile units,
and the page offset into the object where the plane starts. Each plane
is handled exactly the same way, no special casing for NV12 or other
formats. We then store the computed rotation_info under
intel_framebuffer so that we don't have to recompute it again.
To handle fb->offsets[] we treat them as a linear offsets and convert
them to x/y offsets from the start of the relevant GTT mapping (either
normal or rotated). We store the x/y offsets under intel_framebuffer,
and for some extra convenience we also store the rotated pitch (ie.
tile aligned plane height). So for each plane we have the normal
x/y offsets, rotated x/y offsets, and the rotated pitch. The normal
pitch is available already in fb->pitches[].
While we're gathering up all that extra information, we can also easily
compute the storage requirements for the framebuffer, so that we can
check that the object is big enough to hold it.
When it comes time to deal with the plane source coordinates, we first
rotate the clipped src coordinates to match the relevant GTT view
orientation, then add to them the fb x/y offsets. Next we compute
the aligned surface page offset, and as a result we're left with some
residual x/y offsets. Finally, if required by the hardware, we convert
the remaining x/y offsets into a linear offset.
For gen2/3 we simply skip computing the final page offset, and just
convert the src+fb x/y offsets directly into a linear offset since
that's what the hardware wants.
After this all platforms, incluing SKL+, compute these things in exactly
the same way (excluding alignemnt differences).
v2: Use BIT(DRM_ROTATE_270) instead of ROTATE_270 when rotating
plane src coordinates
Drop some spurious changes that got left behind during
development
v3: Split out more changes to prep patches (Daniel)
s/intel_fb->plane[].foo.bar/intel_fb->foo[].bar/ for brevity
Rename intel_surf_gtt_offset to intel_fb_gtt_offset
Kill the pointless 'plane' parameter from intel_fb_gtt_offset()
v4: Fix alignment vs. alignment-1 when calling
_intel_compute_tile_offset() from intel_fill_fb_info()
Pass the pitch in tiles in
stad of pixels to intel_adjust_tile_offset() from intel_fill_fb_info()
Pass the full width/height of the rotated area to
drm_rect_rotate() for clarity
Use u32 for more offsets
v5: Preserve the upper_32_bits()/lower_32_bits() handling for the
fb ggtt offset (Sivakumar)
v6: Rebase due to drm_plane_state src/dst rects
Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470821001-25272-2-git-send-email-ville.syrjala@linux.intel.com
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-09-15 17:16:41 +07:00
|
|
|
unsigned int intel_fb_xy_to_linear(int x, int y,
|
2016-01-20 23:02:50 +07:00
|
|
|
const struct intel_plane_state *state,
|
|
|
|
int plane);
|
drm/i915: Rewrite fb rotation GTT handling
Redo the fb rotation handling in order to:
- eliminate the NV12 special casing
- handle fb->offsets[] properly
- make the rotation handling easier for the plane code
To achieve these goals we reduce intel_rotation_info to only contain
(for each plane) the rotated view width,height,stride in tile units,
and the page offset into the object where the plane starts. Each plane
is handled exactly the same way, no special casing for NV12 or other
formats. We then store the computed rotation_info under
intel_framebuffer so that we don't have to recompute it again.
To handle fb->offsets[] we treat them as a linear offsets and convert
them to x/y offsets from the start of the relevant GTT mapping (either
normal or rotated). We store the x/y offsets under intel_framebuffer,
and for some extra convenience we also store the rotated pitch (ie.
tile aligned plane height). So for each plane we have the normal
x/y offsets, rotated x/y offsets, and the rotated pitch. The normal
pitch is available already in fb->pitches[].
While we're gathering up all that extra information, we can also easily
compute the storage requirements for the framebuffer, so that we can
check that the object is big enough to hold it.
When it comes time to deal with the plane source coordinates, we first
rotate the clipped src coordinates to match the relevant GTT view
orientation, then add to them the fb x/y offsets. Next we compute
the aligned surface page offset, and as a result we're left with some
residual x/y offsets. Finally, if required by the hardware, we convert
the remaining x/y offsets into a linear offset.
For gen2/3 we simply skip computing the final page offset, and just
convert the src+fb x/y offsets directly into a linear offset since
that's what the hardware wants.
After this all platforms, incluing SKL+, compute these things in exactly
the same way (excluding alignemnt differences).
v2: Use BIT(DRM_ROTATE_270) instead of ROTATE_270 when rotating
plane src coordinates
Drop some spurious changes that got left behind during
development
v3: Split out more changes to prep patches (Daniel)
s/intel_fb->plane[].foo.bar/intel_fb->foo[].bar/ for brevity
Rename intel_surf_gtt_offset to intel_fb_gtt_offset
Kill the pointless 'plane' parameter from intel_fb_gtt_offset()
v4: Fix alignment vs. alignment-1 when calling
_intel_compute_tile_offset() from intel_fill_fb_info()
Pass the pitch in tiles in
stad of pixels to intel_adjust_tile_offset() from intel_fill_fb_info()
Pass the full width/height of the rotated area to
drm_rect_rotate() for clarity
Use u32 for more offsets
v5: Preserve the upper_32_bits()/lower_32_bits() handling for the
fb ggtt offset (Sivakumar)
v6: Rebase due to drm_plane_state src/dst rects
Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470821001-25272-2-git-send-email-ville.syrjala@linux.intel.com
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-09-15 17:16:41 +07:00
|
|
|
void intel_add_fb_offsets(int *x, int *y,
|
2016-01-20 23:02:50 +07:00
|
|
|
const struct intel_plane_state *state, int plane);
|
2016-02-16 03:54:45 +07:00
|
|
|
unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
|
2016-11-29 16:50:08 +07:00
|
|
|
bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
|
2016-04-28 18:57:00 +07:00
|
|
|
void intel_mark_busy(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_mark_idle(struct drm_i915_private *dev_priv);
|
2015-07-13 21:30:29 +07:00
|
|
|
int intel_display_suspend(struct drm_device *dev);
|
2016-08-10 18:07:33 +07:00
|
|
|
void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
|
2013-09-25 01:48:31 +07:00
|
|
|
void intel_encoder_destroy(struct drm_encoder *encoder);
|
2015-04-10 14:59:10 +07:00
|
|
|
int intel_connector_init(struct intel_connector *);
|
|
|
|
struct intel_connector *intel_connector_alloc(void);
|
2017-10-14 01:01:44 +07:00
|
|
|
void intel_connector_free(struct intel_connector *connector);
|
2013-09-25 01:48:31 +07:00
|
|
|
bool intel_connector_get_hw_state(struct intel_connector *connector);
|
|
|
|
void intel_connector_attach_encoder(struct intel_connector *connector,
|
|
|
|
struct intel_encoder *encoder);
|
2017-10-09 23:19:50 +07:00
|
|
|
struct drm_display_mode *
|
|
|
|
intel_encoder_current_mode(struct intel_encoder *encoder);
|
|
|
|
|
2013-10-31 23:55:49 +07:00
|
|
|
enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
|
2009-04-30 04:43:54 +07:00
|
|
|
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv);
|
2013-09-25 01:48:31 +07:00
|
|
|
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe);
|
2016-06-23 01:57:02 +07:00
|
|
|
static inline bool
|
|
|
|
intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
|
|
|
|
enum intel_output_type type)
|
|
|
|
{
|
|
|
|
return crtc_state->output_types & (1 << type);
|
|
|
|
}
|
2016-06-23 01:57:04 +07:00
|
|
|
static inline bool
|
|
|
|
intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
return crtc_state->output_types &
|
2016-06-23 01:57:06 +07:00
|
|
|
((1 << INTEL_OUTPUT_DP) |
|
2016-06-23 01:57:04 +07:00
|
|
|
(1 << INTEL_OUTPUT_DP_MST) |
|
|
|
|
(1 << INTEL_OUTPUT_EDP));
|
|
|
|
}
|
2014-09-15 19:12:21 +07:00
|
|
|
static inline void
|
2016-11-01 03:37:06 +07:00
|
|
|
intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
|
2014-09-15 19:12:21 +07:00
|
|
|
{
|
2016-11-01 03:37:06 +07:00
|
|
|
drm_wait_one_vblank(&dev_priv->drm, pipe);
|
2014-09-15 19:12:21 +07:00
|
|
|
}
|
2015-10-31 00:23:22 +07:00
|
|
|
static inline void
|
2016-11-01 03:37:06 +07:00
|
|
|
intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
|
2015-10-31 00:23:22 +07:00
|
|
|
{
|
2016-11-01 03:37:09 +07:00
|
|
|
const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
|
2015-10-31 00:23:22 +07:00
|
|
|
|
|
|
|
if (crtc->active)
|
2016-11-01 03:37:06 +07:00
|
|
|
intel_wait_for_vblank(dev_priv, pipe);
|
2015-10-31 00:23:22 +07:00
|
|
|
}
|
2016-05-17 20:07:48 +07:00
|
|
|
|
|
|
|
u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
|
|
|
|
|
2013-09-25 01:48:31 +07:00
|
|
|
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
|
2013-11-06 13:36:35 +07:00
|
|
|
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
|
2015-04-10 22:21:31 +07:00
|
|
|
struct intel_digital_port *dport,
|
|
|
|
unsigned int expected_mask);
|
2017-04-07 01:55:20 +07:00
|
|
|
int intel_get_load_detect_pipe(struct drm_connector *connector,
|
2017-05-19 02:38:37 +07:00
|
|
|
const struct drm_display_mode *mode,
|
2017-04-07 01:55:20 +07:00
|
|
|
struct intel_load_detect_pipe *old,
|
|
|
|
struct drm_modeset_acquire_ctx *ctx);
|
2013-09-25 01:48:31 +07:00
|
|
|
void intel_release_load_detect_pipe(struct drm_connector *connector,
|
2015-03-20 21:18:02 +07:00
|
|
|
struct intel_load_detect_pipe *old,
|
|
|
|
struct drm_modeset_acquire_ctx *ctx);
|
2016-08-15 16:49:06 +07:00
|
|
|
struct i915_vma *
|
|
|
|
intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
|
2017-01-16 22:21:27 +07:00
|
|
|
void intel_unpin_fb_vma(struct i915_vma *vma);
|
2014-02-11 00:00:39 +07:00
|
|
|
struct drm_framebuffer *
|
2017-02-15 17:59:18 +07:00
|
|
|
intel_framebuffer_create(struct drm_i915_gem_object *obj,
|
|
|
|
struct drm_mode_fb_cmd2 *mode_cmd);
|
2014-12-02 06:40:14 +07:00
|
|
|
int intel_prepare_plane_fb(struct drm_plane *plane,
|
2016-08-19 01:00:16 +07:00
|
|
|
struct drm_plane_state *new_state);
|
2014-12-02 22:45:25 +07:00
|
|
|
void intel_cleanup_plane_fb(struct drm_plane *plane,
|
2016-08-19 01:00:16 +07:00
|
|
|
struct drm_plane_state *old_state);
|
2015-01-22 07:35:43 +07:00
|
|
|
int intel_plane_atomic_get_property(struct drm_plane *plane,
|
|
|
|
const struct drm_plane_state *state,
|
|
|
|
struct drm_property *property,
|
|
|
|
uint64_t *val);
|
|
|
|
int intel_plane_atomic_set_property(struct drm_plane *plane,
|
|
|
|
struct drm_plane_state *state,
|
|
|
|
struct drm_property *property,
|
|
|
|
uint64_t val);
|
2017-08-23 22:22:23 +07:00
|
|
|
int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
|
|
|
|
struct drm_crtc_state *crtc_state,
|
|
|
|
const struct intel_plane_state *old_plane_state,
|
2015-06-15 17:33:44 +07:00
|
|
|
struct drm_plane_state *plane_state);
|
2014-06-26 02:02:02 +07:00
|
|
|
|
2016-03-08 22:46:15 +07:00
|
|
|
void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe);
|
|
|
|
|
2016-11-01 03:37:07 +07:00
|
|
|
int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
|
2016-01-19 22:25:17 +07:00
|
|
|
const struct dpll *dpll);
|
2016-11-01 03:37:07 +07:00
|
|
|
void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
|
2016-02-18 02:41:12 +07:00
|
|
|
int lpt_get_iclkip(struct drm_i915_private *dev_priv);
|
2014-10-28 18:20:22 +07:00
|
|
|
|
2014-06-26 02:02:02 +07:00
|
|
|
/* modesetting asserts */
|
2014-09-19 23:27:27 +07:00
|
|
|
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe);
|
2013-06-17 02:42:39 +07:00
|
|
|
void assert_pll(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe, bool state);
|
|
|
|
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
|
|
|
|
#define assert_pll_disabled(d, p) assert_pll(d, p, false)
|
2016-03-16 17:57:14 +07:00
|
|
|
void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
|
|
|
|
#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
|
|
|
|
#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
|
2013-06-17 02:42:39 +07:00
|
|
|
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe, bool state);
|
|
|
|
#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
|
|
|
|
#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
|
2013-09-25 01:48:31 +07:00
|
|
|
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
|
2011-12-14 04:19:38 +07:00
|
|
|
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
|
|
|
|
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
|
2016-02-16 03:54:44 +07:00
|
|
|
u32 intel_compute_tile_offset(int *x, int *y,
|
2016-01-20 23:02:50 +07:00
|
|
|
const struct intel_plane_state *state, int plane);
|
2016-05-06 21:40:21 +07:00
|
|
|
void intel_prepare_reset(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_finish_reset(struct drm_i915_private *dev_priv);
|
2014-03-08 06:08:17 +07:00
|
|
|
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
|
|
|
|
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
|
2016-04-21 00:27:56 +07:00
|
|
|
void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
|
2014-11-24 15:07:44 +07:00
|
|
|
void bxt_enable_dc9(struct drm_i915_private *dev_priv);
|
|
|
|
void bxt_disable_dc9(struct drm_i915_private *dev_priv);
|
2016-04-21 00:27:57 +07:00
|
|
|
void gen9_enable_dc5(struct drm_i915_private *dev_priv);
|
2016-05-14 03:41:21 +07:00
|
|
|
unsigned int skl_cdclk_get_vco(unsigned int freq);
|
2015-09-29 12:31:59 +07:00
|
|
|
void skl_enable_dc6(struct drm_i915_private *dev_priv);
|
|
|
|
void skl_disable_dc6(struct drm_i915_private *dev_priv);
|
2013-09-25 01:48:31 +07:00
|
|
|
void intel_dp_get_m_n(struct intel_crtc *crtc,
|
2015-01-15 19:55:21 +07:00
|
|
|
struct intel_crtc_state *pipe_config);
|
2015-02-13 17:02:59 +07:00
|
|
|
void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
|
2013-09-25 01:48:31 +07:00
|
|
|
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
|
2015-03-06 08:29:25 +07:00
|
|
|
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
|
2016-05-04 16:11:57 +07:00
|
|
|
struct dpll *best_clock);
|
|
|
|
int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
|
2015-06-23 03:35:51 +07:00
|
|
|
|
2016-11-01 03:37:02 +07:00
|
|
|
bool intel_crtc_active(struct intel_crtc *crtc);
|
2017-11-23 01:39:01 +07:00
|
|
|
bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
|
2017-11-10 18:35:00 +07:00
|
|
|
void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
|
|
|
|
void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
|
2017-02-22 13:34:27 +07:00
|
|
|
enum intel_display_power_domain intel_port_to_power_domain(enum port port);
|
2014-02-12 06:28:57 +07:00
|
|
|
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
|
2015-01-15 19:55:21 +07:00
|
|
|
struct intel_crtc_state *pipe_config);
|
2015-06-22 14:50:32 +07:00
|
|
|
|
2015-07-13 21:30:15 +07:00
|
|
|
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
|
2015-04-28 03:48:39 +07:00
|
|
|
int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
|
2012-01-03 23:05:39 +07:00
|
|
|
|
2017-01-16 22:21:27 +07:00
|
|
|
static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
|
|
|
|
{
|
|
|
|
return i915_ggtt_offset(state->vma);
|
|
|
|
}
|
2015-09-21 16:45:35 +07:00
|
|
|
|
2017-11-14 01:11:28 +07:00
|
|
|
u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct intel_plane_state *plane_state);
|
2017-03-18 04:17:56 +07:00
|
|
|
u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct intel_plane_state *plane_state);
|
2016-01-28 23:33:11 +07:00
|
|
|
u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
|
|
|
|
unsigned int rotation);
|
2016-01-28 21:53:54 +07:00
|
|
|
int skl_check_plane_surface(struct intel_plane_state *plane_state);
|
2017-03-24 02:27:12 +07:00
|
|
|
int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
|
2015-03-23 18:10:37 +07:00
|
|
|
|
drm/i915/skl: Add support to load SKL CSR firmware.
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC CSR program
that we received from h/w team.
Here we are using request_firmware based design.
Finally this firmware should end up in linux-firmware tree.
For SKL platform its mandatory to ensure that we load this
csr program before enabling DC states like DC5/DC6.
As CSR program gets reset on various conditions, we should ensure
to load it during boot and in future change to be added to load
this system resume sequence too.
v1: Initial relese as RFC patch
v2: Design change as per Daniel, Damien and Shobit's review comments
request firmware method followed.
v3: Some optimization and functional changes.
Pulled register defines into drivers/gpu/drm/i915/i915_reg.h
Used kmemdup to allocate and duplicate firmware content.
Ensured to free allocated buffer.
v4: Modified as per review comments from Satheesh and Daniel
Removed temporary buffer.
Optimized number of writes by replacing I915_WRITE with I915_WRITE64.
v5:
Modified as per review comemnts from Damien.
- Changed name for functions and firmware.
- Introduced HAS_CSR.
- Reverted back previous change and used csr_buf with u8 size.
- Using cpu_to_be64 for endianness change.
Modified as per review comments from Imre.
- Modified registers and macro names to be a bit closer to bspec terminology
and the existing register naming in the driver.
- Early return for non SKL platforms in intel_load_csr_program function.
- Added locking around CSR program load function as it may be called
concurrently during system/runtime resume.
- Releasing the fw before loading the program for consistency
- Handled error path during f/w load.
v6: Modified as per review comments from Imre.
- Corrected out_freecsr sequence.
v7: Modified as per review comments from Imre.
Fail loading fw if fw->size%8!=0.
v8: Rebase to latest.
v9: Rebase on top of -nightly (Damien)
v10: Enabled support for dmc firmware ver 1.0.
According to ver 1.0 in a single binary package all the firmware's that are
required for different stepping's of the product will be stored. The package
contains the css header, followed by the package header and the actual dmc
firmwares. Package header contains the firmware/stepping mapping table and
the corresponding firmware offsets to the individual binaries, within the
package. Each individual program binary contains the header and the payload
sections whose size is specified in the header section. This changes are done
to extract the specific firmaware from the package. (Animesh)
v11: Modified as per review comemnts from Imre.
- Added code comment from bpec for header structure elements.
- Added __packed to avoid structure padding.
- Added helper functions for stepping and substepping info.
- Added code comment for CSR_MAX_FW_SIZE.
- Disabled BXT firmware loading, will be enabled with dmc 1.0 support.
- Changed skl_stepping_info based on bspec, earlier used from config DB.
- Removed duplicate call of cpu_to_be* from intel_csr_load_program function.
- Used cpu_to_be32 instead of cpu_to_be64 as firmware binary in dword aligned.
- Added sanity check for header length.
- Added sanity check for mmio address got from firmware binary.
- kmalloc done separately for dmc header and dmc firmware. (Animesh)
v12: Modified as per review comemnts from Imre.
- Corrected the typo error in skl stepping info structure.
- Added out-of-bound access for skl_stepping_info.
- Sanity check for mmio address modified.
- Sanity check added for stepping and substeppig.
- Modified the intel_dmc_info structure, cache only the required header info. (Animesh)
v13: clarify firmware load error message.
The reason for a firmware loading failure can be obscure if the driver
is built-in. Provide an explanation to the user about the likely reason for
the failure and how to resolve it. (Imre)
v14: Suggested by Jani.
- fix s/I915/CONFIG_DRM_I915/ typo
- add fw_path to the firmware object instead of using a static ptr (Jani)
v15:
1) Changed the firmware name as dmc_gen9.bin, everytime for a new firmware version a symbolic link
with same name will help not to build kernel again.
2) Changes done as per review comments from Imre.
- Error check removed for intel_csr_ucode_init.
- Moved csr-specific data structure to intel_csr.h and optimization done on structure definition.
- fw->data used directly for parsing the header info & memory allocation
only done separately for payload. (Animesh)
v16:
- No need for out_regs label in i915_driver_load(), so removed it.
- Changed the firmware name as skl_dmc_ver1.bin, followed naming convention <platform>_dmc_<api-version>.bin (Animesh)
Issue: VIZ-2569
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-04 19:58:44 +07:00
|
|
|
/* intel_csr.c */
|
2015-10-29 04:59:02 +07:00
|
|
|
void intel_csr_ucode_init(struct drm_i915_private *);
|
2016-03-05 02:57:41 +07:00
|
|
|
void intel_csr_load_program(struct drm_i915_private *);
|
2015-10-29 04:59:02 +07:00
|
|
|
void intel_csr_ucode_fini(struct drm_i915_private *);
|
2016-04-18 18:48:21 +07:00
|
|
|
void intel_csr_ucode_suspend(struct drm_i915_private *);
|
|
|
|
void intel_csr_ucode_resume(struct drm_i915_private *);
|
drm/i915/skl: Add support to load SKL CSR firmware.
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC CSR program
that we received from h/w team.
Here we are using request_firmware based design.
Finally this firmware should end up in linux-firmware tree.
For SKL platform its mandatory to ensure that we load this
csr program before enabling DC states like DC5/DC6.
As CSR program gets reset on various conditions, we should ensure
to load it during boot and in future change to be added to load
this system resume sequence too.
v1: Initial relese as RFC patch
v2: Design change as per Daniel, Damien and Shobit's review comments
request firmware method followed.
v3: Some optimization and functional changes.
Pulled register defines into drivers/gpu/drm/i915/i915_reg.h
Used kmemdup to allocate and duplicate firmware content.
Ensured to free allocated buffer.
v4: Modified as per review comments from Satheesh and Daniel
Removed temporary buffer.
Optimized number of writes by replacing I915_WRITE with I915_WRITE64.
v5:
Modified as per review comemnts from Damien.
- Changed name for functions and firmware.
- Introduced HAS_CSR.
- Reverted back previous change and used csr_buf with u8 size.
- Using cpu_to_be64 for endianness change.
Modified as per review comments from Imre.
- Modified registers and macro names to be a bit closer to bspec terminology
and the existing register naming in the driver.
- Early return for non SKL platforms in intel_load_csr_program function.
- Added locking around CSR program load function as it may be called
concurrently during system/runtime resume.
- Releasing the fw before loading the program for consistency
- Handled error path during f/w load.
v6: Modified as per review comments from Imre.
- Corrected out_freecsr sequence.
v7: Modified as per review comments from Imre.
Fail loading fw if fw->size%8!=0.
v8: Rebase to latest.
v9: Rebase on top of -nightly (Damien)
v10: Enabled support for dmc firmware ver 1.0.
According to ver 1.0 in a single binary package all the firmware's that are
required for different stepping's of the product will be stored. The package
contains the css header, followed by the package header and the actual dmc
firmwares. Package header contains the firmware/stepping mapping table and
the corresponding firmware offsets to the individual binaries, within the
package. Each individual program binary contains the header and the payload
sections whose size is specified in the header section. This changes are done
to extract the specific firmaware from the package. (Animesh)
v11: Modified as per review comemnts from Imre.
- Added code comment from bpec for header structure elements.
- Added __packed to avoid structure padding.
- Added helper functions for stepping and substepping info.
- Added code comment for CSR_MAX_FW_SIZE.
- Disabled BXT firmware loading, will be enabled with dmc 1.0 support.
- Changed skl_stepping_info based on bspec, earlier used from config DB.
- Removed duplicate call of cpu_to_be* from intel_csr_load_program function.
- Used cpu_to_be32 instead of cpu_to_be64 as firmware binary in dword aligned.
- Added sanity check for header length.
- Added sanity check for mmio address got from firmware binary.
- kmalloc done separately for dmc header and dmc firmware. (Animesh)
v12: Modified as per review comemnts from Imre.
- Corrected the typo error in skl stepping info structure.
- Added out-of-bound access for skl_stepping_info.
- Sanity check for mmio address modified.
- Sanity check added for stepping and substeppig.
- Modified the intel_dmc_info structure, cache only the required header info. (Animesh)
v13: clarify firmware load error message.
The reason for a firmware loading failure can be obscure if the driver
is built-in. Provide an explanation to the user about the likely reason for
the failure and how to resolve it. (Imre)
v14: Suggested by Jani.
- fix s/I915/CONFIG_DRM_I915/ typo
- add fw_path to the firmware object instead of using a static ptr (Jani)
v15:
1) Changed the firmware name as dmc_gen9.bin, everytime for a new firmware version a symbolic link
with same name will help not to build kernel again.
2) Changes done as per review comments from Imre.
- Error check removed for intel_csr_ucode_init.
- Moved csr-specific data structure to intel_csr.h and optimization done on structure definition.
- fw->data used directly for parsing the header info & memory allocation
only done separately for payload. (Animesh)
v16:
- No need for out_regs label in i915_driver_load(), so removed it.
- Changed the firmware name as skl_dmc_ver1.bin, followed naming convention <platform>_dmc_<api-version>.bin (Animesh)
Issue: VIZ-2569
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-04 19:58:44 +07:00
|
|
|
|
2013-09-24 23:52:53 +07:00
|
|
|
/* intel_dp.c */
|
2016-11-23 21:21:44 +07:00
|
|
|
bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
|
|
|
|
enum port port);
|
2013-09-25 01:48:31 +07:00
|
|
|
bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
|
|
|
|
struct intel_connector *intel_connector);
|
2015-08-17 22:05:12 +07:00
|
|
|
void intel_dp_set_link_params(struct intel_dp *intel_dp,
|
2016-09-02 05:08:06 +07:00
|
|
|
int link_rate, uint8_t lane_count,
|
|
|
|
bool link_mst);
|
2016-12-09 10:05:12 +07:00
|
|
|
int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
|
|
|
|
int link_rate, uint8_t lane_count);
|
2013-09-25 01:48:31 +07:00
|
|
|
void intel_dp_start_link_train(struct intel_dp *intel_dp);
|
|
|
|
void intel_dp_stop_link_train(struct intel_dp *intel_dp);
|
|
|
|
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
|
2016-04-18 14:04:21 +07:00
|
|
|
void intel_dp_encoder_reset(struct drm_encoder *encoder);
|
|
|
|
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
|
2013-09-25 01:48:31 +07:00
|
|
|
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
|
2017-11-10 18:34:59 +07:00
|
|
|
int intel_dp_sink_crc(struct intel_dp *intel_dp,
|
|
|
|
struct intel_crtc_state *crtc_state, u8 *crc);
|
2013-09-25 01:48:31 +07:00
|
|
|
bool intel_dp_compute_config(struct intel_encoder *encoder,
|
2016-08-09 22:04:05 +07:00
|
|
|
struct intel_crtc_state *pipe_config,
|
|
|
|
struct drm_connector_state *conn_state);
|
2017-08-18 16:30:20 +07:00
|
|
|
bool intel_dp_is_edp(struct intel_dp *intel_dp);
|
2017-08-18 16:30:19 +07:00
|
|
|
bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
|
2015-01-23 12:00:31 +07:00
|
|
|
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
|
|
|
|
bool long_hpd);
|
2017-06-12 17:21:13 +07:00
|
|
|
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state);
|
|
|
|
void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
|
2014-03-17 21:43:36 +07:00
|
|
|
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
|
2014-01-17 20:39:48 +07:00
|
|
|
void intel_edp_panel_on(struct intel_dp *intel_dp);
|
|
|
|
void intel_edp_panel_off(struct intel_dp *intel_dp);
|
2014-05-02 11:02:48 +07:00
|
|
|
void intel_dp_mst_suspend(struct drm_device *dev);
|
|
|
|
void intel_dp_mst_resume(struct drm_device *dev);
|
2015-03-12 22:10:34 +07:00
|
|
|
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
|
2017-04-06 20:44:14 +07:00
|
|
|
int intel_dp_max_lane_count(struct intel_dp *intel_dp);
|
2015-03-12 22:10:36 +07:00
|
|
|
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
|
2014-05-02 11:02:48 +07:00
|
|
|
void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
|
2016-06-16 20:37:20 +07:00
|
|
|
void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
|
2014-11-14 23:52:28 +07:00
|
|
|
uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
|
2014-12-24 01:41:51 +07:00
|
|
|
void intel_plane_destroy(struct drm_plane *plane);
|
2016-08-09 22:04:13 +07:00
|
|
|
void intel_edp_drrs_enable(struct intel_dp *intel_dp,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *crtc_state);
|
2016-08-09 22:04:13 +07:00
|
|
|
void intel_edp_drrs_disable(struct intel_dp *intel_dp,
|
2017-08-18 20:49:58 +07:00
|
|
|
const struct intel_crtc_state *crtc_state);
|
2016-08-04 22:32:38 +07:00
|
|
|
void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
|
|
|
|
unsigned int frontbuffer_bits);
|
|
|
|
void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
|
|
|
|
unsigned int frontbuffer_bits);
|
2014-11-14 23:52:28 +07:00
|
|
|
|
2015-10-23 17:01:48 +07:00
|
|
|
void
|
|
|
|
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
|
|
|
|
uint8_t dp_train_pat);
|
|
|
|
void
|
|
|
|
intel_dp_set_signal_levels(struct intel_dp *intel_dp);
|
|
|
|
void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
|
|
|
|
uint8_t
|
|
|
|
intel_dp_voltage_max(struct intel_dp *intel_dp);
|
|
|
|
uint8_t
|
|
|
|
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
|
|
|
|
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
|
|
|
|
uint8_t *link_bw, uint8_t *rate_select);
|
2015-10-23 17:01:50 +07:00
|
|
|
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
|
2015-10-23 17:01:48 +07:00
|
|
|
bool
|
|
|
|
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
|
|
|
|
|
2016-04-27 19:44:19 +07:00
|
|
|
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
|
|
|
|
{
|
|
|
|
return ~((1 << lane_count) - 1) & 0xf;
|
|
|
|
}
|
|
|
|
|
2016-10-24 23:33:28 +07:00
|
|
|
bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
|
2016-11-16 03:59:06 +07:00
|
|
|
int intel_dp_link_required(int pixel_clock, int bpp);
|
|
|
|
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
|
2017-01-27 16:39:19 +07:00
|
|
|
bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_digital_port *port);
|
2016-10-24 23:33:28 +07:00
|
|
|
|
2016-04-05 21:10:52 +07:00
|
|
|
/* intel_dp_aux_backlight.c */
|
|
|
|
int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
|
|
|
|
|
2014-05-02 11:02:48 +07:00
|
|
|
/* intel_dp_mst.c */
|
|
|
|
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
|
|
|
|
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
|
2013-09-24 23:52:53 +07:00
|
|
|
/* intel_dsi.c */
|
2016-11-23 21:21:44 +07:00
|
|
|
void intel_dsi_init(struct drm_i915_private *dev_priv);
|
2013-09-24 23:52:53 +07:00
|
|
|
|
2016-04-26 20:14:25 +07:00
|
|
|
/* intel_dsi_dcs_backlight.c */
|
|
|
|
int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
|
2013-09-24 23:52:53 +07:00
|
|
|
|
|
|
|
/* intel_dvo.c */
|
2016-11-23 21:21:44 +07:00
|
|
|
void intel_dvo_init(struct drm_i915_private *dev_priv);
|
2016-06-22 04:03:44 +07:00
|
|
|
/* intel_hotplug.c */
|
|
|
|
void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
|
2013-09-24 23:52:53 +07:00
|
|
|
|
|
|
|
|
2013-10-08 22:44:49 +07:00
|
|
|
/* legacy fbdev emulation in intel_fbdev.c */
|
2015-08-10 18:34:08 +07:00
|
|
|
#ifdef CONFIG_DRM_FBDEV_EMULATION
|
2013-10-09 14:18:51 +07:00
|
|
|
extern int intel_fbdev_init(struct drm_device *dev);
|
2015-11-06 20:08:33 +07:00
|
|
|
extern void intel_fbdev_initial_config_async(struct drm_device *dev);
|
2017-07-15 05:46:55 +07:00
|
|
|
extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
|
|
|
|
extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
|
2014-08-13 19:09:46 +07:00
|
|
|
extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
|
2013-10-08 22:44:49 +07:00
|
|
|
extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
|
|
|
|
extern void intel_fbdev_restore_mode(struct drm_device *dev);
|
2013-10-09 14:18:51 +07:00
|
|
|
#else
|
|
|
|
static inline int intel_fbdev_init(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2013-09-24 23:52:53 +07:00
|
|
|
|
2015-11-06 20:08:33 +07:00
|
|
|
static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
|
2013-10-09 14:18:51 +07:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2017-07-15 05:46:55 +07:00
|
|
|
static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
|
2013-10-09 14:18:51 +07:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2014-08-13 19:09:46 +07:00
|
|
|
static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
|
2013-10-09 14:18:51 +07:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2016-10-04 14:53:48 +07:00
|
|
|
static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2013-10-08 22:44:49 +07:00
|
|
|
static inline void intel_fbdev_restore_mode(struct drm_device *dev)
|
2013-10-09 14:18:51 +07:00
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
2013-09-24 23:52:53 +07:00
|
|
|
|
2014-12-08 23:09:10 +07:00
|
|
|
/* intel_fbc.c */
|
2016-01-19 20:35:50 +07:00
|
|
|
void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
|
2017-11-18 02:19:14 +07:00
|
|
|
struct intel_atomic_state *state);
|
2015-10-15 03:45:36 +07:00
|
|
|
bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
|
2016-06-14 19:24:20 +07:00
|
|
|
void intel_fbc_pre_update(struct intel_crtc *crtc,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
struct intel_plane_state *plane_state);
|
2016-01-19 20:35:44 +07:00
|
|
|
void intel_fbc_post_update(struct intel_crtc *crtc);
|
2014-12-08 23:09:10 +07:00
|
|
|
void intel_fbc_init(struct drm_i915_private *dev_priv);
|
2016-01-19 20:35:48 +07:00
|
|
|
void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
|
2016-06-14 19:24:20 +07:00
|
|
|
void intel_fbc_enable(struct intel_crtc *crtc,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
struct intel_plane_state *plane_state);
|
2016-01-19 20:35:46 +07:00
|
|
|
void intel_fbc_disable(struct intel_crtc *crtc);
|
|
|
|
void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
|
2015-02-14 02:23:46 +07:00
|
|
|
void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
|
|
|
|
unsigned int frontbuffer_bits,
|
|
|
|
enum fb_op_origin origin);
|
|
|
|
void intel_fbc_flush(struct drm_i915_private *dev_priv,
|
2015-07-15 02:29:10 +07:00
|
|
|
unsigned int frontbuffer_bits, enum fb_op_origin origin);
|
2015-07-08 01:26:04 +07:00
|
|
|
void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
|
2016-09-13 20:38:57 +07:00
|
|
|
void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
|
2014-12-08 23:09:10 +07:00
|
|
|
|
2013-09-24 23:52:53 +07:00
|
|
|
/* intel_hdmi.c */
|
2016-11-23 21:21:44 +07:00
|
|
|
void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
|
|
|
|
enum port port);
|
2013-09-25 01:48:31 +07:00
|
|
|
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
|
|
|
|
struct intel_connector *intel_connector);
|
|
|
|
struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
|
|
|
|
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
|
2016-08-09 22:04:05 +07:00
|
|
|
struct intel_crtc_state *pipe_config,
|
|
|
|
struct drm_connector_state *conn_state);
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 18:24:03 +07:00
|
|
|
void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
|
|
|
|
struct drm_connector *connector,
|
|
|
|
bool high_tmds_clock_ratio,
|
|
|
|
bool scrambling);
|
2016-05-03 02:08:24 +07:00
|
|
|
void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
|
2017-08-18 20:49:55 +07:00
|
|
|
void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
|
2013-09-24 23:52:53 +07:00
|
|
|
|
|
|
|
|
|
|
|
/* intel_lvds.c */
|
2016-11-23 21:21:44 +07:00
|
|
|
void intel_lvds_init(struct drm_i915_private *dev_priv);
|
2016-06-21 15:51:47 +07:00
|
|
|
struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
|
2013-09-25 01:48:31 +07:00
|
|
|
bool intel_is_dual_link_lvds(struct drm_device *dev);
|
2013-09-24 23:52:53 +07:00
|
|
|
|
|
|
|
|
|
|
|
/* intel_modes.c */
|
|
|
|
int intel_connector_update_modes(struct drm_connector *connector,
|
2013-09-25 01:48:31 +07:00
|
|
|
struct edid *edid);
|
2013-09-24 23:52:53 +07:00
|
|
|
int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
|
2013-09-25 01:48:31 +07:00
|
|
|
void intel_attach_force_audio_property(struct drm_connector *connector);
|
|
|
|
void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
|
2015-09-25 20:39:30 +07:00
|
|
|
void intel_attach_aspect_ratio_property(struct drm_connector *connector);
|
2013-09-24 23:52:53 +07:00
|
|
|
|
|
|
|
|
|
|
|
/* intel_overlay.c */
|
2016-05-12 18:43:23 +07:00
|
|
|
void intel_setup_overlay(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
|
2013-09-25 01:48:31 +07:00
|
|
|
int intel_overlay_switch_off(struct intel_overlay *overlay);
|
2016-05-12 18:43:23 +07:00
|
|
|
int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv);
|
|
|
|
int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv);
|
2014-11-26 22:07:29 +07:00
|
|
|
void intel_overlay_reset(struct drm_i915_private *dev_priv);
|
2013-09-24 23:52:53 +07:00
|
|
|
|
|
|
|
|
|
|
|
/* intel_panel.c */
|
2013-09-25 01:48:31 +07:00
|
|
|
int intel_panel_init(struct intel_panel *panel,
|
2014-02-11 15:56:36 +07:00
|
|
|
struct drm_display_mode *fixed_mode,
|
2017-08-10 02:48:53 +07:00
|
|
|
struct drm_display_mode *alt_fixed_mode,
|
2014-02-11 15:56:36 +07:00
|
|
|
struct drm_display_mode *downclock_mode);
|
2013-09-25 01:48:31 +07:00
|
|
|
void intel_panel_fini(struct intel_panel *panel);
|
|
|
|
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
|
|
|
|
struct drm_display_mode *adjusted_mode);
|
|
|
|
void intel_pch_panel_fitting(struct intel_crtc *crtc,
|
2015-01-15 19:55:21 +07:00
|
|
|
struct intel_crtc_state *pipe_config,
|
2013-09-25 01:48:31 +07:00
|
|
|
int fitting_mode);
|
|
|
|
void intel_gmch_panel_fitting(struct intel_crtc *crtc,
|
2015-01-15 19:55:21 +07:00
|
|
|
struct intel_crtc_state *pipe_config,
|
2013-09-25 01:48:31 +07:00
|
|
|
int fitting_mode);
|
2017-06-12 17:21:14 +07:00
|
|
|
void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
|
2014-06-24 22:27:40 +07:00
|
|
|
u32 level, u32 max);
|
2016-06-24 20:00:13 +07:00
|
|
|
int intel_panel_setup_backlight(struct drm_connector *connector,
|
|
|
|
enum pipe pipe);
|
2017-06-12 17:21:13 +07:00
|
|
|
void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state);
|
|
|
|
void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
|
2013-11-08 21:48:53 +07:00
|
|
|
void intel_panel_destroy_backlight(struct drm_connector *connector);
|
2016-12-13 15:02:47 +07:00
|
|
|
enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
|
2013-12-10 15:07:36 +07:00
|
|
|
extern struct drm_display_mode *intel_find_panel_downclock(
|
2016-12-13 15:02:48 +07:00
|
|
|
struct drm_i915_private *dev_priv,
|
2013-12-10 15:07:36 +07:00
|
|
|
struct drm_display_mode *fixed_mode,
|
|
|
|
struct drm_connector *connector);
|
2016-06-17 17:40:34 +07:00
|
|
|
|
|
|
|
#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
|
2016-06-24 20:00:15 +07:00
|
|
|
int intel_backlight_device_register(struct intel_connector *connector);
|
2016-06-17 17:40:34 +07:00
|
|
|
void intel_backlight_device_unregister(struct intel_connector *connector);
|
|
|
|
#else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
|
2017-11-27 22:10:27 +07:00
|
|
|
static inline int intel_backlight_device_register(struct intel_connector *connector)
|
2016-06-24 20:00:15 +07:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2016-06-17 17:40:34 +07:00
|
|
|
static inline void intel_backlight_device_unregister(struct intel_connector *connector)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
|
2014-11-07 20:19:46 +07:00
|
|
|
|
2013-09-24 23:52:53 +07:00
|
|
|
|
2014-11-14 23:52:28 +07:00
|
|
|
/* intel_psr.c */
|
2017-08-18 20:49:56 +07:00
|
|
|
void intel_psr_enable(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *crtc_state);
|
|
|
|
void intel_psr_disable(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *old_crtc_state);
|
2016-08-04 22:32:38 +07:00
|
|
|
void intel_psr_invalidate(struct drm_i915_private *dev_priv,
|
2015-06-18 15:30:27 +07:00
|
|
|
unsigned frontbuffer_bits);
|
2016-08-04 22:32:38 +07:00
|
|
|
void intel_psr_flush(struct drm_i915_private *dev_priv,
|
2015-07-09 06:21:31 +07:00
|
|
|
unsigned frontbuffer_bits,
|
|
|
|
enum fb_op_origin origin);
|
2016-11-23 21:21:44 +07:00
|
|
|
void intel_psr_init(struct drm_i915_private *dev_priv);
|
2016-08-04 22:32:38 +07:00
|
|
|
void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
|
2015-06-18 15:30:27 +07:00
|
|
|
unsigned frontbuffer_bits);
|
2017-10-12 20:02:01 +07:00
|
|
|
void intel_psr_compute_config(struct intel_dp *intel_dp,
|
|
|
|
struct intel_crtc_state *crtc_state);
|
2014-11-14 23:52:28 +07:00
|
|
|
|
2014-09-30 15:56:38 +07:00
|
|
|
/* intel_runtime_pm.c */
|
|
|
|
int intel_power_domains_init(struct drm_i915_private *);
|
2014-09-30 15:56:39 +07:00
|
|
|
void intel_power_domains_fini(struct drm_i915_private *);
|
2015-11-17 22:33:53 +07:00
|
|
|
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
|
|
|
|
void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
|
2017-02-17 22:39:46 +07:00
|
|
|
void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
|
2016-04-01 20:02:42 +07:00
|
|
|
void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
|
|
|
|
void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
|
2014-09-30 15:56:39 +07:00
|
|
|
void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
|
2015-11-20 22:55:33 +07:00
|
|
|
const char *
|
|
|
|
intel_display_power_domain_str(enum intel_display_power_domain domain);
|
2014-09-30 15:56:38 +07:00
|
|
|
|
2014-09-30 15:56:39 +07:00
|
|
|
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
|
|
|
|
enum intel_display_power_domain domain);
|
|
|
|
bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
|
|
|
|
enum intel_display_power_domain domain);
|
2014-09-30 15:56:38 +07:00
|
|
|
void intel_display_power_get(struct drm_i915_private *dev_priv,
|
|
|
|
enum intel_display_power_domain domain);
|
2016-02-17 19:17:42 +07:00
|
|
|
bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
|
|
|
|
enum intel_display_power_domain domain);
|
2014-09-30 15:56:38 +07:00
|
|
|
void intel_display_power_put(struct drm_i915_private *dev_priv,
|
|
|
|
enum intel_display_power_domain domain);
|
2015-12-16 01:10:33 +07:00
|
|
|
|
|
|
|
static inline void
|
|
|
|
assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2017-10-11 04:30:04 +07:00
|
|
|
WARN_ONCE(dev_priv->runtime_pm.suspended,
|
2015-12-16 01:10:33 +07:00
|
|
|
"Device suspended during HW access\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
assert_rpm_device_not_suspended(dev_priv);
|
2017-10-11 04:30:04 +07:00
|
|
|
WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
|
2017-03-02 14:41:57 +07:00
|
|
|
"RPM wakelock ref not held during HW access");
|
2015-12-16 01:10:33 +07:00
|
|
|
}
|
|
|
|
|
2015-12-16 07:52:19 +07:00
|
|
|
/**
|
|
|
|
* disable_rpm_wakeref_asserts - disable the RPM assert checks
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* This function disable asserts that check if we hold an RPM wakelock
|
|
|
|
* reference, while keeping the device-not-suspended checks still enabled.
|
|
|
|
* It's meant to be used only in special circumstances where our rule about
|
|
|
|
* the wakelock refcount wrt. the device power state doesn't hold. According
|
|
|
|
* to this rule at any point where we access the HW or want to keep the HW in
|
|
|
|
* an active state we must hold an RPM wakelock reference acquired via one of
|
|
|
|
* the intel_runtime_pm_get() helpers. Currently there are a few special spots
|
|
|
|
* where this rule doesn't hold: the IRQ and suspend/resume handlers, the
|
|
|
|
* forcewake release timer, and the GPU RPS and hangcheck works. All other
|
|
|
|
* users should avoid using this function.
|
|
|
|
*
|
|
|
|
* Any calls to this function must have a symmetric call to
|
|
|
|
* enable_rpm_wakeref_asserts().
|
|
|
|
*/
|
|
|
|
static inline void
|
|
|
|
disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2017-10-11 04:30:04 +07:00
|
|
|
atomic_inc(&dev_priv->runtime_pm.wakeref_count);
|
2015-12-16 07:52:19 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* enable_rpm_wakeref_asserts - re-enable the RPM assert checks
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* This function re-enables the RPM assert checks after disabling them with
|
|
|
|
* disable_rpm_wakeref_asserts. It's meant to be used only in special
|
|
|
|
* circumstances otherwise its use should be avoided.
|
|
|
|
*
|
|
|
|
* Any calls to this function must have a symmetric call to
|
|
|
|
* disable_rpm_wakeref_asserts().
|
|
|
|
*/
|
|
|
|
static inline void
|
|
|
|
enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2017-10-11 04:30:04 +07:00
|
|
|
atomic_dec(&dev_priv->runtime_pm.wakeref_count);
|
2015-12-16 07:52:19 +07:00
|
|
|
}
|
|
|
|
|
2014-09-30 15:56:38 +07:00
|
|
|
void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
|
2016-02-17 19:17:42 +07:00
|
|
|
bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
|
2014-09-30 15:56:38 +07:00
|
|
|
void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
|
|
|
|
|
2014-09-30 15:56:40 +07:00
|
|
|
void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
|
|
|
|
|
2015-07-09 03:45:54 +07:00
|
|
|
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
|
|
|
|
bool override, unsigned int mask);
|
drm/i915: Trick CL2 into life on CHV when using pipe B with port B
Normmally the common lane in a PHY channel gets powered up when some
of the data lanes get powered up. But when we're driving port B with
pipe B we don't want to enabled any of the data lanes, and just want
the DPLL in the common lane to be active.
To make that happens we have to temporarily enable some data lanes
after which we can access the DPLL registers in the common lane. Once
the pipe is up and running we can drop the power override on the data
lanes allowing them to shut down. From this point forward the common
lane will in fact stay powered on until the data lanes in the other
channel get powered down.
Ville's extended explanation from the review thread:
On Wed, Aug 19, 2015 at 07:47:41AM +0530, Deepak wrote:
> One Q, why only for port B? Port C is also in same common lane right?
Port B is in the first PHY channel which also houses CL1. CL1 always
powers up whenever any lanes in either PHY channel are powered up.
CL2 only powers up if lanes in the second channel (ie. the one with
port C) powers up.
So in this scenario (pipe B->port B) we want the DPLL from CL2, but
ideally we only want to power up the lanes for port B. Powering up
port B lanes will only power up CL1, but as we need CL2 instead we
need to, temporarily, power up some lanes in port C as well.
Crossing the streams the other way (pipe A->port C) is not a problem
since CL1 powers up whenever anything else powers up. So powering up
some port C lanes is enough on its own to make the CL1 DPLL
operational, even though CL1 and the lanes live in separate channels.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
[danvet: Amend commit message with extended explanation.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-09 03:45:55 +07:00
|
|
|
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
|
|
|
|
enum dpio_channel ch, bool override);
|
2015-07-09 03:45:54 +07:00
|
|
|
|
|
|
|
|
2013-09-24 23:52:53 +07:00
|
|
|
/* intel_pm.c */
|
2016-11-01 03:37:22 +07:00
|
|
|
void intel_init_clock_gating(struct drm_i915_private *dev_priv);
|
2016-11-01 03:37:23 +07:00
|
|
|
void intel_suspend_hw(struct drm_i915_private *dev_priv);
|
2016-10-13 17:03:10 +07:00
|
|
|
int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
|
2016-11-01 03:37:03 +07:00
|
|
|
void intel_update_watermarks(struct intel_crtc *crtc);
|
2016-11-01 03:37:25 +07:00
|
|
|
void intel_init_pm(struct drm_i915_private *dev_priv);
|
2016-03-16 18:38:54 +07:00
|
|
|
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
|
2016-12-01 21:16:45 +07:00
|
|
|
void intel_pm_setup(struct drm_i915_private *dev_priv);
|
2013-09-25 01:48:31 +07:00
|
|
|
void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_gpu_ips_teardown(void);
|
2016-05-10 20:10:04 +07:00
|
|
|
void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
|
2016-07-22 03:16:19 +07:00
|
|
|
void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
|
2016-05-10 20:10:04 +07:00
|
|
|
void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
|
2016-07-22 03:16:19 +07:00
|
|
|
void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
|
2015-03-18 16:48:22 +07:00
|
|
|
void gen6_rps_busy(struct drm_i915_private *dev_priv);
|
|
|
|
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
|
2013-10-09 00:39:29 +07:00
|
|
|
void gen6_rps_idle(struct drm_i915_private *dev_priv);
|
2017-06-28 19:35:48 +07:00
|
|
|
void gen6_rps_boost(struct drm_i915_gem_request *rq,
|
|
|
|
struct intel_rps_client *rps);
|
2017-04-22 01:14:29 +07:00
|
|
|
void g4x_wm_get_hw_state(struct drm_device *dev);
|
2015-06-25 02:00:03 +07:00
|
|
|
void vlv_wm_get_hw_state(struct drm_device *dev);
|
2013-10-14 18:55:24 +07:00
|
|
|
void ilk_wm_get_hw_state(struct drm_device *dev);
|
2014-11-05 00:06:45 +07:00
|
|
|
void skl_wm_get_hw_state(struct drm_device *dev);
|
2014-11-05 00:06:52 +07:00
|
|
|
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
|
|
|
|
struct skl_ddb_allocation *ddb /* out */);
|
2016-10-15 04:31:55 +07:00
|
|
|
void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
|
|
|
|
struct skl_pipe_wm *out);
|
2017-04-22 01:14:29 +07:00
|
|
|
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
|
2017-03-03 00:15:02 +07:00
|
|
|
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
|
2016-09-23 04:00:27 +07:00
|
|
|
bool intel_can_enable_sagv(struct drm_atomic_state *state);
|
|
|
|
int intel_enable_sagv(struct drm_i915_private *dev_priv);
|
|
|
|
int intel_disable_sagv(struct drm_i915_private *dev_priv);
|
2016-10-15 04:31:56 +07:00
|
|
|
bool skl_wm_level_equals(const struct skl_wm_level *l1,
|
|
|
|
const struct skl_wm_level *l2);
|
2017-10-10 17:17:03 +07:00
|
|
|
bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
|
|
|
|
const struct skl_ddb_entry **entries,
|
2016-11-08 19:55:35 +07:00
|
|
|
const struct skl_ddb_entry *ddb,
|
|
|
|
int ignore);
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 08:20:13 +07:00
|
|
|
bool ilk_disable_lp_wm(struct drm_device *dev);
|
2017-05-26 22:15:46 +07:00
|
|
|
int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
|
|
|
|
struct intel_crtc_state *cstate);
|
2017-08-17 20:45:28 +07:00
|
|
|
void intel_init_ipc(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_enable_ipc(struct drm_i915_private *dev_priv);
|
2012-05-10 01:37:31 +07:00
|
|
|
|
2013-09-24 23:52:53 +07:00
|
|
|
/* intel_sdvo.c */
|
2016-11-23 21:21:44 +07:00
|
|
|
bool intel_sdvo_init(struct drm_i915_private *dev_priv,
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 20:33:26 +07:00
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i915_reg_t reg, enum port port);
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2013-02-19 00:08:49 +07:00
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2013-07-12 04:44:58 +07:00
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2013-09-24 23:52:53 +07:00
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/* intel_sprite.c */
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2016-05-18 15:34:38 +07:00
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int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
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int usecs);
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2016-11-01 03:37:00 +07:00
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struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
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2016-10-25 22:58:02 +07:00
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enum pipe pipe, int plane);
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2013-09-25 01:48:31 +07:00
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int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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2017-08-23 22:22:21 +07:00
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void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
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void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
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2017-10-18 03:08:09 +07:00
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void skl_update_plane(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state);
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2017-10-18 03:08:10 +07:00
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void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
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2017-11-18 02:19:08 +07:00
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bool skl_plane_get_hw_state(struct intel_plane *plane);
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2013-09-24 23:52:53 +07:00
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/* intel_tv.c */
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2016-11-23 21:21:44 +07:00
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void intel_tv_init(struct drm_i915_private *dev_priv);
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2013-09-04 22:25:25 +07:00
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2014-12-24 01:41:52 +07:00
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/* intel_atomic.c */
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2017-05-01 20:37:57 +07:00
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int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
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const struct drm_connector_state *state,
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struct drm_property *property,
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uint64_t *val);
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int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
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struct drm_connector_state *state,
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struct drm_property *property,
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uint64_t val);
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int intel_digital_connector_atomic_check(struct drm_connector *conn,
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struct drm_connector_state *new_state);
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struct drm_connector_state *
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intel_digital_connector_duplicate_state(struct drm_connector *connector);
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2015-01-22 07:35:47 +07:00
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struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
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void intel_crtc_destroy_state(struct drm_crtc *crtc,
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struct drm_crtc_state *state);
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2015-06-04 15:21:28 +07:00
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struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
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void intel_atomic_state_clear(struct drm_atomic_state *);
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2015-03-20 21:18:01 +07:00
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static inline struct intel_crtc_state *
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intel_atomic_get_crtc_state(struct drm_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_crtc_state *crtc_state;
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crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
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if (IS_ERR(crtc_state))
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2015-04-25 16:34:29 +07:00
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return ERR_CAST(crtc_state);
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2015-03-20 21:18:01 +07:00
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return to_intel_crtc_state(crtc_state);
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}
|
2016-03-01 17:07:22 +07:00
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2016-12-01 22:49:38 +07:00
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static inline struct intel_crtc_state *
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intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
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struct intel_crtc *crtc)
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{
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struct drm_crtc_state *crtc_state;
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crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
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if (crtc_state)
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return to_intel_crtc_state(crtc_state);
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else
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return NULL;
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}
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2016-03-01 17:07:22 +07:00
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static inline struct intel_plane_state *
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intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
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struct intel_plane *plane)
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{
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struct drm_plane_state *plane_state;
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plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
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return to_intel_plane_state(plane_state);
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}
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|
2017-02-23 14:15:59 +07:00
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int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
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struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state);
|
2015-01-22 07:35:44 +07:00
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|
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/* intel_atomic_plane.c */
|
2015-01-22 07:35:41 +07:00
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struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
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2014-12-24 01:41:52 +07:00
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struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
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void intel_plane_destroy_state(struct drm_plane *plane,
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struct drm_plane_state *state);
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|
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extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
|
2017-08-23 22:22:23 +07:00
|
|
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int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
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struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *old_plane_state,
|
2016-12-12 17:34:55 +07:00
|
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struct intel_plane_state *intel_state);
|
2014-12-24 01:41:52 +07:00
|
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|
|
2016-03-16 17:57:14 +07:00
|
|
|
/* intel_color.c */
|
|
|
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void intel_color_init(struct drm_crtc *crtc);
|
2016-03-16 17:57:16 +07:00
|
|
|
int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
|
2016-03-30 22:16:34 +07:00
|
|
|
void intel_color_set_csc(struct drm_crtc_state *crtc_state);
|
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void intel_color_load_luts(struct drm_crtc_state *crtc_state);
|
2016-03-16 17:57:14 +07:00
|
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|
2016-10-14 21:26:49 +07:00
|
|
|
/* intel_lspcon.c */
|
|
|
|
bool lspcon_init(struct intel_digital_port *intel_dig_port);
|
2016-10-14 21:26:52 +07:00
|
|
|
void lspcon_resume(struct intel_lspcon *lspcon);
|
2016-11-22 02:15:06 +07:00
|
|
|
void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
|
2016-12-12 19:29:48 +07:00
|
|
|
|
|
|
|
/* intel_pipe_crc.c */
|
|
|
|
int intel_pipe_crc_create(struct drm_minor *minor);
|
2017-01-10 20:43:04 +07:00
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
|
|
|
|
size_t *values_cnt);
|
|
|
|
#else
|
|
|
|
#define intel_crtc_set_crc_source NULL
|
|
|
|
#endif
|
2016-12-12 19:29:48 +07:00
|
|
|
extern const struct file_operations i915_display_crc_ctl_fops;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
#endif /* __INTEL_DRV_H__ */
|