2015-04-21 03:51:00 +07:00
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#ifndef __AMDGPU_H__
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#define __AMDGPU_H__
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#include <linux/atomic.h>
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#include <linux/wait.h>
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#include <linux/list.h>
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#include <linux/kref.h>
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2017-03-30 19:03:59 +07:00
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#include <linux/rbtree.h>
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2015-04-21 03:51:00 +07:00
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#include <linux/hashtable.h>
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2016-10-25 19:00:45 +07:00
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#include <linux/dma-fence.h>
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2015-04-21 03:51:00 +07:00
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2017-04-24 11:50:21 +07:00
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#include <drm/ttm/ttm_bo_api.h>
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#include <drm/ttm/ttm_bo_driver.h>
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#include <drm/ttm/ttm_placement.h>
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#include <drm/ttm/ttm_module.h>
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#include <drm/ttm/ttm_execbuf_util.h>
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2015-04-21 03:51:00 +07:00
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2015-07-29 01:20:03 +07:00
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#include <drm/drmP.h>
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2015-04-21 03:51:00 +07:00
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#include <drm/drm_gem.h>
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2015-04-24 16:37:30 +07:00
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#include <drm/amdgpu_drm.h>
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2017-12-06 23:49:39 +07:00
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#include <drm/gpu_scheduler.h>
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2015-04-21 03:51:00 +07:00
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2017-02-02 12:38:22 +07:00
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#include <kgd_kfd_interface.h>
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2017-09-29 14:58:19 +07:00
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#include "dm_pp_interface.h"
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#include "kgd_pp_interface.h"
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2017-02-02 12:38:22 +07:00
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2015-05-23 01:39:35 +07:00
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#include "amd_shared.h"
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2015-04-21 03:51:00 +07:00
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#include "amdgpu_mode.h"
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#include "amdgpu_ih.h"
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#include "amdgpu_irq.h"
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#include "amdgpu_ucode.h"
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2016-08-02 10:32:41 +07:00
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#include "amdgpu_ttm.h"
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2017-03-04 06:37:23 +07:00
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#include "amdgpu_psp.h"
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2015-04-21 03:51:00 +07:00
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#include "amdgpu_gds.h"
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2016-09-28 17:36:44 +07:00
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#include "amdgpu_sync.h"
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2016-09-28 20:33:18 +07:00
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#include "amdgpu_ring.h"
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2016-09-28 20:41:50 +07:00
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#include "amdgpu_vm.h"
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2016-10-07 22:40:09 +07:00
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#include "amdgpu_dpm.h"
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2015-09-23 04:05:20 +07:00
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#include "amdgpu_acp.h"
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2017-01-02 22:07:33 +07:00
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#include "amdgpu_uvd.h"
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2017-01-10 23:02:58 +07:00
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#include "amdgpu_vce.h"
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2017-05-12 03:27:33 +07:00
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#include "amdgpu_vcn.h"
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2017-09-13 01:29:07 +07:00
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#include "amdgpu_mn.h"
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2018-01-12 20:52:22 +07:00
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#include "amdgpu_gmc.h"
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2017-09-13 02:58:20 +07:00
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#include "amdgpu_dm.h"
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2016-09-19 11:13:58 +07:00
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#include "amdgpu_virt.h"
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2017-07-07 03:02:41 +07:00
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#include "amdgpu_gart.h"
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2017-12-15 03:23:14 +07:00
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#include "amdgpu_debugfs.h"
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2017-09-29 14:58:19 +07:00
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2015-04-21 03:51:00 +07:00
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/*
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* Modules parameters.
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*/
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extern int amdgpu_modeset;
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extern int amdgpu_vram_limit;
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2017-06-28 09:33:17 +07:00
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extern int amdgpu_vis_vram_limit;
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2017-08-21 22:58:25 +07:00
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extern int amdgpu_gart_size;
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2017-07-07 18:17:45 +07:00
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extern int amdgpu_gtt_size;
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2016-08-18 04:49:27 +07:00
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extern int amdgpu_moverate;
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2015-04-21 03:51:00 +07:00
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extern int amdgpu_benchmarking;
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extern int amdgpu_testing;
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extern int amdgpu_audio;
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extern int amdgpu_disp_priority;
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extern int amdgpu_hw_i2c;
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extern int amdgpu_pcie_gen2;
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extern int amdgpu_msi;
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extern int amdgpu_lockup_timeout;
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extern int amdgpu_dpm;
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2016-11-01 14:35:38 +07:00
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extern int amdgpu_fw_load_type;
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2015-04-21 03:51:00 +07:00
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extern int amdgpu_aspm;
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extern int amdgpu_runtime_pm;
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2017-09-19 13:36:08 +07:00
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extern uint amdgpu_ip_block_mask;
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2015-04-21 03:51:00 +07:00
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extern int amdgpu_bapm;
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extern int amdgpu_deep_color;
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extern int amdgpu_vm_size;
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extern int amdgpu_vm_block_size;
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2017-08-15 15:05:59 +07:00
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extern int amdgpu_vm_fragment_size;
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2015-09-28 17:31:26 +07:00
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extern int amdgpu_vm_fault_stop;
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2015-09-10 19:00:35 +07:00
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extern int amdgpu_vm_debug;
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2017-06-09 22:26:57 +07:00
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extern int amdgpu_vm_update_mode;
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2017-09-13 02:58:20 +07:00
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extern int amdgpu_dc;
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2017-09-13 07:02:11 +07:00
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extern int amdgpu_dc_log;
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2015-07-30 15:36:58 +07:00
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extern int amdgpu_sched_jobs;
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2015-07-30 15:44:05 +07:00
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extern int amdgpu_sched_hw_submission;
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2016-11-02 12:38:37 +07:00
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extern int amdgpu_no_evict;
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extern int amdgpu_direct_gma_size;
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2017-09-19 13:36:08 +07:00
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extern uint amdgpu_pcie_gen_cap;
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extern uint amdgpu_pcie_lane_cap;
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extern uint amdgpu_cg_mask;
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extern uint amdgpu_pg_mask;
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extern uint amdgpu_sdma_phase_quantum;
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2016-06-18 00:31:33 +07:00
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extern char *amdgpu_disable_cu;
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2016-08-10 15:01:25 +07:00
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extern char *amdgpu_virtual_display;
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2017-09-19 13:36:08 +07:00
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extern uint amdgpu_pp_feature_mask;
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2016-08-24 20:51:49 +07:00
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extern int amdgpu_vram_page_split;
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2017-03-28 23:52:08 +07:00
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extern int amdgpu_ngg;
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extern int amdgpu_prim_buf_per_se;
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extern int amdgpu_pos_buf_per_se;
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extern int amdgpu_cntl_sb_buf_per_se;
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extern int amdgpu_param_buf_per_se;
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drm/amdgpu/SRIOV:implement guilty job TDR for(V2)
1,TDR will kickout guilty job if it hang exceed the threshold
of the given one from kernel paramter "job_hang_limit", that
way a bad command stream will not infinitly cause GPU hang.
by default this threshold is 1 so a job will be kicked out
after it hang.
2,if a job timeout TDR routine will not reset all sched/ring,
instead if will only reset on the givn one which is indicated
by @job of amdgpu_sriov_gpu_reset, that way we don't need to
reset and recover each sched/ring if we already know which job
cause GPU hang.
3,unblock sriov_gpu_reset for AI family.
V2:
1:put kickout guilty job after sched parked.
2:since parking scheduler prior to kickout already occupies a
while, we can do last check on the in question job before
doing hw_reset.
TODO:
1:when a job is considered as guilty, we should mark some flag
in its fence status flag, and let UMD side aware that this
fence signaling is not due to job complete but job hang.
2:if gpu reset cause all video memory lost, we need introduce
a new policy to implement TDR, like drop all jobs not yet
signaled, and all IOCTL on this device will return ERROR
DEVICE_LOST.
this will be implemented later.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-11 12:36:44 +07:00
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extern int amdgpu_job_hang_limit;
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2017-05-26 13:40:36 +07:00
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extern int amdgpu_lbpw;
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2017-09-26 23:22:46 +07:00
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extern int amdgpu_compute_multipipe;
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2017-12-13 02:09:30 +07:00
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extern int amdgpu_gpu_recovery;
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2018-02-02 05:37:50 +07:00
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extern int amdgpu_emu_mode;
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2015-04-21 03:51:00 +07:00
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2017-06-05 16:53:55 +07:00
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#ifdef CONFIG_DRM_AMDGPU_SI
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extern int amdgpu_si_support;
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#endif
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2017-06-05 16:43:27 +07:00
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#ifdef CONFIG_DRM_AMDGPU_CIK
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extern int amdgpu_cik_support;
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#endif
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2015-04-21 03:51:00 +07:00
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2017-04-21 15:40:00 +07:00
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#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
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2015-07-21 14:53:04 +07:00
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#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
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2015-04-21 03:51:00 +07:00
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#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
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#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
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/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
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#define AMDGPU_IB_POOL_SIZE 16
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#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
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#define AMDGPUFB_CONN_LIMIT 4
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2016-09-24 03:23:41 +07:00
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#define AMDGPU_BIOS_NUM_SCRATCH 16
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2015-04-21 03:51:00 +07:00
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2015-09-01 11:54:27 +07:00
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/* max number of IP instances */
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#define AMDGPU_MAX_SDMA_INSTANCES 2
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2015-04-21 03:51:00 +07:00
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/* hard reset data */
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#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
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/* reset flags */
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#define AMDGPU_RESET_GFX (1 << 0)
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#define AMDGPU_RESET_COMPUTE (1 << 1)
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#define AMDGPU_RESET_DMA (1 << 2)
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#define AMDGPU_RESET_CP (1 << 3)
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#define AMDGPU_RESET_GRBM (1 << 4)
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#define AMDGPU_RESET_DMA1 (1 << 5)
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#define AMDGPU_RESET_RLC (1 << 6)
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#define AMDGPU_RESET_SEM (1 << 7)
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#define AMDGPU_RESET_IH (1 << 8)
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#define AMDGPU_RESET_VMC (1 << 9)
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#define AMDGPU_RESET_MC (1 << 10)
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#define AMDGPU_RESET_DISPLAY (1 << 11)
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#define AMDGPU_RESET_UVD (1 << 12)
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#define AMDGPU_RESET_VCE (1 << 13)
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#define AMDGPU_RESET_VCE1 (1 << 14)
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/* GFX current status */
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#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
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#define AMDGPU_GFX_SAFE_MODE 0x00000001L
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#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
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#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
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#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
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/* max cursor sizes (in pixels) */
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#define CIK_CURSOR_WIDTH 128
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#define CIK_CURSOR_HEIGHT 128
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struct amdgpu_device;
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struct amdgpu_ib;
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struct amdgpu_cs_parser;
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2015-08-18 14:16:40 +07:00
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struct amdgpu_job;
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2015-04-21 03:51:00 +07:00
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struct amdgpu_irq_src;
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2015-08-17 09:48:26 +07:00
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struct amdgpu_fpriv;
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2017-09-06 21:15:28 +07:00
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struct amdgpu_bo_va_mapping;
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2015-04-21 03:51:00 +07:00
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enum amdgpu_cp_irq {
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AMDGPU_CP_IRQ_GFX_EOP = 0,
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AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
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AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
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AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
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AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
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AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
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AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
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AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
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AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
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AMDGPU_CP_IRQ_LAST
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};
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enum amdgpu_sdma_irq {
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AMDGPU_SDMA_IRQ_TRAP0 = 0,
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AMDGPU_SDMA_IRQ_TRAP1,
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AMDGPU_SDMA_IRQ_LAST
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};
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enum amdgpu_thermal_irq {
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AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
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AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
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AMDGPU_THERMAL_IRQ_LAST
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};
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2016-12-23 14:00:01 +07:00
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enum amdgpu_kiq_irq {
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AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
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AMDGPU_CP_KIQ_IRQ_LAST
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};
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2017-12-16 04:18:00 +07:00
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int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
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enum amd_ip_block_type block_type,
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enum amd_clockgating_state state);
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int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
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enum amd_ip_block_type block_type,
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enum amd_powergating_state state);
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void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
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u32 *flags);
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int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
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enum amd_ip_block_type block_type);
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bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
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enum amd_ip_block_type block_type);
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2015-04-21 03:51:00 +07:00
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2016-10-14 04:41:13 +07:00
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#define AMDGPU_MAX_IP_NUM 16
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struct amdgpu_ip_block_status {
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bool valid;
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bool sw;
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bool hw;
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bool late_initialized;
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bool hang;
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};
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2015-04-21 03:51:00 +07:00
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struct amdgpu_ip_block_version {
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2016-10-14 04:41:13 +07:00
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const enum amd_ip_block_type type;
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const u32 major;
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const u32 minor;
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const u32 rev;
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2015-05-23 01:39:35 +07:00
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const struct amd_ip_funcs *funcs;
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2015-04-21 03:51:00 +07:00
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};
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2016-10-14 04:41:13 +07:00
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struct amdgpu_ip_block {
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struct amdgpu_ip_block_status status;
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const struct amdgpu_ip_block_version *version;
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};
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2017-12-16 04:18:00 +07:00
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|
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int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
|
|
|
|
enum amd_ip_block_type type,
|
|
|
|
u32 major, u32 minor);
|
2015-04-21 03:51:00 +07:00
|
|
|
|
2017-12-16 04:18:00 +07:00
|
|
|
struct amdgpu_ip_block *
|
|
|
|
amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
|
|
|
|
enum amd_ip_block_type type);
|
2016-10-14 04:41:13 +07:00
|
|
|
|
2017-12-16 04:18:00 +07:00
|
|
|
int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
|
|
|
|
const struct amdgpu_ip_block_version *ip_block_version);
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
|
|
|
|
struct amdgpu_buffer_funcs {
|
|
|
|
/* maximum bytes in a single operation */
|
|
|
|
uint32_t copy_max_bytes;
|
|
|
|
|
|
|
|
/* number of dw to reserve per operation */
|
|
|
|
unsigned copy_num_dw;
|
|
|
|
|
|
|
|
/* used for buffer migration */
|
2015-08-25 16:23:45 +07:00
|
|
|
void (*emit_copy_buffer)(struct amdgpu_ib *ib,
|
2015-04-21 03:51:00 +07:00
|
|
|
/* src addr in bytes */
|
|
|
|
uint64_t src_offset,
|
|
|
|
/* dst addr in bytes */
|
|
|
|
uint64_t dst_offset,
|
|
|
|
/* number of byte to transfer */
|
|
|
|
uint32_t byte_count);
|
|
|
|
|
|
|
|
/* maximum bytes in a single operation */
|
|
|
|
uint32_t fill_max_bytes;
|
|
|
|
|
|
|
|
/* number of dw to reserve per operation */
|
|
|
|
unsigned fill_num_dw;
|
|
|
|
|
|
|
|
/* used for buffer clearing */
|
2015-08-27 12:46:09 +07:00
|
|
|
void (*emit_fill_buffer)(struct amdgpu_ib *ib,
|
2015-04-21 03:51:00 +07:00
|
|
|
/* value to write to memory */
|
|
|
|
uint32_t src_data,
|
|
|
|
/* dst addr in bytes */
|
|
|
|
uint64_t dst_offset,
|
|
|
|
/* number of byte to fill */
|
|
|
|
uint32_t byte_count);
|
|
|
|
};
|
|
|
|
|
|
|
|
/* provided by hw blocks that can write ptes, e.g., sdma */
|
|
|
|
struct amdgpu_vm_pte_funcs {
|
2017-09-19 23:58:15 +07:00
|
|
|
/* number of dw to reserve per operation */
|
|
|
|
unsigned copy_pte_num_dw;
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/* copy pte entries from GART */
|
|
|
|
void (*copy_pte)(struct amdgpu_ib *ib,
|
|
|
|
uint64_t pe, uint64_t src,
|
|
|
|
unsigned count);
|
2017-09-19 23:58:15 +07:00
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/* write pte one entry at a time with addr mapping */
|
2016-08-12 16:33:30 +07:00
|
|
|
void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
|
|
|
|
uint64_t value, unsigned count,
|
|
|
|
uint32_t incr);
|
2015-04-21 03:51:00 +07:00
|
|
|
/* for linear pte/pde updates without addr mapping */
|
|
|
|
void (*set_pte_pde)(struct amdgpu_ib *ib,
|
|
|
|
uint64_t pe,
|
|
|
|
uint64_t addr, unsigned count,
|
2016-09-21 15:19:19 +07:00
|
|
|
uint32_t incr, uint64_t flags);
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
/* provided by the ih block */
|
|
|
|
struct amdgpu_ih_funcs {
|
|
|
|
/* ring read/write ptr handling, called from interrupt context */
|
|
|
|
u32 (*get_wptr)(struct amdgpu_device *adev);
|
2017-08-26 13:40:45 +07:00
|
|
|
bool (*prescreen_iv)(struct amdgpu_device *adev);
|
2015-04-21 03:51:00 +07:00
|
|
|
void (*decode_iv)(struct amdgpu_device *adev,
|
|
|
|
struct amdgpu_iv_entry *entry);
|
|
|
|
void (*set_rptr)(struct amdgpu_device *adev);
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* BIOS.
|
|
|
|
*/
|
|
|
|
bool amdgpu_get_bios(struct amdgpu_device *adev);
|
|
|
|
bool amdgpu_read_bios(struct amdgpu_device *adev);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clocks
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define AMDGPU_MAX_PPLL 3
|
|
|
|
|
|
|
|
struct amdgpu_clock {
|
|
|
|
struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
|
|
|
|
struct amdgpu_pll spll;
|
|
|
|
struct amdgpu_pll mpll;
|
|
|
|
/* 10 Khz units */
|
|
|
|
uint32_t default_mclk;
|
|
|
|
uint32_t default_sclk;
|
|
|
|
uint32_t default_dispclk;
|
|
|
|
uint32_t current_dispclk;
|
|
|
|
uint32_t dp_extclk;
|
|
|
|
uint32_t max_pixel_clock;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
2017-07-21 05:16:21 +07:00
|
|
|
* GEM.
|
2015-04-21 03:51:00 +07:00
|
|
|
*/
|
|
|
|
|
2015-04-24 16:37:30 +07:00
|
|
|
#define AMDGPU_GEM_DOMAIN_MAX 0x3
|
2015-04-21 03:51:00 +07:00
|
|
|
#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
|
|
|
|
|
|
|
|
void amdgpu_gem_object_free(struct drm_gem_object *obj);
|
|
|
|
int amdgpu_gem_object_open(struct drm_gem_object *obj,
|
|
|
|
struct drm_file *file_priv);
|
|
|
|
void amdgpu_gem_object_close(struct drm_gem_object *obj,
|
|
|
|
struct drm_file *file_priv);
|
|
|
|
unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
|
|
|
|
struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
|
2016-05-03 23:46:19 +07:00
|
|
|
struct drm_gem_object *
|
|
|
|
amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
|
|
|
|
struct dma_buf_attachment *attach,
|
|
|
|
struct sg_table *sg);
|
2015-04-21 03:51:00 +07:00
|
|
|
struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
|
|
|
|
struct drm_gem_object *gobj,
|
|
|
|
int flags);
|
2017-12-09 04:18:59 +07:00
|
|
|
struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
|
|
|
|
struct dma_buf *dma_buf);
|
2015-04-21 03:51:00 +07:00
|
|
|
struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
|
|
|
|
void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
|
|
|
|
void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
|
2017-08-23 02:25:33 +07:00
|
|
|
int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
/* sub-allocation manager, it has to be protected by another lock.
|
|
|
|
* By conception this is an helper for other part of the driver
|
|
|
|
* like the indirect buffer or semaphore, which both have their
|
|
|
|
* locking.
|
|
|
|
*
|
|
|
|
* Principe is simple, we keep a list of sub allocation in offset
|
|
|
|
* order (first entry has offset == 0, last entry has the highest
|
|
|
|
* offset).
|
|
|
|
*
|
|
|
|
* When allocating new object we first check if there is room at
|
|
|
|
* the end total_size - (last_object_offset + last_object_size) >=
|
|
|
|
* alloc_size. If so we allocate new object there.
|
|
|
|
*
|
|
|
|
* When there is not enough room at the end, we start waiting for
|
|
|
|
* each sub object until we reach object_offset+object_size >=
|
|
|
|
* alloc_size, this object then become the sub object we return.
|
|
|
|
*
|
|
|
|
* Alignment can't be bigger than page size.
|
|
|
|
*
|
|
|
|
* Hole are not considered for allocation to keep things simple.
|
|
|
|
* Assumption is that there won't be hole (all object on same
|
|
|
|
* alignment).
|
|
|
|
*/
|
2016-03-11 20:50:08 +07:00
|
|
|
|
|
|
|
#define AMDGPU_SA_NUM_FENCE_LISTS 32
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_sa_manager {
|
|
|
|
wait_queue_head_t wq;
|
|
|
|
struct amdgpu_bo *bo;
|
|
|
|
struct list_head *hole;
|
2016-03-11 20:50:08 +07:00
|
|
|
struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
|
2015-04-21 03:51:00 +07:00
|
|
|
struct list_head olist;
|
|
|
|
unsigned size;
|
|
|
|
uint64_t gpu_addr;
|
|
|
|
void *cpu_ptr;
|
|
|
|
uint32_t domain;
|
|
|
|
uint32_t align;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* sub-allocation buffer */
|
|
|
|
struct amdgpu_sa_bo {
|
|
|
|
struct list_head olist;
|
|
|
|
struct list_head flist;
|
|
|
|
struct amdgpu_sa_manager *manager;
|
|
|
|
unsigned soffset;
|
|
|
|
unsigned eoffset;
|
2016-10-25 19:00:45 +07:00
|
|
|
struct dma_fence *fence;
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* GEM objects.
|
|
|
|
*/
|
2016-02-15 22:59:57 +07:00
|
|
|
void amdgpu_gem_force_release(struct amdgpu_device *adev);
|
2015-04-21 03:51:00 +07:00
|
|
|
int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
|
2017-08-25 14:14:43 +07:00
|
|
|
int alignment, u32 initial_domain,
|
2018-03-15 02:48:17 +07:00
|
|
|
u64 flags, enum ttm_bo_type type,
|
2017-08-25 14:14:43 +07:00
|
|
|
struct reservation_object *resv,
|
|
|
|
struct drm_gem_object **obj);
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
int amdgpu_mode_dumb_create(struct drm_file *file_priv,
|
|
|
|
struct drm_device *dev,
|
|
|
|
struct drm_mode_create_dumb *args);
|
|
|
|
int amdgpu_mode_dumb_mmap(struct drm_file *filp,
|
|
|
|
struct drm_device *dev,
|
|
|
|
uint32_t handle, uint64_t *offset_p);
|
2016-05-12 12:27:28 +07:00
|
|
|
int amdgpu_fence_slab_init(void);
|
|
|
|
void amdgpu_fence_slab_fini(void);
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* GPU doorbell structures, functions & helpers
|
|
|
|
*/
|
|
|
|
typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
|
|
|
|
{
|
|
|
|
AMDGPU_DOORBELL_KIQ = 0x000,
|
|
|
|
AMDGPU_DOORBELL_HIQ = 0x001,
|
|
|
|
AMDGPU_DOORBELL_DIQ = 0x002,
|
|
|
|
AMDGPU_DOORBELL_MEC_RING0 = 0x010,
|
|
|
|
AMDGPU_DOORBELL_MEC_RING1 = 0x011,
|
|
|
|
AMDGPU_DOORBELL_MEC_RING2 = 0x012,
|
|
|
|
AMDGPU_DOORBELL_MEC_RING3 = 0x013,
|
|
|
|
AMDGPU_DOORBELL_MEC_RING4 = 0x014,
|
|
|
|
AMDGPU_DOORBELL_MEC_RING5 = 0x015,
|
|
|
|
AMDGPU_DOORBELL_MEC_RING6 = 0x016,
|
|
|
|
AMDGPU_DOORBELL_MEC_RING7 = 0x017,
|
|
|
|
AMDGPU_DOORBELL_GFX_RING0 = 0x020,
|
|
|
|
AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
|
|
|
|
AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
|
|
|
|
AMDGPU_DOORBELL_IH = 0x1E8,
|
|
|
|
AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
|
|
|
|
AMDGPU_DOORBELL_INVALID = 0xFFFF
|
|
|
|
} AMDGPU_DOORBELL_ASSIGNMENT;
|
|
|
|
|
|
|
|
struct amdgpu_doorbell {
|
|
|
|
/* doorbell mmio */
|
|
|
|
resource_size_t base;
|
|
|
|
resource_size_t size;
|
|
|
|
u32 __iomem *ptr;
|
|
|
|
u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
|
|
|
|
};
|
|
|
|
|
2016-03-18 14:41:42 +07:00
|
|
|
/*
|
|
|
|
* 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
|
|
|
|
*/
|
|
|
|
typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
|
|
|
|
* a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
|
|
|
|
* Compute related doorbells are allocated from 0x00 to 0x8a
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
|
|
/* kernel scheduling */
|
|
|
|
AMDGPU_DOORBELL64_KIQ = 0x00,
|
|
|
|
|
|
|
|
/* HSA interface queue and debug queue */
|
|
|
|
AMDGPU_DOORBELL64_HIQ = 0x01,
|
|
|
|
AMDGPU_DOORBELL64_DIQ = 0x02,
|
|
|
|
|
|
|
|
/* Compute engines */
|
|
|
|
AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
|
|
|
|
AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
|
|
|
|
AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
|
|
|
|
AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
|
|
|
|
AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
|
|
|
|
AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
|
|
|
|
AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
|
|
|
|
AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
|
|
|
|
|
|
|
|
/* User queue doorbell range (128 doorbells) */
|
|
|
|
AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
|
|
|
|
AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
|
|
|
|
|
|
|
|
/* Graphics engine */
|
|
|
|
AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Other graphics doorbells can be allocated here: from 0x8c to 0xef
|
|
|
|
* Graphics voltage island aperture 1
|
|
|
|
* default non-graphics QWORD index is 0xF0 - 0xFF inclusive
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* sDMA engines */
|
|
|
|
AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
|
|
|
|
AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
|
|
|
|
AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
|
|
|
|
AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
|
|
|
|
|
|
|
|
/* Interrupt handler */
|
|
|
|
AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
|
|
|
|
AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
|
|
|
|
AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
|
|
|
|
|
2016-12-30 15:18:56 +07:00
|
|
|
/* VCN engine use 32 bits doorbell */
|
|
|
|
AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
|
|
|
|
AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
|
|
|
|
AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
|
|
|
|
AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
|
|
|
|
|
|
|
|
/* overlap the doorbell assignment with VCN as they are mutually exclusive
|
|
|
|
* VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
|
|
|
|
*/
|
2017-06-12 09:57:43 +07:00
|
|
|
AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
|
|
|
|
AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
|
|
|
|
AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
|
|
|
|
AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
|
|
|
|
|
|
|
|
AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
|
|
|
|
AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
|
|
|
|
AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
|
|
|
|
AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
|
2016-03-18 14:41:42 +07:00
|
|
|
|
|
|
|
AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
|
|
|
|
AMDGPU_DOORBELL64_INVALID = 0xFFFF
|
|
|
|
} AMDGPU_DOORBELL64_ASSIGNMENT;
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/*
|
|
|
|
* IRQS.
|
|
|
|
*/
|
|
|
|
|
|
|
|
struct amdgpu_flip_work {
|
2016-08-04 10:39:37 +07:00
|
|
|
struct delayed_work flip_work;
|
2015-04-21 03:51:00 +07:00
|
|
|
struct work_struct unpin_work;
|
|
|
|
struct amdgpu_device *adev;
|
|
|
|
int crtc_id;
|
2016-08-04 10:39:37 +07:00
|
|
|
u32 target_vblank;
|
2015-04-21 03:51:00 +07:00
|
|
|
uint64_t base;
|
|
|
|
struct drm_pending_vblank_event *event;
|
2016-09-15 20:06:50 +07:00
|
|
|
struct amdgpu_bo *old_abo;
|
2016-10-25 19:00:45 +07:00
|
|
|
struct dma_fence *excl;
|
2015-08-11 22:29:52 +07:00
|
|
|
unsigned shared_count;
|
2016-10-25 19:00:45 +07:00
|
|
|
struct dma_fence **shared;
|
|
|
|
struct dma_fence_cb cb;
|
2016-05-06 03:03:57 +07:00
|
|
|
bool async;
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* CP & rings.
|
|
|
|
*/
|
|
|
|
|
|
|
|
struct amdgpu_ib {
|
|
|
|
struct amdgpu_sa_bo *sa_bo;
|
|
|
|
uint32_t length_dw;
|
|
|
|
uint64_t gpu_addr;
|
|
|
|
uint32_t *ptr;
|
2015-05-11 22:41:41 +07:00
|
|
|
uint32_t flags;
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
2017-12-06 23:49:39 +07:00
|
|
|
extern const struct drm_sched_backend_ops amdgpu_sched_ops;
|
2015-07-21 12:45:14 +07:00
|
|
|
|
2016-02-03 19:44:52 +07:00
|
|
|
int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
|
2016-04-19 19:11:32 +07:00
|
|
|
struct amdgpu_job **job, struct amdgpu_vm *vm);
|
2016-02-01 18:20:25 +07:00
|
|
|
int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
|
|
|
|
struct amdgpu_job **job);
|
2016-03-10 11:14:44 +07:00
|
|
|
|
2016-06-29 20:10:31 +07:00
|
|
|
void amdgpu_job_free_resources(struct amdgpu_job *job);
|
2016-02-03 19:44:52 +07:00
|
|
|
void amdgpu_job_free(struct amdgpu_job *job);
|
2016-02-01 18:20:25 +07:00
|
|
|
int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
|
2017-12-06 23:49:39 +07:00
|
|
|
struct drm_sched_entity *entity, void *owner,
|
2016-10-25 19:00:45 +07:00
|
|
|
struct dma_fence **f);
|
2015-11-15 22:04:16 +07:00
|
|
|
|
2017-02-16 12:47:32 +07:00
|
|
|
/*
|
|
|
|
* Queue manager
|
|
|
|
*/
|
|
|
|
struct amdgpu_queue_mapper {
|
|
|
|
int hw_ip;
|
|
|
|
struct mutex lock;
|
|
|
|
/* protected by lock */
|
|
|
|
struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];
|
|
|
|
};
|
|
|
|
|
|
|
|
struct amdgpu_queue_mgr {
|
|
|
|
struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];
|
|
|
|
};
|
|
|
|
|
|
|
|
int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
|
|
|
|
struct amdgpu_queue_mgr *mgr);
|
|
|
|
int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
|
|
|
|
struct amdgpu_queue_mgr *mgr);
|
|
|
|
int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
|
|
|
|
struct amdgpu_queue_mgr *mgr,
|
2017-11-22 21:55:21 +07:00
|
|
|
u32 hw_ip, u32 instance, u32 ring,
|
2017-02-16 12:47:32 +07:00
|
|
|
struct amdgpu_ring **out_ring);
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/*
|
|
|
|
* context related structures
|
|
|
|
*/
|
|
|
|
|
2015-07-07 22:24:49 +07:00
|
|
|
struct amdgpu_ctx_ring {
|
2015-08-05 23:33:21 +07:00
|
|
|
uint64_t sequence;
|
2016-10-25 19:00:45 +07:00
|
|
|
struct dma_fence **fences;
|
2017-12-06 23:49:39 +07:00
|
|
|
struct drm_sched_entity entity;
|
2015-07-07 22:24:49 +07:00
|
|
|
};
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_ctx {
|
2015-08-17 09:48:26 +07:00
|
|
|
struct kref refcount;
|
2015-07-21 12:17:19 +07:00
|
|
|
struct amdgpu_device *adev;
|
2017-02-16 12:47:32 +07:00
|
|
|
struct amdgpu_queue_mgr queue_mgr;
|
2015-08-17 09:48:26 +07:00
|
|
|
unsigned reset_counter;
|
2017-10-17 13:39:23 +07:00
|
|
|
unsigned reset_counter_query;
|
2017-10-09 20:18:43 +07:00
|
|
|
uint32_t vram_lost_counter;
|
2015-07-07 22:24:49 +07:00
|
|
|
spinlock_t ring_lock;
|
2016-10-25 19:00:45 +07:00
|
|
|
struct dma_fence **fences;
|
2015-07-07 22:24:49 +07:00
|
|
|
struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
|
2017-10-09 20:18:43 +07:00
|
|
|
bool preamble_presented;
|
2017-12-06 23:49:39 +07:00
|
|
|
enum drm_sched_priority init_priority;
|
|
|
|
enum drm_sched_priority override_priority;
|
2017-10-11 03:50:17 +07:00
|
|
|
struct mutex lock;
|
2017-10-23 11:25:24 +07:00
|
|
|
atomic_t guilty;
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
struct amdgpu_ctx_mgr {
|
2015-08-17 09:48:26 +07:00
|
|
|
struct amdgpu_device *adev;
|
|
|
|
struct mutex lock;
|
|
|
|
/* protected by lock */
|
|
|
|
struct idr ctx_handles;
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
2015-08-17 09:48:26 +07:00
|
|
|
struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
|
|
|
|
int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
|
|
|
|
|
2017-09-15 12:40:31 +07:00
|
|
|
int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
|
|
|
|
struct dma_fence *fence, uint64_t *seq);
|
2016-10-25 19:00:45 +07:00
|
|
|
struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
|
2015-07-07 22:24:49 +07:00
|
|
|
struct amdgpu_ring *ring, uint64_t seq);
|
2017-06-07 07:20:38 +07:00
|
|
|
void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
|
2017-12-06 23:49:39 +07:00
|
|
|
enum drm_sched_priority priority);
|
2015-07-07 22:24:49 +07:00
|
|
|
|
2015-08-17 09:48:26 +07:00
|
|
|
int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp);
|
|
|
|
|
2017-10-11 03:50:17 +07:00
|
|
|
int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
|
|
|
|
|
2015-08-04 21:20:31 +07:00
|
|
|
void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
|
|
|
|
void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
|
2015-08-17 09:48:26 +07:00
|
|
|
|
2017-10-11 03:50:17 +07:00
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/*
|
|
|
|
* file private structure
|
|
|
|
*/
|
|
|
|
|
|
|
|
struct amdgpu_fpriv {
|
|
|
|
struct amdgpu_vm vm;
|
2017-01-16 12:59:01 +07:00
|
|
|
struct amdgpu_bo_va *prt_va;
|
2017-07-31 20:32:40 +07:00
|
|
|
struct amdgpu_bo_va *csa_va;
|
2015-04-21 03:51:00 +07:00
|
|
|
struct mutex bo_list_lock;
|
|
|
|
struct idr bo_list_handles;
|
2015-08-17 09:48:26 +07:00
|
|
|
struct amdgpu_ctx_mgr ctx_mgr;
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* residency list
|
|
|
|
*/
|
2017-07-21 05:16:21 +07:00
|
|
|
struct amdgpu_bo_list_entry {
|
|
|
|
struct amdgpu_bo *robj;
|
|
|
|
struct ttm_validate_buffer tv;
|
|
|
|
struct amdgpu_bo_va *bo_va;
|
|
|
|
uint32_t priority;
|
|
|
|
struct page **user_pages;
|
|
|
|
int user_invalidated;
|
|
|
|
};
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
struct amdgpu_bo_list {
|
|
|
|
struct mutex lock;
|
2017-06-16 20:07:29 +07:00
|
|
|
struct rcu_head rhead;
|
|
|
|
struct kref refcount;
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_bo *gds_obj;
|
|
|
|
struct amdgpu_bo *gws_obj;
|
|
|
|
struct amdgpu_bo *oa_obj;
|
2016-02-22 21:40:59 +07:00
|
|
|
unsigned first_userptr;
|
2015-04-21 03:51:00 +07:00
|
|
|
unsigned num_entries;
|
|
|
|
struct amdgpu_bo_list_entry *array;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct amdgpu_bo_list *
|
|
|
|
amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
|
2015-12-19 03:26:47 +07:00
|
|
|
void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
|
|
|
|
struct list_head *validated);
|
2015-04-21 03:51:00 +07:00
|
|
|
void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
|
|
|
|
void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* GFX stuff
|
|
|
|
*/
|
|
|
|
#include "clearstate_defs.h"
|
|
|
|
|
2016-04-09 02:45:13 +07:00
|
|
|
struct amdgpu_rlc_funcs {
|
|
|
|
void (*enter_safe_mode)(struct amdgpu_device *adev);
|
|
|
|
void (*exit_safe_mode)(struct amdgpu_device *adev);
|
|
|
|
};
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_rlc {
|
|
|
|
/* for power gating */
|
|
|
|
struct amdgpu_bo *save_restore_obj;
|
|
|
|
uint64_t save_restore_gpu_addr;
|
|
|
|
volatile uint32_t *sr_ptr;
|
|
|
|
const u32 *reg_list;
|
|
|
|
u32 reg_list_size;
|
|
|
|
/* for clear state */
|
|
|
|
struct amdgpu_bo *clear_state_obj;
|
|
|
|
uint64_t clear_state_gpu_addr;
|
|
|
|
volatile uint32_t *cs_ptr;
|
|
|
|
const struct cs_section_def *cs_data;
|
|
|
|
u32 clear_state_size;
|
|
|
|
/* for cp tables */
|
|
|
|
struct amdgpu_bo *cp_table_obj;
|
|
|
|
uint64_t cp_table_gpu_addr;
|
|
|
|
volatile uint32_t *cp_table_ptr;
|
|
|
|
u32 cp_table_size;
|
2016-04-09 02:45:13 +07:00
|
|
|
|
|
|
|
/* safe mode for updating CG/PG state */
|
|
|
|
bool in_safe_mode;
|
|
|
|
const struct amdgpu_rlc_funcs *funcs;
|
2016-04-15 04:26:07 +07:00
|
|
|
|
|
|
|
/* for firmware data */
|
|
|
|
u32 save_and_restore_offset;
|
|
|
|
u32 clear_state_descriptor_offset;
|
|
|
|
u32 avail_scratch_ram_locations;
|
|
|
|
u32 reg_restore_list_size;
|
|
|
|
u32 reg_list_format_start;
|
|
|
|
u32 reg_list_format_separate_start;
|
|
|
|
u32 starting_offsets_start;
|
|
|
|
u32 reg_list_format_size_bytes;
|
|
|
|
u32 reg_list_size_bytes;
|
|
|
|
|
|
|
|
u32 *register_list_format;
|
|
|
|
u32 *register_restore;
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
2017-02-02 12:38:22 +07:00
|
|
|
#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_mec {
|
|
|
|
struct amdgpu_bo *hpd_eop_obj;
|
|
|
|
u64 hpd_eop_gpu_addr;
|
2017-03-04 05:59:39 +07:00
|
|
|
struct amdgpu_bo *mec_fw_obj;
|
|
|
|
u64 mec_fw_gpu_addr;
|
2015-04-21 03:51:00 +07:00
|
|
|
u32 num_mec;
|
2017-02-02 07:08:23 +07:00
|
|
|
u32 num_pipe_per_mec;
|
|
|
|
u32 num_queue_per_pipe;
|
2017-02-17 15:03:10 +07:00
|
|
|
void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
|
2017-02-02 12:38:22 +07:00
|
|
|
|
|
|
|
/* These are the resources for which amdgpu takes ownership */
|
|
|
|
DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
2016-12-23 14:00:01 +07:00
|
|
|
struct amdgpu_kiq {
|
|
|
|
u64 eop_gpu_addr;
|
|
|
|
struct amdgpu_bo *eop_obj;
|
2017-10-13 14:38:35 +07:00
|
|
|
spinlock_t ring_lock;
|
2016-12-23 14:00:01 +07:00
|
|
|
struct amdgpu_ring ring;
|
|
|
|
struct amdgpu_irq_src irq;
|
|
|
|
};
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/*
|
|
|
|
* GPU scratch registers structures, functions & helpers
|
|
|
|
*/
|
|
|
|
struct amdgpu_scratch {
|
|
|
|
unsigned num_reg;
|
|
|
|
uint32_t reg_base;
|
2017-01-17 03:56:48 +07:00
|
|
|
uint32_t free_mask;
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* GFX configurations
|
|
|
|
*/
|
2016-10-10 21:56:21 +07:00
|
|
|
#define AMDGPU_GFX_MAX_SE 4
|
|
|
|
#define AMDGPU_GFX_MAX_SH_PER_SE 2
|
|
|
|
|
|
|
|
struct amdgpu_rb_config {
|
|
|
|
uint32_t rb_backend_disable;
|
|
|
|
uint32_t user_rb_backend_disable;
|
|
|
|
uint32_t raster_config;
|
|
|
|
uint32_t raster_config_1;
|
|
|
|
};
|
|
|
|
|
2016-12-13 01:40:37 +07:00
|
|
|
struct gb_addr_config {
|
|
|
|
uint16_t pipe_interleave_size;
|
|
|
|
uint8_t num_pipes;
|
|
|
|
uint8_t max_compress_frags;
|
|
|
|
uint8_t num_banks;
|
|
|
|
uint8_t num_se;
|
|
|
|
uint8_t num_rb_per_se;
|
|
|
|
};
|
|
|
|
|
2017-02-21 09:32:37 +07:00
|
|
|
struct amdgpu_gfx_config {
|
2015-04-21 03:51:00 +07:00
|
|
|
unsigned max_shader_engines;
|
|
|
|
unsigned max_tile_pipes;
|
|
|
|
unsigned max_cu_per_sh;
|
|
|
|
unsigned max_sh_per_se;
|
|
|
|
unsigned max_backends_per_se;
|
|
|
|
unsigned max_texture_channel_caches;
|
|
|
|
unsigned max_gprs;
|
|
|
|
unsigned max_gs_threads;
|
|
|
|
unsigned max_hw_contexts;
|
|
|
|
unsigned sc_prim_fifo_size_frontend;
|
|
|
|
unsigned sc_prim_fifo_size_backend;
|
|
|
|
unsigned sc_hiz_tile_fifo_size;
|
|
|
|
unsigned sc_earlyz_tile_fifo_size;
|
|
|
|
|
|
|
|
unsigned num_tile_pipes;
|
|
|
|
unsigned backend_enable_mask;
|
|
|
|
unsigned mem_max_burst_length_bytes;
|
|
|
|
unsigned mem_row_size_in_kb;
|
|
|
|
unsigned shader_engine_tile_size;
|
|
|
|
unsigned num_gpus;
|
|
|
|
unsigned multi_gpu_tile_size;
|
|
|
|
unsigned mc_arb_ramcfg;
|
|
|
|
unsigned gb_addr_config;
|
2016-02-12 12:39:13 +07:00
|
|
|
unsigned num_rbs;
|
2017-04-27 10:12:07 +07:00
|
|
|
unsigned gs_vgt_table_depth;
|
|
|
|
unsigned gs_prim_buffer_depth;
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
uint32_t tile_mode_array[32];
|
|
|
|
uint32_t macrotile_mode_array[16];
|
2016-10-10 21:56:21 +07:00
|
|
|
|
2016-12-13 01:40:37 +07:00
|
|
|
struct gb_addr_config gb_addr_config_fields;
|
2016-10-10 21:56:21 +07:00
|
|
|
struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
|
2017-02-17 10:05:49 +07:00
|
|
|
|
|
|
|
/* gfx configure feature */
|
|
|
|
uint32_t double_offchip_lds_buf;
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
2016-05-04 03:25:53 +07:00
|
|
|
struct amdgpu_cu_info {
|
2017-12-09 11:08:40 +07:00
|
|
|
uint32_t simd_per_cu;
|
2017-06-09 21:30:52 +07:00
|
|
|
uint32_t max_waves_per_simd;
|
2017-04-27 10:12:07 +07:00
|
|
|
uint32_t wave_front_size;
|
2017-06-09 21:30:52 +07:00
|
|
|
uint32_t max_scratch_slots_per_cu;
|
|
|
|
uint32_t lds_size;
|
2017-06-20 10:08:35 +07:00
|
|
|
|
|
|
|
/* total active CU number */
|
|
|
|
uint32_t number;
|
|
|
|
uint32_t ao_cu_mask;
|
|
|
|
uint32_t ao_cu_bitmap[4][4];
|
2016-05-04 03:25:53 +07:00
|
|
|
uint32_t bitmap[4][4];
|
|
|
|
};
|
|
|
|
|
2016-07-08 02:01:42 +07:00
|
|
|
struct amdgpu_gfx_funcs {
|
|
|
|
/* get the gpu clock counter */
|
|
|
|
uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
|
2016-06-28 21:26:48 +07:00
|
|
|
void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
|
2016-10-14 20:49:09 +07:00
|
|
|
void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
|
2016-12-05 23:39:19 +07:00
|
|
|
void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
|
|
|
|
void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
|
2016-07-08 02:01:42 +07:00
|
|
|
};
|
|
|
|
|
2017-03-28 23:52:08 +07:00
|
|
|
struct amdgpu_ngg_buf {
|
|
|
|
struct amdgpu_bo *bo;
|
|
|
|
uint64_t gpu_addr;
|
|
|
|
uint32_t size;
|
|
|
|
uint32_t bo_size;
|
|
|
|
};
|
|
|
|
|
|
|
|
enum {
|
2017-05-04 13:49:18 +07:00
|
|
|
NGG_PRIM = 0,
|
|
|
|
NGG_POS,
|
|
|
|
NGG_CNTL,
|
|
|
|
NGG_PARAM,
|
2017-03-28 23:52:08 +07:00
|
|
|
NGG_BUF_MAX
|
|
|
|
};
|
|
|
|
|
|
|
|
struct amdgpu_ngg {
|
|
|
|
struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
|
|
|
|
uint32_t gds_reserve_addr;
|
|
|
|
uint32_t gds_reserve_size;
|
|
|
|
bool init;
|
|
|
|
};
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_gfx {
|
|
|
|
struct mutex gpu_clock_mutex;
|
2017-02-21 09:32:37 +07:00
|
|
|
struct amdgpu_gfx_config config;
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_rlc rlc;
|
|
|
|
struct amdgpu_mec mec;
|
2016-12-23 14:00:01 +07:00
|
|
|
struct amdgpu_kiq kiq;
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_scratch scratch;
|
|
|
|
const struct firmware *me_fw; /* ME firmware */
|
|
|
|
uint32_t me_fw_version;
|
|
|
|
const struct firmware *pfp_fw; /* PFP firmware */
|
|
|
|
uint32_t pfp_fw_version;
|
|
|
|
const struct firmware *ce_fw; /* CE firmware */
|
|
|
|
uint32_t ce_fw_version;
|
|
|
|
const struct firmware *rlc_fw; /* RLC firmware */
|
|
|
|
uint32_t rlc_fw_version;
|
|
|
|
const struct firmware *mec_fw; /* MEC firmware */
|
|
|
|
uint32_t mec_fw_version;
|
|
|
|
const struct firmware *mec2_fw; /* MEC2 firmware */
|
|
|
|
uint32_t mec2_fw_version;
|
2015-06-03 18:52:06 +07:00
|
|
|
uint32_t me_feature_version;
|
|
|
|
uint32_t ce_feature_version;
|
|
|
|
uint32_t pfp_feature_version;
|
2015-08-04 09:43:50 +07:00
|
|
|
uint32_t rlc_feature_version;
|
|
|
|
uint32_t mec_feature_version;
|
|
|
|
uint32_t mec2_feature_version;
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
|
|
|
|
unsigned num_gfx_rings;
|
|
|
|
struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
|
|
|
|
unsigned num_compute_rings;
|
|
|
|
struct amdgpu_irq_src eop_irq;
|
|
|
|
struct amdgpu_irq_src priv_reg_irq;
|
|
|
|
struct amdgpu_irq_src priv_inst_irq;
|
|
|
|
/* gfx status */
|
2016-05-04 03:25:53 +07:00
|
|
|
uint32_t gfx_current_status;
|
2015-06-03 16:47:54 +07:00
|
|
|
/* ce ram size*/
|
2016-05-04 03:25:53 +07:00
|
|
|
unsigned ce_ram_size;
|
|
|
|
struct amdgpu_cu_info cu_info;
|
2016-07-08 02:01:42 +07:00
|
|
|
const struct amdgpu_gfx_funcs *funcs;
|
2016-07-15 10:28:30 +07:00
|
|
|
|
|
|
|
/* reset mask */
|
|
|
|
uint32_t grbm_soft_reset;
|
|
|
|
uint32_t srbm_soft_reset;
|
2017-03-28 23:57:31 +07:00
|
|
|
/* s3/s4 mask */
|
|
|
|
bool in_suspend;
|
2017-03-28 23:52:08 +07:00
|
|
|
/* NGG */
|
|
|
|
struct amdgpu_ngg ngg;
|
2017-04-29 07:05:51 +07:00
|
|
|
|
|
|
|
/* pipe reservation */
|
|
|
|
struct mutex pipe_reserve_mutex;
|
|
|
|
DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
2016-01-31 18:29:04 +07:00
|
|
|
int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
|
2015-04-21 03:51:00 +07:00
|
|
|
unsigned size, struct amdgpu_ib *ib);
|
2016-05-03 23:46:19 +07:00
|
|
|
void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
|
2016-10-25 19:00:45 +07:00
|
|
|
struct dma_fence *f);
|
2016-01-31 18:29:04 +07:00
|
|
|
int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
|
2017-01-23 15:30:38 +07:00
|
|
|
struct amdgpu_ib *ibs, struct amdgpu_job *job,
|
|
|
|
struct dma_fence **f);
|
2015-04-21 03:51:00 +07:00
|
|
|
int amdgpu_ib_pool_init(struct amdgpu_device *adev);
|
|
|
|
void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
|
|
|
|
int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* CS.
|
|
|
|
*/
|
|
|
|
struct amdgpu_cs_chunk {
|
|
|
|
uint32_t chunk_id;
|
|
|
|
uint32_t length_dw;
|
2016-05-07 03:14:00 +07:00
|
|
|
void *kdata;
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
struct amdgpu_cs_parser {
|
|
|
|
struct amdgpu_device *adev;
|
|
|
|
struct drm_file *filp;
|
2015-05-11 20:34:59 +07:00
|
|
|
struct amdgpu_ctx *ctx;
|
2015-12-15 20:41:33 +07:00
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/* chunks */
|
|
|
|
unsigned nchunks;
|
|
|
|
struct amdgpu_cs_chunk *chunks;
|
|
|
|
|
2016-02-03 19:44:52 +07:00
|
|
|
/* scheduler job object */
|
|
|
|
struct amdgpu_job *job;
|
2015-04-21 03:51:00 +07:00
|
|
|
|
2015-12-15 20:41:33 +07:00
|
|
|
/* buffer objects */
|
|
|
|
struct ww_acquire_ctx ticket;
|
|
|
|
struct amdgpu_bo_list *bo_list;
|
2017-09-13 01:25:14 +07:00
|
|
|
struct amdgpu_mn *mn;
|
2015-12-15 20:41:33 +07:00
|
|
|
struct amdgpu_bo_list_entry vm_pd;
|
|
|
|
struct list_head validated;
|
2016-10-25 19:00:45 +07:00
|
|
|
struct dma_fence *fence;
|
2015-12-15 20:41:33 +07:00
|
|
|
uint64_t bytes_moved_threshold;
|
2017-06-28 09:33:18 +07:00
|
|
|
uint64_t bytes_moved_vis_threshold;
|
2015-12-15 20:41:33 +07:00
|
|
|
uint64_t bytes_moved;
|
2017-06-28 09:33:18 +07:00
|
|
|
uint64_t bytes_moved_vis;
|
2016-09-01 17:13:18 +07:00
|
|
|
struct amdgpu_bo_list_entry *evictable;
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
/* user fence */
|
2015-12-14 22:42:31 +07:00
|
|
|
struct amdgpu_bo_list_entry uf_entry;
|
2017-03-14 05:18:15 +07:00
|
|
|
|
|
|
|
unsigned num_post_dep_syncobjs;
|
|
|
|
struct drm_syncobj **post_dep_syncobjs;
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
2016-08-26 12:28:28 +07:00
|
|
|
#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
|
|
|
|
#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
|
|
|
|
#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
|
|
|
|
|
2015-08-18 14:16:40 +07:00
|
|
|
struct amdgpu_job {
|
2017-12-06 23:49:39 +07:00
|
|
|
struct drm_sched_job base;
|
2015-08-18 14:16:40 +07:00
|
|
|
struct amdgpu_device *adev;
|
2016-05-03 20:54:54 +07:00
|
|
|
struct amdgpu_vm *vm;
|
2016-01-31 18:29:04 +07:00
|
|
|
struct amdgpu_ring *ring;
|
2016-02-08 18:13:05 +07:00
|
|
|
struct amdgpu_sync sync;
|
2017-05-09 14:50:22 +07:00
|
|
|
struct amdgpu_sync sched_sync;
|
2015-08-18 14:16:40 +07:00
|
|
|
struct amdgpu_ib *ibs;
|
2016-10-25 19:00:45 +07:00
|
|
|
struct dma_fence *fence; /* the hw fence */
|
2016-08-26 12:28:28 +07:00
|
|
|
uint32_t preamble_status;
|
2015-08-18 14:16:40 +07:00
|
|
|
uint32_t num_ibs;
|
2015-11-06 01:49:48 +07:00
|
|
|
void *owner;
|
2016-08-25 14:40:48 +07:00
|
|
|
uint64_t fence_ctx; /* the fence_context this job uses */
|
2016-07-01 16:59:01 +07:00
|
|
|
bool vm_needs_flush;
|
2016-05-06 22:50:03 +07:00
|
|
|
uint64_t vm_pd_addr;
|
2018-01-08 20:48:11 +07:00
|
|
|
unsigned vmid;
|
|
|
|
unsigned pasid;
|
2016-05-06 22:50:03 +07:00
|
|
|
uint32_t gds_base, gds_size;
|
|
|
|
uint32_t gws_base, gws_size;
|
|
|
|
uint32_t oa_base, oa_size;
|
2017-10-09 20:04:41 +07:00
|
|
|
uint32_t vram_lost_counter;
|
2016-05-07 03:14:00 +07:00
|
|
|
|
|
|
|
/* user fence handling */
|
2016-06-29 18:26:41 +07:00
|
|
|
uint64_t uf_addr;
|
2016-05-07 03:14:00 +07:00
|
|
|
uint64_t uf_sequence;
|
|
|
|
|
2015-08-18 14:16:40 +07:00
|
|
|
};
|
2015-09-09 08:21:19 +07:00
|
|
|
#define to_amdgpu_job(sched_job) \
|
|
|
|
container_of((sched_job), struct amdgpu_job, base)
|
2015-08-18 14:16:40 +07:00
|
|
|
|
2016-01-31 17:00:41 +07:00
|
|
|
static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
|
|
|
|
uint32_t ib_idx, int idx)
|
2015-04-21 03:51:00 +07:00
|
|
|
{
|
2016-02-03 19:44:52 +07:00
|
|
|
return p->job->ibs[ib_idx].ptr[idx];
|
2015-04-21 03:51:00 +07:00
|
|
|
}
|
|
|
|
|
2016-01-31 17:00:41 +07:00
|
|
|
static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
|
|
|
|
uint32_t ib_idx, int idx,
|
|
|
|
uint32_t value)
|
|
|
|
{
|
2016-02-03 19:44:52 +07:00
|
|
|
p->job->ibs[ib_idx].ptr[idx] = value;
|
2016-01-31 17:00:41 +07:00
|
|
|
}
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/*
|
|
|
|
* Writeback
|
|
|
|
*/
|
2017-12-29 16:06:41 +07:00
|
|
|
#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
struct amdgpu_wb {
|
|
|
|
struct amdgpu_bo *wb_obj;
|
|
|
|
volatile uint32_t *wb;
|
|
|
|
uint64_t gpu_addr;
|
|
|
|
u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
|
|
|
|
unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
|
|
|
|
};
|
|
|
|
|
2017-12-15 04:03:43 +07:00
|
|
|
int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
|
|
|
|
void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* SDMA
|
|
|
|
*/
|
2015-10-09 03:30:37 +07:00
|
|
|
struct amdgpu_sdma_instance {
|
2015-04-21 03:51:00 +07:00
|
|
|
/* SDMA firmware */
|
|
|
|
const struct firmware *fw;
|
|
|
|
uint32_t fw_version;
|
2015-08-04 09:50:47 +07:00
|
|
|
uint32_t feature_version;
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
struct amdgpu_ring ring;
|
2015-08-31 13:06:39 +07:00
|
|
|
bool burst_nop;
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
2015-10-09 03:30:37 +07:00
|
|
|
struct amdgpu_sdma {
|
|
|
|
struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
|
2016-01-19 13:05:23 +07:00
|
|
|
#ifdef CONFIG_DRM_AMDGPU_SI
|
|
|
|
//SI DMA has a difference trap irq number for the second engine
|
|
|
|
struct amdgpu_irq_src trap_irq_1;
|
|
|
|
#endif
|
2015-10-09 03:30:37 +07:00
|
|
|
struct amdgpu_irq_src trap_irq;
|
|
|
|
struct amdgpu_irq_src illegal_inst_irq;
|
2016-05-03 20:54:54 +07:00
|
|
|
int num_instances;
|
2016-07-13 09:28:56 +07:00
|
|
|
uint32_t srbm_soft_reset;
|
2015-10-09 03:30:37 +07:00
|
|
|
};
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/*
|
|
|
|
* Firmware
|
|
|
|
*/
|
2016-11-01 14:35:38 +07:00
|
|
|
enum amdgpu_firmware_load_type {
|
|
|
|
AMDGPU_FW_LOAD_DIRECT = 0,
|
|
|
|
AMDGPU_FW_LOAD_SMU,
|
|
|
|
AMDGPU_FW_LOAD_PSP,
|
|
|
|
};
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_firmware {
|
|
|
|
struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
|
2016-11-01 14:35:38 +07:00
|
|
|
enum amdgpu_firmware_load_type load_type;
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_bo *fw_buf;
|
|
|
|
unsigned int fw_size;
|
2017-03-04 04:20:35 +07:00
|
|
|
unsigned int max_ucodes;
|
2017-03-04 06:37:23 +07:00
|
|
|
/* firmwares are loaded by psp instead of smu from vega10 */
|
|
|
|
const struct amdgpu_psp_funcs *funcs;
|
|
|
|
struct amdgpu_bo *rbuf;
|
|
|
|
struct mutex mutex;
|
2017-06-05 21:11:59 +07:00
|
|
|
|
|
|
|
/* gpu info firmware data pointer */
|
|
|
|
const struct firmware *gpu_info_fw;
|
2017-09-15 13:35:09 +07:00
|
|
|
|
|
|
|
void *fw_buf_ptr;
|
|
|
|
uint64_t fw_buf_mc;
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Benchmarking
|
|
|
|
*/
|
|
|
|
void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Testing
|
|
|
|
*/
|
|
|
|
void amdgpu_test_moves(struct amdgpu_device *adev);
|
|
|
|
|
drm/amdgpu: introduce a firmware debugfs to dump all current firmware versions
This patch implements the debugfs to dump all currect firmware
version:
root@jenkins-All-Series:/home/jenkins# cat /sys/kernel/debug/dri/0/amdgpu_firmware_info
VCE feature version: 0, firmware version: 0x34040300
UVD feature version: 0, firmware version: 0x01451000
MC feature version: 0, firmware version: 0x00000000
ME feature version: 37, firmware version: 0x00000093
PFP feature version: 37, firmware version: 0x000000da
CE feature version: 37, firmware version: 0x00000080
RLC feature version: 1, firmware version: 0x0000010e
MEC feature version: 37, firmware version: 0x0000029e
MEC2 feature version: 37, firmware version: 0x0000029e
SMC feature version: 0, firmware version: 0x013353e6
SDMA0 feature version: 31, firmware version: 0x00000036
SDMA1 feature version: 0, firmware version: 0x00000036
Suggested-by: Alex Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-06-12 14:51:09 +07:00
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/*
|
|
|
|
* amdgpu smumgr functions
|
|
|
|
*/
|
|
|
|
struct amdgpu_smumgr_funcs {
|
|
|
|
int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
|
|
|
|
int (*request_smu_load_fw)(struct amdgpu_device *adev);
|
|
|
|
int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* amdgpu smumgr
|
|
|
|
*/
|
|
|
|
struct amdgpu_smumgr {
|
|
|
|
struct amdgpu_bo *toc_buf;
|
|
|
|
struct amdgpu_bo *smu_buf;
|
|
|
|
/* asic priv smu data */
|
|
|
|
void *priv;
|
|
|
|
spinlock_t smu_lock;
|
|
|
|
/* smumgr functions */
|
|
|
|
const struct amdgpu_smumgr_funcs *smumgr_funcs;
|
|
|
|
/* ucode loading complete flag */
|
|
|
|
uint32_t fw_flags;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ASIC specific register table accessible by UMD
|
|
|
|
*/
|
|
|
|
struct amdgpu_allowed_register_entry {
|
|
|
|
uint32_t reg_offset;
|
|
|
|
bool grbm_indexed;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ASIC specific functions.
|
|
|
|
*/
|
|
|
|
struct amdgpu_asic_funcs {
|
|
|
|
bool (*read_disabled_bios)(struct amdgpu_device *adev);
|
2015-11-24 22:14:28 +07:00
|
|
|
bool (*read_bios_from_rom)(struct amdgpu_device *adev,
|
|
|
|
u8 *bios, u32 length_bytes);
|
2015-04-21 03:51:00 +07:00
|
|
|
int (*read_register)(struct amdgpu_device *adev, u32 se_num,
|
|
|
|
u32 sh_num, u32 reg_offset, u32 *value);
|
|
|
|
void (*set_vga_state)(struct amdgpu_device *adev, bool state);
|
|
|
|
int (*reset)(struct amdgpu_device *adev);
|
|
|
|
/* get the reference clock */
|
|
|
|
u32 (*get_xclk)(struct amdgpu_device *adev);
|
|
|
|
/* MM block clocks */
|
|
|
|
int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
|
|
|
|
int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
|
2016-08-01 23:42:32 +07:00
|
|
|
/* static power management */
|
|
|
|
int (*get_pcie_lanes)(struct amdgpu_device *adev);
|
|
|
|
void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
|
2017-03-04 05:26:10 +07:00
|
|
|
/* get config memsize register */
|
|
|
|
u32 (*get_config_memsize)(struct amdgpu_device *adev);
|
2017-09-07 05:04:51 +07:00
|
|
|
/* flush hdp write queue */
|
2018-01-19 20:17:40 +07:00
|
|
|
void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
|
2017-09-07 05:04:51 +07:00
|
|
|
/* invalidate hdp read cache */
|
2018-01-19 20:17:40 +07:00
|
|
|
void (*invalidate_hdp)(struct amdgpu_device *adev,
|
|
|
|
struct amdgpu_ring *ring);
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* IOCTL.
|
|
|
|
*/
|
|
|
|
int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp);
|
|
|
|
int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp);
|
|
|
|
|
|
|
|
int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp);
|
|
|
|
int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp);
|
|
|
|
int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp);
|
|
|
|
int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp);
|
|
|
|
int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp);
|
|
|
|
int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp);
|
|
|
|
int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
|
2017-09-13 03:42:14 +07:00
|
|
|
int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp);
|
2015-04-21 03:51:00 +07:00
|
|
|
int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
|
2016-11-05 03:16:10 +07:00
|
|
|
int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp);
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp);
|
|
|
|
|
|
|
|
/* VRAM scratch page for HDP bug, default vram page */
|
|
|
|
struct amdgpu_vram_scratch {
|
|
|
|
struct amdgpu_bo *robj;
|
|
|
|
volatile uint32_t *ptr;
|
|
|
|
u64 gpu_addr;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ACPI
|
|
|
|
*/
|
|
|
|
struct amdgpu_atif_notification_cfg {
|
|
|
|
bool enabled;
|
|
|
|
int command_code;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct amdgpu_atif_notifications {
|
|
|
|
bool display_switch;
|
|
|
|
bool expansion_mode_change;
|
|
|
|
bool thermal_state;
|
|
|
|
bool forced_power_state;
|
|
|
|
bool system_power_state;
|
|
|
|
bool display_conf_change;
|
|
|
|
bool px_gfx_switch;
|
|
|
|
bool brightness_change;
|
|
|
|
bool dgpu_display_event;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct amdgpu_atif_functions {
|
|
|
|
bool system_params;
|
|
|
|
bool sbios_requests;
|
|
|
|
bool select_active_disp;
|
|
|
|
bool lid_state;
|
|
|
|
bool get_tv_standard;
|
|
|
|
bool set_tv_standard;
|
|
|
|
bool get_panel_expansion_mode;
|
|
|
|
bool set_panel_expansion_mode;
|
|
|
|
bool temperature_change;
|
|
|
|
bool graphics_device_types;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct amdgpu_atif {
|
|
|
|
struct amdgpu_atif_notifications notifications;
|
|
|
|
struct amdgpu_atif_functions functions;
|
|
|
|
struct amdgpu_atif_notification_cfg notification_cfg;
|
|
|
|
struct amdgpu_encoder *encoder_for_bl;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct amdgpu_atcs_functions {
|
|
|
|
bool get_ext_state;
|
|
|
|
bool pcie_perf_req;
|
|
|
|
bool pcie_dev_rdy;
|
|
|
|
bool pcie_bus_width;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct amdgpu_atcs {
|
|
|
|
struct amdgpu_atcs_functions functions;
|
|
|
|
};
|
|
|
|
|
2017-09-29 13:41:57 +07:00
|
|
|
/*
|
|
|
|
* Firmware VRAM reservation
|
|
|
|
*/
|
|
|
|
struct amdgpu_fw_vram_usage {
|
|
|
|
u64 start_offset;
|
|
|
|
u64 size;
|
|
|
|
struct amdgpu_bo *reserved_bo;
|
|
|
|
void *va;
|
|
|
|
};
|
|
|
|
|
2015-07-29 01:20:03 +07:00
|
|
|
/*
|
|
|
|
* CGS
|
|
|
|
*/
|
2016-04-12 10:25:48 +07:00
|
|
|
struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
|
|
|
|
void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
|
2015-09-23 04:05:20 +07:00
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/*
|
|
|
|
* Core structure, functions and helpers.
|
|
|
|
*/
|
|
|
|
typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
|
|
|
|
typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
|
|
|
|
|
|
|
|
typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
|
|
|
|
typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
|
|
|
|
|
2017-11-29 05:01:21 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* amdgpu nbio functions
|
|
|
|
*
|
|
|
|
*/
|
2017-12-09 01:07:58 +07:00
|
|
|
struct nbio_hdp_flush_reg {
|
|
|
|
u32 ref_and_mask_cp0;
|
|
|
|
u32 ref_and_mask_cp1;
|
|
|
|
u32 ref_and_mask_cp2;
|
|
|
|
u32 ref_and_mask_cp3;
|
|
|
|
u32 ref_and_mask_cp4;
|
|
|
|
u32 ref_and_mask_cp5;
|
|
|
|
u32 ref_and_mask_cp6;
|
|
|
|
u32 ref_and_mask_cp7;
|
|
|
|
u32 ref_and_mask_cp8;
|
|
|
|
u32 ref_and_mask_cp9;
|
|
|
|
u32 ref_and_mask_sdma0;
|
|
|
|
u32 ref_and_mask_sdma1;
|
|
|
|
};
|
2017-11-29 05:01:21 +07:00
|
|
|
|
|
|
|
struct amdgpu_nbio_funcs {
|
2017-12-09 01:07:58 +07:00
|
|
|
const struct nbio_hdp_flush_reg *hdp_flush_reg;
|
|
|
|
u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
|
|
|
|
u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
|
|
|
|
u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
|
|
|
|
u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
|
|
|
|
u32 (*get_rev_id)(struct amdgpu_device *adev);
|
|
|
|
void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
|
2018-01-19 20:17:40 +07:00
|
|
|
void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
|
2017-12-09 01:07:58 +07:00
|
|
|
u32 (*get_memsize)(struct amdgpu_device *adev);
|
|
|
|
void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
|
|
|
|
bool use_doorbell, int doorbell_index);
|
|
|
|
void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
|
|
|
|
bool enable);
|
|
|
|
void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
|
|
|
|
bool enable);
|
|
|
|
void (*ih_doorbell_range)(struct amdgpu_device *adev,
|
|
|
|
bool use_doorbell, int doorbell_index);
|
|
|
|
void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
|
|
|
|
bool enable);
|
|
|
|
void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
|
|
|
|
bool enable);
|
|
|
|
void (*get_clockgating_state)(struct amdgpu_device *adev,
|
|
|
|
u32 *flags);
|
|
|
|
void (*ih_control)(struct amdgpu_device *adev);
|
|
|
|
void (*init_registers)(struct amdgpu_device *adev);
|
|
|
|
void (*detect_hw_virt)(struct amdgpu_device *adev);
|
2017-11-29 05:01:21 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
2017-11-28 01:16:35 +07:00
|
|
|
/* Define the HW IP blocks will be used in driver , add more if necessary */
|
|
|
|
enum amd_hw_ip_block_type {
|
|
|
|
GC_HWIP = 1,
|
|
|
|
HDP_HWIP,
|
|
|
|
SDMA0_HWIP,
|
|
|
|
SDMA1_HWIP,
|
|
|
|
MMHUB_HWIP,
|
|
|
|
ATHUB_HWIP,
|
|
|
|
NBIO_HWIP,
|
|
|
|
MP0_HWIP,
|
|
|
|
UVD_HWIP,
|
|
|
|
VCN_HWIP = UVD_HWIP,
|
|
|
|
VCE_HWIP,
|
|
|
|
DF_HWIP,
|
|
|
|
DCE_HWIP,
|
|
|
|
OSSSYS_HWIP,
|
|
|
|
SMUIO_HWIP,
|
|
|
|
PWR_HWIP,
|
|
|
|
NBIF_HWIP,
|
|
|
|
MAX_HWIP
|
|
|
|
};
|
|
|
|
|
|
|
|
#define HWIP_MAX_INSTANCE 6
|
|
|
|
|
2017-09-29 15:07:14 +07:00
|
|
|
struct amd_powerplay {
|
|
|
|
void *pp_handle;
|
|
|
|
const struct amd_pm_funcs *pp_funcs;
|
|
|
|
};
|
|
|
|
|
2017-05-15 13:20:00 +07:00
|
|
|
#define AMDGPU_RESET_MAGIC_NUM 64
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_device {
|
|
|
|
struct device *dev;
|
|
|
|
struct drm_device *ddev;
|
|
|
|
struct pci_dev *pdev;
|
|
|
|
|
2015-09-23 04:05:20 +07:00
|
|
|
#ifdef CONFIG_DRM_AMD_ACP
|
|
|
|
struct amdgpu_acp acp;
|
|
|
|
#endif
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/* ASIC */
|
2015-07-22 10:29:01 +07:00
|
|
|
enum amd_asic_type asic_type;
|
2015-04-21 03:51:00 +07:00
|
|
|
uint32_t family;
|
|
|
|
uint32_t rev_id;
|
|
|
|
uint32_t external_rev_id;
|
|
|
|
unsigned long flags;
|
|
|
|
int usec_timeout;
|
|
|
|
const struct amdgpu_asic_funcs *asic_funcs;
|
|
|
|
bool shutdown;
|
|
|
|
bool need_dma32;
|
2018-02-09 09:44:09 +07:00
|
|
|
bool need_swiotlb;
|
2015-04-21 03:51:00 +07:00
|
|
|
bool accel_working;
|
2016-05-03 20:54:54 +07:00
|
|
|
struct work_struct reset_work;
|
2015-04-21 03:51:00 +07:00
|
|
|
struct notifier_block acpi_nb;
|
|
|
|
struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
|
|
|
|
struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
|
2016-05-03 20:54:54 +07:00
|
|
|
unsigned debugfs_count;
|
2015-04-21 03:51:00 +07:00
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
2016-04-16 00:08:44 +07:00
|
|
|
struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
|
2015-04-21 03:51:00 +07:00
|
|
|
#endif
|
|
|
|
struct amdgpu_atif atif;
|
|
|
|
struct amdgpu_atcs atcs;
|
|
|
|
struct mutex srbm_mutex;
|
|
|
|
/* GRBM index mutex. Protects concurrent access to GRBM index */
|
|
|
|
struct mutex grbm_idx_mutex;
|
|
|
|
struct dev_pm_domain vga_pm_domain;
|
|
|
|
bool have_disp_power_ref;
|
|
|
|
|
|
|
|
/* BIOS */
|
2017-02-14 04:01:58 +07:00
|
|
|
bool is_atom_fw;
|
2015-04-21 03:51:00 +07:00
|
|
|
uint8_t *bios;
|
2016-12-07 08:56:46 +07:00
|
|
|
uint32_t bios_size;
|
2017-08-08 18:48:01 +07:00
|
|
|
struct amdgpu_bo *stolen_vga_memory;
|
2016-09-24 03:23:41 +07:00
|
|
|
uint32_t bios_scratch_reg_offset;
|
2015-04-21 03:51:00 +07:00
|
|
|
uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
|
|
|
|
|
|
|
|
/* Register/doorbell mmio */
|
|
|
|
resource_size_t rmmio_base;
|
|
|
|
resource_size_t rmmio_size;
|
|
|
|
void __iomem *rmmio;
|
|
|
|
/* protects concurrent MM_INDEX/DATA based register access */
|
|
|
|
spinlock_t mmio_idx_lock;
|
|
|
|
/* protects concurrent SMC based register access */
|
|
|
|
spinlock_t smc_idx_lock;
|
|
|
|
amdgpu_rreg_t smc_rreg;
|
|
|
|
amdgpu_wreg_t smc_wreg;
|
|
|
|
/* protects concurrent PCIE register access */
|
|
|
|
spinlock_t pcie_idx_lock;
|
|
|
|
amdgpu_rreg_t pcie_rreg;
|
|
|
|
amdgpu_wreg_t pcie_wreg;
|
2016-08-31 12:23:25 +07:00
|
|
|
amdgpu_rreg_t pciep_rreg;
|
|
|
|
amdgpu_wreg_t pciep_wreg;
|
2015-04-21 03:51:00 +07:00
|
|
|
/* protects concurrent UVD register access */
|
|
|
|
spinlock_t uvd_ctx_idx_lock;
|
|
|
|
amdgpu_rreg_t uvd_ctx_rreg;
|
|
|
|
amdgpu_wreg_t uvd_ctx_wreg;
|
|
|
|
/* protects concurrent DIDT register access */
|
|
|
|
spinlock_t didt_idx_lock;
|
|
|
|
amdgpu_rreg_t didt_rreg;
|
|
|
|
amdgpu_wreg_t didt_wreg;
|
2016-06-08 11:47:41 +07:00
|
|
|
/* protects concurrent gc_cac register access */
|
|
|
|
spinlock_t gc_cac_idx_lock;
|
|
|
|
amdgpu_rreg_t gc_cac_rreg;
|
|
|
|
amdgpu_wreg_t gc_cac_wreg;
|
2017-07-04 08:21:50 +07:00
|
|
|
/* protects concurrent se_cac register access */
|
|
|
|
spinlock_t se_cac_idx_lock;
|
|
|
|
amdgpu_rreg_t se_cac_rreg;
|
|
|
|
amdgpu_wreg_t se_cac_wreg;
|
2015-04-21 03:51:00 +07:00
|
|
|
/* protects concurrent ENDPOINT (audio) register access */
|
|
|
|
spinlock_t audio_endpt_idx_lock;
|
|
|
|
amdgpu_block_rreg_t audio_endpt_rreg;
|
|
|
|
amdgpu_block_wreg_t audio_endpt_wreg;
|
|
|
|
void __iomem *rio_mem;
|
|
|
|
resource_size_t rio_mem_size;
|
|
|
|
struct amdgpu_doorbell doorbell;
|
|
|
|
|
|
|
|
/* clock/pll info */
|
|
|
|
struct amdgpu_clock clock;
|
|
|
|
|
|
|
|
/* MC */
|
2018-01-12 20:52:22 +07:00
|
|
|
struct amdgpu_gmc gmc;
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_gart gart;
|
2018-02-22 14:35:11 +07:00
|
|
|
dma_addr_t dummy_page_addr;
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_vm_manager vm_manager;
|
2017-03-09 23:36:26 +07:00
|
|
|
struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
/* memory management */
|
|
|
|
struct amdgpu_mman mman;
|
|
|
|
struct amdgpu_vram_scratch vram_scratch;
|
|
|
|
struct amdgpu_wb wb;
|
|
|
|
atomic64_t num_bytes_moved;
|
2016-06-21 21:28:14 +07:00
|
|
|
atomic64_t num_evictions;
|
2017-05-18 01:05:08 +07:00
|
|
|
atomic64_t num_vram_cpu_page_faults;
|
2015-05-06 02:13:49 +07:00
|
|
|
atomic_t gpu_reset_counter;
|
2017-05-15 15:48:27 +07:00
|
|
|
atomic_t vram_lost_counter;
|
2015-04-21 03:51:00 +07:00
|
|
|
|
2016-08-18 04:49:27 +07:00
|
|
|
/* data for buffer migration throttling */
|
|
|
|
struct {
|
|
|
|
spinlock_t lock;
|
|
|
|
s64 last_update_us;
|
|
|
|
s64 accum_us; /* accumulated microseconds */
|
2017-06-28 09:33:18 +07:00
|
|
|
s64 accum_us_vis; /* for visible VRAM */
|
2016-08-18 04:49:27 +07:00
|
|
|
u32 log2_max_MBps;
|
|
|
|
} mm_stats;
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/* display */
|
2016-08-10 15:01:25 +07:00
|
|
|
bool enable_virtual_display;
|
2015-04-21 03:51:00 +07:00
|
|
|
struct amdgpu_mode_info mode_info;
|
2017-09-13 02:58:20 +07:00
|
|
|
/* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
|
2015-04-21 03:51:00 +07:00
|
|
|
struct work_struct hotplug_work;
|
|
|
|
struct amdgpu_irq_src crtc_irq;
|
|
|
|
struct amdgpu_irq_src pageflip_irq;
|
|
|
|
struct amdgpu_irq_src hpd_irq;
|
|
|
|
|
|
|
|
/* rings */
|
2016-06-01 20:10:02 +07:00
|
|
|
u64 fence_context;
|
2015-04-21 03:51:00 +07:00
|
|
|
unsigned num_rings;
|
|
|
|
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
|
|
|
|
bool ib_pool_ready;
|
|
|
|
struct amdgpu_sa_manager ring_tmp_bo;
|
|
|
|
|
|
|
|
/* interrupts */
|
|
|
|
struct amdgpu_irq irq;
|
|
|
|
|
2015-12-03 05:46:21 +07:00
|
|
|
/* powerplay */
|
|
|
|
struct amd_powerplay powerplay;
|
drm/amd/powerplay: add some sysfs interfaces for powerplay.
The new sysfs interfaces:
pp_num_states: Read-only, return the number of all pp states, 0 if powerplay is not available.
pp_cur_state: Read-only, return the index number of current pp state.
pp_force_state: Read-write, to write a power state index will switch to selected state forcedly and
enable forced state mode, disable forced state mode. such as "echo >...".
pp_table: Read-write, binary output, to be used to read or write the dpm table, the maximum
file size is 4KB of page size.
pp_dpm_sclk: Read-write, reading will return a dpm levels list, to write an index number will force
powerplay to set the corresponding dpm level.
pp_dpm_mclk: same as sclk.
pp_dpm_pcie: same as sclk.
And add new setting "manual" to the existing interface power_dpm_force_performance_level.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-12 04:24:34 +07:00
|
|
|
bool pp_force_state_enabled;
|
2015-12-03 05:46:21 +07:00
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/* dpm */
|
|
|
|
struct amdgpu_pm pm;
|
|
|
|
u32 cg_flags;
|
|
|
|
u32 pg_flags;
|
|
|
|
|
|
|
|
/* amdgpu smumgr */
|
|
|
|
struct amdgpu_smumgr smu;
|
|
|
|
|
|
|
|
/* gfx */
|
|
|
|
struct amdgpu_gfx gfx;
|
|
|
|
|
|
|
|
/* sdma */
|
2015-10-09 03:30:37 +07:00
|
|
|
struct amdgpu_sdma sdma;
|
2015-04-21 03:51:00 +07:00
|
|
|
|
2017-11-21 21:08:07 +07:00
|
|
|
/* uvd */
|
|
|
|
struct amdgpu_uvd uvd;
|
|
|
|
|
|
|
|
/* vce */
|
|
|
|
struct amdgpu_vce vce;
|
|
|
|
|
|
|
|
/* vcn */
|
|
|
|
struct amdgpu_vcn vcn;
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
/* firmwares */
|
|
|
|
struct amdgpu_firmware firmware;
|
|
|
|
|
2017-03-04 06:37:23 +07:00
|
|
|
/* PSP */
|
|
|
|
struct psp_context psp;
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/* GDS */
|
|
|
|
struct amdgpu_gds gds;
|
|
|
|
|
2017-09-13 02:58:20 +07:00
|
|
|
/* display related functionality */
|
|
|
|
struct amdgpu_display_manager dm;
|
|
|
|
|
2016-10-14 04:41:13 +07:00
|
|
|
struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
|
2015-04-21 03:51:00 +07:00
|
|
|
int num_ip_blocks;
|
|
|
|
struct mutex mn_lock;
|
|
|
|
DECLARE_HASHTABLE(mn_hash, 7);
|
|
|
|
|
|
|
|
/* tracking pinned memory */
|
|
|
|
u64 vram_pin_size;
|
2016-04-05 09:48:48 +07:00
|
|
|
u64 invisible_pin_size;
|
2015-04-21 03:51:00 +07:00
|
|
|
u64 gart_pin_size;
|
2015-06-13 01:35:14 +07:00
|
|
|
|
|
|
|
/* amdkfd interface */
|
|
|
|
struct kfd_dev *kfd;
|
2015-07-06 12:42:58 +07:00
|
|
|
|
2017-11-28 01:16:35 +07:00
|
|
|
/* soc15 register offset based on ip, instance and segment */
|
|
|
|
uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
|
|
|
|
|
2017-11-29 05:01:21 +07:00
|
|
|
const struct amdgpu_nbio_funcs *nbio_funcs;
|
|
|
|
|
2017-05-25 11:35:25 +07:00
|
|
|
/* delayed work_func for deferring clockgating during resume */
|
|
|
|
struct delayed_work late_init_work;
|
|
|
|
|
2017-01-10 06:06:57 +07:00
|
|
|
struct amdgpu_virt virt;
|
2017-09-29 13:41:57 +07:00
|
|
|
/* firmware VRAM reservation */
|
|
|
|
struct amdgpu_fw_vram_usage fw_vram_usage;
|
2016-08-17 10:41:30 +07:00
|
|
|
|
|
|
|
/* link all shadow bo */
|
|
|
|
struct list_head shadow_list;
|
|
|
|
struct mutex shadow_list_lock;
|
2017-03-07 04:27:55 +07:00
|
|
|
/* keep an lru list of rings by HW IP */
|
|
|
|
struct list_head ring_lru_list;
|
|
|
|
spinlock_t ring_lru_list_lock;
|
2016-08-30 15:13:10 +07:00
|
|
|
|
2017-02-10 14:59:59 +07:00
|
|
|
/* record hw reset is performed */
|
|
|
|
bool has_hw_reset;
|
2017-05-15 13:20:00 +07:00
|
|
|
u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
|
2017-02-10 14:59:59 +07:00
|
|
|
|
2017-07-04 12:11:52 +07:00
|
|
|
/* record last mm index being written through WREG32*/
|
|
|
|
unsigned long last_mm_index;
|
2017-10-17 14:11:12 +07:00
|
|
|
bool in_gpu_reset;
|
|
|
|
struct mutex lock_reset;
|
2015-04-21 03:51:00 +07:00
|
|
|
};
|
|
|
|
|
2016-09-15 19:58:48 +07:00
|
|
|
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
|
|
|
|
{
|
|
|
|
return container_of(bdev, struct amdgpu_device, mman.bdev);
|
|
|
|
}
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
int amdgpu_device_init(struct amdgpu_device *adev,
|
|
|
|
struct drm_device *ddev,
|
|
|
|
struct pci_dev *pdev,
|
|
|
|
uint32_t flags);
|
|
|
|
void amdgpu_device_fini(struct amdgpu_device *adev);
|
|
|
|
int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
|
|
|
|
|
|
|
|
uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
|
2017-01-25 14:07:40 +07:00
|
|
|
uint32_t acc_flags);
|
2015-04-21 03:51:00 +07:00
|
|
|
void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
|
2017-01-25 14:07:40 +07:00
|
|
|
uint32_t acc_flags);
|
2018-01-04 17:13:20 +07:00
|
|
|
void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
|
|
|
|
uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
|
|
|
|
void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
|
|
|
|
|
|
|
|
u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
|
|
|
|
void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
|
2016-03-18 14:23:08 +07:00
|
|
|
u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
|
|
|
|
void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
|
2015-04-21 03:51:00 +07:00
|
|
|
|
2017-09-13 02:58:20 +07:00
|
|
|
bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
|
|
|
|
bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
|
|
|
|
|
2018-02-02 06:13:23 +07:00
|
|
|
int emu_soc_asic_init(struct amdgpu_device *adev);
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/*
|
|
|
|
* Registers read & write functions.
|
|
|
|
*/
|
2017-01-25 14:07:40 +07:00
|
|
|
|
|
|
|
#define AMDGPU_REGS_IDX (1<<0)
|
|
|
|
#define AMDGPU_REGS_NO_KIQ (1<<1)
|
|
|
|
|
|
|
|
#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
|
|
|
|
#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
|
|
|
|
|
2018-01-04 17:13:20 +07:00
|
|
|
#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
|
|
|
|
#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
|
|
|
|
|
2017-01-25 14:07:40 +07:00
|
|
|
#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
|
|
|
|
#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
|
|
|
|
#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
|
|
|
|
#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
|
|
|
|
#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
|
2015-04-21 03:51:00 +07:00
|
|
|
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
|
|
|
|
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
|
|
|
|
#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
|
|
|
|
#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
|
2016-08-31 12:23:25 +07:00
|
|
|
#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
|
|
|
|
#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
|
2015-04-21 03:51:00 +07:00
|
|
|
#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
|
|
|
|
#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
|
|
|
|
#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
|
|
|
|
#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
|
|
|
|
#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
|
|
|
|
#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
|
2016-06-08 11:47:41 +07:00
|
|
|
#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
|
|
|
|
#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
|
2017-07-04 08:21:50 +07:00
|
|
|
#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
|
|
|
|
#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
|
2015-04-21 03:51:00 +07:00
|
|
|
#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
|
|
|
|
#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
|
|
|
|
#define WREG32_P(reg, val, mask) \
|
|
|
|
do { \
|
|
|
|
uint32_t tmp_ = RREG32(reg); \
|
|
|
|
tmp_ &= (mask); \
|
|
|
|
tmp_ |= ((val) & ~(mask)); \
|
|
|
|
WREG32(reg, tmp_); \
|
|
|
|
} while (0)
|
|
|
|
#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
|
|
|
|
#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
|
|
|
|
#define WREG32_PLL_P(reg, val, mask) \
|
|
|
|
do { \
|
|
|
|
uint32_t tmp_ = RREG32_PLL(reg); \
|
|
|
|
tmp_ &= (mask); \
|
|
|
|
tmp_ |= ((val) & ~(mask)); \
|
|
|
|
WREG32_PLL(reg, tmp_); \
|
|
|
|
} while (0)
|
|
|
|
#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
|
|
|
|
#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
|
|
|
|
#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
|
|
|
|
|
|
|
|
#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
|
|
|
|
#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
|
2016-03-18 14:23:08 +07:00
|
|
|
#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
|
|
|
|
#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
|
|
|
|
#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
|
|
|
|
|
|
|
|
#define REG_SET_FIELD(orig_val, reg, field, field_val) \
|
|
|
|
(((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
|
|
|
|
(REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
|
|
|
|
|
|
|
|
#define REG_GET_FIELD(value, reg, field) \
|
|
|
|
(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
|
2016-08-09 21:13:21 +07:00
|
|
|
|
|
|
|
#define WREG32_FIELD(reg, field, val) \
|
|
|
|
WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
|
2015-04-21 03:51:00 +07:00
|
|
|
|
2017-04-04 20:14:13 +07:00
|
|
|
#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
|
|
|
|
WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/*
|
|
|
|
* BIOS helpers.
|
|
|
|
*/
|
|
|
|
#define RBIOS8(i) (adev->bios[i])
|
|
|
|
#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
|
|
|
|
#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
|
|
|
|
|
2015-10-09 03:30:37 +07:00
|
|
|
static inline struct amdgpu_sdma_instance *
|
|
|
|
amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
|
2015-09-01 11:56:17 +07:00
|
|
|
{
|
|
|
|
struct amdgpu_device *adev = ring->adev;
|
|
|
|
int i;
|
|
|
|
|
2015-10-09 03:30:37 +07:00
|
|
|
for (i = 0; i < adev->sdma.num_instances; i++)
|
|
|
|
if (&adev->sdma.instance[i].ring == ring)
|
2015-09-01 11:56:17 +07:00
|
|
|
break;
|
|
|
|
|
|
|
|
if (i < AMDGPU_MAX_SDMA_INSTANCES)
|
2015-10-09 03:30:37 +07:00
|
|
|
return &adev->sdma.instance[i];
|
2015-09-01 11:56:17 +07:00
|
|
|
else
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2015-04-21 03:51:00 +07:00
|
|
|
/*
|
|
|
|
* ASICs macro.
|
|
|
|
*/
|
|
|
|
#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
|
|
|
|
#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
|
|
|
|
#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
|
|
|
|
#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
|
|
|
|
#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
|
2016-08-01 23:42:32 +07:00
|
|
|
#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
|
|
|
|
#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
|
|
|
|
#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
|
2015-04-21 03:51:00 +07:00
|
|
|
#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
|
2015-11-24 22:14:28 +07:00
|
|
|
#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
|
2015-04-21 03:51:00 +07:00
|
|
|
#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
|
2017-03-04 05:26:10 +07:00
|
|
|
#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
|
2018-01-19 20:17:40 +07:00
|
|
|
#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
|
|
|
|
#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
|
2018-01-12 21:26:08 +07:00
|
|
|
#define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
|
2018-02-04 16:32:35 +07:00
|
|
|
#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
|
|
|
|
#define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
|
2018-01-12 21:26:08 +07:00
|
|
|
#define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
|
|
|
|
#define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
|
|
|
|
#define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
|
2015-04-21 03:51:00 +07:00
|
|
|
#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
|
2016-08-12 16:33:30 +07:00
|
|
|
#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
|
2015-04-21 03:51:00 +07:00
|
|
|
#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
|
|
|
|
#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
|
|
|
|
#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
|
2016-07-06 02:07:17 +07:00
|
|
|
#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
|
2015-04-21 03:51:00 +07:00
|
|
|
#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
|
|
|
|
#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
|
|
|
|
#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
|
2017-12-18 23:08:25 +07:00
|
|
|
#define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c))
|
2016-03-01 21:42:52 +07:00
|
|
|
#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
|
2018-02-04 16:32:35 +07:00
|
|
|
#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
|
2015-06-01 13:35:03 +07:00
|
|
|
#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
|
2015-04-21 03:51:00 +07:00
|
|
|
#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
|
2015-05-11 19:10:34 +07:00
|
|
|
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
|
2016-08-26 13:12:37 +07:00
|
|
|
#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
|
2016-08-26 12:28:28 +07:00
|
|
|
#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
|
2017-01-10 11:53:52 +07:00
|
|
|
#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
|
|
|
|
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
|
2018-01-26 18:45:32 +07:00
|
|
|
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
|
2017-05-01 17:09:22 +07:00
|
|
|
#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
|
2016-01-31 18:20:55 +07:00
|
|
|
#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
|
2016-01-14 18:07:38 +07:00
|
|
|
#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
|
|
|
|
#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
|
2015-04-21 03:51:00 +07:00
|
|
|
#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
|
2017-08-26 13:40:45 +07:00
|
|
|
#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
|
2015-04-21 03:51:00 +07:00
|
|
|
#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
|
|
|
|
#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
|
|
|
|
#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
|
|
|
|
#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
|
|
|
|
#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
|
|
|
|
#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
|
|
|
|
#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
|
|
|
|
#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
|
|
|
|
#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
|
2016-05-06 03:03:57 +07:00
|
|
|
#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
|
2015-04-21 03:51:00 +07:00
|
|
|
#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
|
|
|
|
#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
|
|
|
|
#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
|
2015-08-25 16:23:45 +07:00
|
|
|
#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
|
2015-08-27 12:46:09 +07:00
|
|
|
#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
|
2016-07-08 02:01:42 +07:00
|
|
|
#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
|
2016-06-28 21:26:48 +07:00
|
|
|
#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
|
2015-04-21 03:51:00 +07:00
|
|
|
#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
|
2017-03-04 06:37:23 +07:00
|
|
|
#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
/* Common functions */
|
2017-12-16 04:40:49 +07:00
|
|
|
int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
|
|
|
|
struct amdgpu_job* job, bool force);
|
2017-12-15 04:22:53 +07:00
|
|
|
void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
|
2017-12-16 04:22:11 +07:00
|
|
|
bool amdgpu_device_need_post(struct amdgpu_device *adev);
|
2018-01-20 03:28:27 +07:00
|
|
|
void amdgpu_display_update_priority(struct amdgpu_device *adev);
|
2015-07-21 15:52:10 +07:00
|
|
|
|
2017-06-28 09:33:18 +07:00
|
|
|
void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
|
|
|
|
u64 num_vis_bytes);
|
2016-09-15 20:06:50 +07:00
|
|
|
void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
|
2015-04-21 03:51:00 +07:00
|
|
|
bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
|
2017-12-15 04:33:36 +07:00
|
|
|
void amdgpu_device_vram_location(struct amdgpu_device *adev,
|
2018-01-12 20:52:22 +07:00
|
|
|
struct amdgpu_gmc *mc, u64 base);
|
2017-12-15 04:33:36 +07:00
|
|
|
void amdgpu_device_gart_location(struct amdgpu_device *adev,
|
2018-01-12 20:52:22 +07:00
|
|
|
struct amdgpu_gmc *mc);
|
2017-02-28 16:36:43 +07:00
|
|
|
int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
|
2017-12-15 04:20:19 +07:00
|
|
|
void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
|
2015-04-21 03:51:00 +07:00
|
|
|
const u32 *registers,
|
|
|
|
const u32 array_size);
|
|
|
|
|
|
|
|
bool amdgpu_device_is_px(struct drm_device *dev);
|
|
|
|
/* atpx handler */
|
|
|
|
#if defined(CONFIG_VGA_SWITCHEROO)
|
|
|
|
void amdgpu_register_atpx_handler(void);
|
|
|
|
void amdgpu_unregister_atpx_handler(void);
|
2016-06-02 00:08:21 +07:00
|
|
|
bool amdgpu_has_atpx_dgpu_power_cntl(void);
|
2016-06-02 20:04:01 +07:00
|
|
|
bool amdgpu_is_atpx_hybrid(void);
|
2016-09-15 01:01:41 +07:00
|
|
|
bool amdgpu_atpx_dgpu_req_power_for_displays(void);
|
2017-04-05 22:07:13 +07:00
|
|
|
bool amdgpu_has_atpx(void);
|
2015-04-21 03:51:00 +07:00
|
|
|
#else
|
|
|
|
static inline void amdgpu_register_atpx_handler(void) {}
|
|
|
|
static inline void amdgpu_unregister_atpx_handler(void) {}
|
2016-06-02 00:08:21 +07:00
|
|
|
static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
|
2016-06-02 20:04:01 +07:00
|
|
|
static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
|
2016-09-15 01:01:41 +07:00
|
|
|
static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
|
2017-04-05 22:07:13 +07:00
|
|
|
static inline bool amdgpu_has_atpx(void) { return false; }
|
2015-04-21 03:51:00 +07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* KMS
|
|
|
|
*/
|
|
|
|
extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
|
2016-04-10 21:29:59 +07:00
|
|
|
extern const int amdgpu_max_kms_ioctl;
|
2015-04-21 03:51:00 +07:00
|
|
|
|
|
|
|
int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
|
2017-01-07 00:57:31 +07:00
|
|
|
void amdgpu_driver_unload_kms(struct drm_device *dev);
|
2015-04-21 03:51:00 +07:00
|
|
|
void amdgpu_driver_lastclose_kms(struct drm_device *dev);
|
|
|
|
int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
|
|
|
|
void amdgpu_driver_postclose_kms(struct drm_device *dev,
|
|
|
|
struct drm_file *file_priv);
|
2017-12-15 04:47:40 +07:00
|
|
|
int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
|
2016-08-24 00:25:49 +07:00
|
|
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int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
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int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
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2015-09-24 23:35:31 +07:00
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u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
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int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
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void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
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2015-04-21 03:51:00 +07:00
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long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
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unsigned long arg);
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/*
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* functions used by amdgpu_encoder.c
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*/
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struct amdgpu_afmt_acr {
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u32 clock;
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int n_32khz;
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int cts_32khz;
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int n_44_1khz;
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int cts_44_1khz;
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int n_48khz;
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int cts_48khz;
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};
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struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
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/* amdgpu_acpi.c */
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#if defined(CONFIG_ACPI)
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int amdgpu_acpi_init(struct amdgpu_device *adev);
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void amdgpu_acpi_fini(struct amdgpu_device *adev);
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bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
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int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
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u8 perf_req, bool advertise);
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int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
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#else
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static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
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static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
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#endif
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2017-09-06 21:15:28 +07:00
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int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
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uint64_t addr, struct amdgpu_bo **bo,
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struct amdgpu_bo_va_mapping **mapping);
|
2015-04-21 03:51:00 +07:00
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2017-09-13 02:58:20 +07:00
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#if defined(CONFIG_DRM_AMD_DC)
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int amdgpu_dm_display_resume(struct amdgpu_device *adev );
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#else
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static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
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#endif
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2015-04-21 03:51:00 +07:00
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#include "amdgpu_object.h"
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#endif
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