linux_dsm_epyc7002/drivers/gpu/drm/i915/gt
Chris Wilson 0a1f57b86c drm/i915/execlists: Reset CSB pointers by mmio as well
Sometimes Icelake forgets to reset the CSB pointers on a GPU reset,
leading to it carry on updating the old tail of the buffer.

<0>[  618.138490] i915_sel-5636    3d..1 673425465us : trace_ports: vecs0: submit { 14de2:504, 0:0 }
<0>[  618.138490] i915_sel-5636    3.... 673425493us : intel_engine_reset: vecs0 flags=100
<0>[  618.138490] i915_sel-5636    3.... 673425493us : execlists_reset_prepare: vecs0: depth<-0
<0>[  618.138490] i915_sel-5636    3.... 673425493us : intel_engine_stop_cs: vecs0
<0>[  618.138490] i915_sel-5636    3.... 673425523us : __intel_gt_reset: engine_mask=40
<0>[  618.138490] i915_sel-5636    3.... 673425568us : execlists_reset: vecs0
<0>[  618.138490] i915_sel-5636    3d..1 673425568us : process_csb: vecs0 cs-irq head=1, tail=2
<0>[  618.138490] i915_sel-5636    3d..1 673425568us : process_csb: vecs0 csb[2]: status=0x00000001:0x40000000
<0>[  618.138490] i915_sel-5636    3d..1 673425569us : trace_ports: vecs0: promote { 14de2:504*, 0:0 }
<0>[  618.138490] i915_sel-5636    3d..1 673425570us : __i915_request_reset: vecs0 rq=14de2:504, guilty? yes
<0>[  618.138490] i915_sel-5636    3d..1 673425571us : __execlists_reset: vecs0 replay {head:2de0, tail:2e48}
<0>[  618.138490] i915_sel-5636    3d..1 673425572us : __i915_request_unsubmit: vecs0 fence 14de2:504, current 503
<0>[  618.138490] i915_sel-5636    3.... 673435544us : intel_engine_cancel_stop_cs: vecs0
<0>[  618.138490] i915_sel-5636    3.... 673435544us : process_csb: vecs0 cs-irq head=11, tail=11
<0>[  618.138490] i915_sel-5636    3d..1 673435545us : __i915_request_submit: vecs0 fence 14de2:504, current 503
<0>[  618.138490] i915_sel-5636    3d..1 673435546us : __execlists_submission_tasklet: vecs0: queue_priority_hint:-2147483648, submit:yes
<0>[  618.138490] i915_sel-5636    3d..1 673435548us : trace_ports: vecs0: submit { 14de2:504*, 0:0 }
<0>[  618.138490] i915_sel-5636    3.... 673435549us : execlists_reset_finish: vecs0: depth->0
<0>[  618.138490] ksoftirq-21      2..s. 673435592us : process_csb: vecs0 cs-irq head=11, tail=3
<0>[  618.138490] ksoftirq-21      2..s. 673435593us : process_csb: vecs0 csb[0]: status=0x00000001:0x40000000
<0>[  618.138490] ksoftirq-21      2..s. 673435594us : trace_ports: vecs0: promote { 14de2:504*, 0:0 }
<0>[  618.138490] ksoftirq-21      2..s. 673435596us : process_csb: vecs0 csb[1]: status=0x00000018:0x40000040
<0>[  618.138490] ksoftirq-21      2..s. 673435597us : trace_ports: vecs0: completed { 14de2:504*, 0:0 }
<0>[  618.138490] ksoftirq-21      2..s. 673435612us : process_csb: process_csb:2188 GEM_BUG_ON(!i915_request_completed(*execlists->active) && !reset_in_progress(execlists))

After the reset, we do another clflush before checking the CSB to be
sure we see whatever was left in the CSB prior to the reset. So it is
unlikely to be an incoherent view of the CSB, and more likely that
Icelake didn't reset its pointers.

References: 582a6f90aa ("drm/i915/execlists: Add a paranoid flush of the CSB pointers upon reset")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191104135307.21083-1-chris@chris-wilson.co.uk
2019-11-04 15:54:26 +00:00
..
selftests drm/i915: Coordinate i915_active with its own mutex 2019-10-04 15:39:12 +01:00
uc drm/i915/guc: drop guc shared area 2019-10-31 16:47:23 +00:00
gen6_renderstate.c drm/i915: Move the renderstate setup under gt/ 2019-07-04 11:48:22 +01:00
gen7_renderstate.c drm/i915: Move the renderstate setup under gt/ 2019-07-04 11:48:22 +01:00
gen8_renderstate.c drm/i915: Move the renderstate setup under gt/ 2019-07-04 11:48:22 +01:00
gen9_renderstate.c drm/i915: Move the renderstate setup under gt/ 2019-07-04 11:48:22 +01:00
intel_breadcrumbs.c drm/i915: Don't disable interrupts for intel_engine_breadcrumbs_irq() 2019-09-26 18:44:35 +01:00
intel_context_types.h drm/i915: Remove logical HW ID 2019-10-04 15:39:30 +01:00
intel_context.c drm/i915/gt: Split intel_ring_submission 2019-10-24 12:14:21 +01:00
intel_context.h drm/i915/gt: Split intel_ring_submission 2019-10-24 12:14:21 +01:00
intel_engine_cs.c drm/i915/gt: Make timeslice duration configurable 2019-10-29 16:23:55 +00:00
intel_engine_heartbeat.c drm/i915: Encapsulate kconfig constant values inside boolean predicates 2019-10-26 09:25:25 +01:00
intel_engine_heartbeat.h drm/i915/gt: Replace hangcheck by heartbeats 2019-10-23 23:52:10 +01:00
intel_engine_pm.c drm/i915/gt: Split intel_ring_submission 2019-10-24 12:14:21 +01:00
intel_engine_pm.h drm/i915: Defer final intel_wakeref_put to process context 2019-08-08 21:28:51 +01:00
intel_engine_pool_types.h drm/i915: Replace struct_mutex for batch pool serialisation 2019-08-04 14:31:18 +01:00
intel_engine_pool.c drm/i915: Coordinate i915_active with its own mutex 2019-10-04 15:39:12 +01:00
intel_engine_pool.h drm/i915: Mark i915_request.timeline as a volatile, rcu pointer 2019-09-20 10:24:09 +01:00
intel_engine_types.h drm/i915/gt: Make timeslice duration configurable 2019-10-29 16:23:55 +00:00
intel_engine_user.c drm/i915: Make for_each_engine_masked work on intel_gt 2019-10-18 00:06:25 +01:00
intel_engine_user.h drm/i915: Rename engines to match their user interface 2019-08-07 14:30:55 +01:00
intel_engine.h drm/i915/gt: Make timeslice duration configurable 2019-10-29 16:23:55 +00:00
intel_gpu_commands.h drm/i915/tgl: Add HDC Pipeline Flush 2019-10-15 18:15:59 +01:00
intel_gt_irq.c drm/i915: Extract GT render power state management 2019-10-26 19:28:59 +01:00
intel_gt_irq.h drm/i915: Extract general GT interrupt handlers 2019-08-12 15:36:13 +01:00
intel_gt_pm_irq.c drm/i915: Extract general GT interrupt handlers 2019-08-12 15:36:13 +01:00
intel_gt_pm_irq.h drm/i915: Extract GT powermanagement interrupt handling 2019-08-12 15:36:06 +01:00
intel_gt_pm.c drm/i915/gt: Drop false assertion on user_forcewake 2019-11-04 09:40:25 +00:00
intel_gt_pm.h drm/i915: Defer rc6 shutdown to suspend_late 2019-11-01 14:47:36 +00:00
intel_gt_requests.c drm/i915: Pass in intel_gt at some for_each_engine sites 2019-10-18 00:06:27 +01:00
intel_gt_requests.h drm/i915: Move request runtime management onto gt 2019-10-04 15:39:26 +01:00
intel_gt_types.h drm/i915: Extract GT render power state management 2019-10-26 19:28:59 +01:00
intel_gt.c drm/i915/gt: Call intel_gt_sanitize() directly 2019-11-01 14:47:36 +00:00
intel_gt.h drm/i915/gt: Call intel_gt_sanitize() directly 2019-11-01 14:47:36 +00:00
intel_llc_types.h drm/i915: Extract GT ring management 2019-10-20 20:45:18 +01:00
intel_llc.c drm/i915: Extract GT render power state management 2019-10-26 19:28:59 +01:00
intel_llc.h drm/i915: Extract GT ring management 2019-10-20 20:45:18 +01:00
intel_lrc_reg.h drm/i915/execlists: Verify context register state before execution 2019-11-02 13:39:13 +00:00
intel_lrc.c drm/i915/execlists: Reset CSB pointers by mmio as well 2019-11-04 15:54:26 +00:00
intel_lrc.h drm/i915: drop lrc header page 2019-10-31 16:47:22 +00:00
intel_mocs.c drm/i915: do not set MOCS control values on dgfx 2019-10-25 13:55:49 -07:00
intel_mocs.h drm/i915: Do initial mocs configuration directly 2019-10-16 19:35:37 +01:00
intel_rc6_types.h drm/i915: Extract GT render sleep (rc6) management 2019-09-27 13:01:57 +01:00
intel_rc6.c drm/i915: Defer rc6 shutdown to suspend_late 2019-11-01 14:47:36 +00:00
intel_rc6.h drm/i915: Extract GT render sleep (rc6) management 2019-09-27 13:01:57 +01:00
intel_renderstate.c drm/i915/gt: Split intel_ring_submission 2019-10-24 12:14:21 +01:00
intel_renderstate.h drm/i915: Move the renderstate setup under gt/ 2019-07-04 11:48:22 +01:00
intel_reset_types.h drm/i915: Define explicit wedged on init reset state 2019-09-26 18:44:35 +01:00
intel_reset.c drm/i915/gt: Replace hangcheck by heartbeats 2019-10-23 23:52:10 +01:00
intel_reset.h drm/i915: Pass intel_gt to has-reset? 2019-09-27 23:25:14 +01:00
intel_ring_submission.c drm/i915/gt: Split intel_ring_submission 2019-10-24 12:14:21 +01:00
intel_ring_types.h drm/i915/gt: Split intel_ring_submission 2019-10-24 12:14:21 +01:00
intel_ring.c drm/i915: don't allocate the ring in stolen if we lack aperture 2019-10-29 10:35:47 +00:00
intel_ring.h drm/i915/gt: Split intel_ring_submission 2019-10-24 12:14:21 +01:00
intel_rps_types.h drm/i915: Extract GT render power state management 2019-10-26 19:28:59 +01:00
intel_rps.c drm/i915/gt: Always track callers to intel_rps_mark_interactive() 2019-10-30 13:23:00 +00:00
intel_rps.h drm/i915/gt: Always track callers to intel_rps_mark_interactive() 2019-10-30 13:23:00 +00:00
intel_sseu.c drm/i915: Expand subslice mask 2019-08-23 19:14:27 +01:00
intel_sseu.h drm/i915/tgl: s/ss/eu fuse reading support 2019-09-21 08:31:08 +01:00
intel_timeline_types.h drm/i915: Coordinate i915_active with its own mutex 2019-10-04 15:39:12 +01:00
intel_timeline.c drm/i915/gt: Pull timeline initialise to intel_gt_init_early 2019-11-01 14:47:36 +00:00
intel_timeline.h drm/i915/gt: Pull timeline initialise to intel_gt_init_early 2019-11-01 14:47:36 +00:00
intel_workarounds_types.h drm/i915: Add engine name to workaround debug print 2019-07-12 09:55:30 +01:00
intel_workarounds.c drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT 2019-10-24 23:34:38 +01:00
intel_workarounds.h drm/i915: Convert gt workarounds to intel_gt 2019-06-21 13:48:25 +01:00
Makefile drm/i915: use upstream version of header tests 2019-07-30 12:11:57 +03:00
mock_engine.c drm/i915/gt: Split intel_ring_submission 2019-10-24 12:14:21 +01:00
mock_engine.h
selftest_context.c drm/i915: drop lrc header page 2019-10-31 16:47:22 +00:00
selftest_engine_cs.c drm/i915: Rename engines to match their user interface 2019-08-07 14:30:55 +01:00
selftest_engine_heartbeat.c drm/i915/selftests: Flush all active callbacks 2019-11-02 08:34:53 +00:00
selftest_engine_pm.c drm/i915: Pass in intel_gt at some for_each_engine sites 2019-10-18 00:06:27 +01:00
selftest_engine.c drm/i915: Defer final intel_wakeref_put to process context 2019-08-08 21:28:51 +01:00
selftest_engine.h drm/i915: Defer final intel_wakeref_put to process context 2019-08-08 21:28:51 +01:00
selftest_gt_pm.c drm/i915/selftests: Add intel_gt_suspend_prepare 2019-11-01 18:52:23 +00:00
selftest_hangcheck.c drm/i915/selftests: Start kthreads before stopping 2019-11-01 10:12:29 +00:00
selftest_llc.c drm/i915: Extract GT render power state management 2019-10-26 19:28:59 +01:00
selftest_llc.h drm/i915: Extract GT ring management 2019-10-20 20:45:18 +01:00
selftest_lrc.c drm/i915/execlists: Verify context register state before execution 2019-11-02 13:39:13 +00:00
selftest_reset.c drm/i915/selftests: Flush interrupts before disabling tasklets 2019-10-24 09:18:52 +01:00
selftest_timeline.c drm/i915/gt: Split intel_ring_submission 2019-10-24 12:14:21 +01:00
selftest_workarounds.c drm/i915: Remove nonpriv flags when srm/lrm 2019-10-24 23:34:38 +01:00