linux_dsm_epyc7002/drivers/gpu/drm/i915/gt
Chris Wilson 93100fdeb4 drm/i915/selftests: Flush interrupts before disabling tasklets
When setting up the system to perform the atomic reset, we need to
serialise with any ongoing interrupt tasklet or else:

<0> [472.951428] i915_sel-4442    0d..1 466527056us : __i915_request_submit: rcs0 fence 11659:2, current 0
<0> [472.951554] i915_sel-4442    0d..1 466527059us : __execlists_submission_tasklet: rcs0: queue_priority_hint:-2147483648, submit:yes
<0> [472.951681] i915_sel-4442    0d..1 466527061us : trace_ports: rcs0: submit { 11659:2, 0:0 }
<0> [472.951805] i915_sel-4442    0.... 466527114us : __igt_atomic_reset_engine: i915_reset_engine(rcs0:active) under hardirq
<0> [472.951932] i915_sel-4442    0d... 466527115us : intel_engine_reset: rcs0 flags=11d
<0> [472.952056] i915_sel-4442    0d... 466527117us : execlists_reset_prepare: rcs0: depth<-1
<0> [472.952179] i915_sel-4442    0d... 466527119us : intel_engine_stop_cs: rcs0
<0> [472.952305]   <idle>-0       1..s1 466527119us : process_csb: rcs0 cs-irq head=3, tail=4
<0> [472.952431] i915_sel-4442    0d... 466527122us : __intel_gt_reset: engine_mask=1
<0> [472.952557]   <idle>-0       1..s1 466527124us : process_csb: rcs0 csb[4]: status=0x00000001:0x00000000
<0> [472.952683]   <idle>-0       1..s1 466527130us : trace_ports: rcs0: promote { 11659:2*, 0:0 }
<0> [472.952808] i915_sel-4442    0d... 466527131us : execlists_reset: rcs0
<0> [472.952933] i915_sel-4442    0d..1 466527133us : process_csb: rcs0 cs-irq head=3, tail=4
<0> [472.953059] i915_sel-4442    0d..1 466527134us : process_csb: rcs0 csb[4]: status=0x00000001:0x00000000
<0> [472.953185] i915_sel-4442    0d..1 466527136us : trace_ports: rcs0: preempted { 11659:2*, 0:0 }
<0> [472.953310] i915_sel-4442    0d..1 466527150us : assert_pending_valid: Nothing pending for promotion!
<0> [472.953436] i915_sel-4442    0d..1 466527158us : process_csb: process_csb:1930 GEM_BUG_ON(!assert_pending_valid(execlists, "promote"))

We have the same CSB events being seen by process_csb() on two different
processors. One being issued by the reset in the test, the other by the
interrupt; this scenario is supposed to be prevented by flushing the
interrupt tasklet with tasklet_disable() before we enter the atomic
reset.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112069
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191023232443.17450-1-chris@chris-wilson.co.uk
2019-10-24 09:18:52 +01:00
..
selftests drm/i915: Coordinate i915_active with its own mutex 2019-10-04 15:39:12 +01:00
uc drm/i915/guc: Update H2G enable logging action definition 2019-10-23 15:05:01 -07:00
gen6_renderstate.c drm/i915: Move the renderstate setup under gt/ 2019-07-04 11:48:22 +01:00
gen7_renderstate.c drm/i915: Move the renderstate setup under gt/ 2019-07-04 11:48:22 +01:00
gen8_renderstate.c drm/i915: Move the renderstate setup under gt/ 2019-07-04 11:48:22 +01:00
gen9_renderstate.c drm/i915: Move the renderstate setup under gt/ 2019-07-04 11:48:22 +01:00
intel_breadcrumbs.c drm/i915: Don't disable interrupts for intel_engine_breadcrumbs_irq() 2019-09-26 18:44:35 +01:00
intel_context_types.h drm/i915: Remove logical HW ID 2019-10-04 15:39:30 +01:00
intel_context.c drm/i915/gt: Prefer local path to runtime powermanagement 2019-10-07 21:44:02 +01:00
intel_context.h drm/i915/gt: Mark context->active_count as protected by timeline->mutex 2019-08-16 18:02:06 +01:00
intel_engine_cs.c drm/i915/gt: Replace hangcheck by heartbeats 2019-10-23 23:52:10 +01:00
intel_engine_heartbeat.c drm/i915/gt: Replace hangcheck by heartbeats 2019-10-23 23:52:10 +01:00
intel_engine_heartbeat.h drm/i915/gt: Replace hangcheck by heartbeats 2019-10-23 23:52:10 +01:00
intel_engine_pm.c drm/i915/gt: Replace hangcheck by heartbeats 2019-10-23 23:52:10 +01:00
intel_engine_pm.h drm/i915: Defer final intel_wakeref_put to process context 2019-08-08 21:28:51 +01:00
intel_engine_pool_types.h drm/i915: Replace struct_mutex for batch pool serialisation 2019-08-04 14:31:18 +01:00
intel_engine_pool.c drm/i915: Coordinate i915_active with its own mutex 2019-10-04 15:39:12 +01:00
intel_engine_pool.h drm/i915: Mark i915_request.timeline as a volatile, rcu pointer 2019-09-20 10:24:09 +01:00
intel_engine_types.h drm/i915/gt: Replace hangcheck by heartbeats 2019-10-23 23:52:10 +01:00
intel_engine_user.c drm/i915: Make for_each_engine_masked work on intel_gt 2019-10-18 00:06:25 +01:00
intel_engine_user.h drm/i915: Rename engines to match their user interface 2019-08-07 14:30:55 +01:00
intel_engine.h drm/i915/gt: Replace hangcheck by heartbeats 2019-10-23 23:52:10 +01:00
intel_gpu_commands.h drm/i915/tgl: Add HDC Pipeline Flush 2019-10-15 18:15:59 +01:00
intel_gt_irq.c drm/i915: Extract general GT interrupt handlers 2019-08-12 15:36:13 +01:00
intel_gt_irq.h drm/i915: Extract general GT interrupt handlers 2019-08-12 15:36:13 +01:00
intel_gt_pm_irq.c drm/i915: Extract general GT interrupt handlers 2019-08-12 15:36:13 +01:00
intel_gt_pm_irq.h drm/i915: Extract GT powermanagement interrupt handling 2019-08-12 15:36:06 +01:00
intel_gt_pm.c drm/i915/gt: Replace hangcheck by heartbeats 2019-10-23 23:52:10 +01:00
intel_gt_pm.h drm/i915: Remove pm park/unpark notifications 2019-10-21 21:07:57 +01:00
intel_gt_requests.c drm/i915: Pass in intel_gt at some for_each_engine sites 2019-10-18 00:06:27 +01:00
intel_gt_requests.h drm/i915: Move request runtime management onto gt 2019-10-04 15:39:26 +01:00
intel_gt_types.h drm/i915/gt: Replace hangcheck by heartbeats 2019-10-23 23:52:10 +01:00
intel_gt.c drm/i915/gt: Replace hangcheck by heartbeats 2019-10-23 23:52:10 +01:00
intel_gt.h drm/i915/gt: Replace hangcheck by heartbeats 2019-10-23 23:52:10 +01:00
intel_llc_types.h drm/i915: Extract GT ring management 2019-10-20 20:45:18 +01:00
intel_llc.c drm/i915: Extract GT ring management 2019-10-20 20:45:18 +01:00
intel_llc.h drm/i915: Extract GT ring management 2019-10-20 20:45:18 +01:00
intel_lrc_reg.h drm/i915/selftests: Verify the LRC register layout between init and HW 2019-09-24 17:27:19 +01:00
intel_lrc.c drm/i915/execlists: Cancel banned contexts on schedule-out 2019-10-23 23:52:10 +01:00
intel_lrc.h drm/i915: Remove logical HW ID 2019-10-04 15:39:30 +01:00
intel_mocs.c drm/i915: Do initial mocs configuration directly 2019-10-16 19:35:37 +01:00
intel_mocs.h drm/i915: Do initial mocs configuration directly 2019-10-16 19:35:37 +01:00
intel_rc6_types.h drm/i915: Extract GT render sleep (rc6) management 2019-09-27 13:01:57 +01:00
intel_rc6.c drm/i915/gt: Convert the leftover for_each_engine(gt) 2019-10-18 14:53:48 +01:00
intel_rc6.h drm/i915: Extract GT render sleep (rc6) management 2019-09-27 13:01:57 +01:00
intel_renderstate.c drm/i915: Serialize against vma moves 2019-08-19 15:25:56 +01:00
intel_renderstate.h drm/i915: Move the renderstate setup under gt/ 2019-07-04 11:48:22 +01:00
intel_reset_types.h drm/i915: Define explicit wedged on init reset state 2019-09-26 18:44:35 +01:00
intel_reset.c drm/i915/gt: Replace hangcheck by heartbeats 2019-10-23 23:52:10 +01:00
intel_reset.h drm/i915: Pass intel_gt to has-reset? 2019-09-27 23:25:14 +01:00
intel_ringbuffer.c drm/i915/gt: Convert the leftover for_each_engine(gt) 2019-10-18 14:53:48 +01:00
intel_sseu.c drm/i915: Expand subslice mask 2019-08-23 19:14:27 +01:00
intel_sseu.h drm/i915/tgl: s/ss/eu fuse reading support 2019-09-21 08:31:08 +01:00
intel_timeline_types.h drm/i915: Coordinate i915_active with its own mutex 2019-10-04 15:39:12 +01:00
intel_timeline.c drm/i915: Coordinate i915_active with its own mutex 2019-10-04 15:39:12 +01:00
intel_timeline.h drm/i915/gt: Track timeline activeness in enter/exit 2019-08-15 23:16:05 +01:00
intel_workarounds_types.h drm/i915: Add engine name to workaround debug print 2019-07-12 09:55:30 +01:00
intel_workarounds.c drm/i915/tgl: Wa_1607030317, Wa_1607186500, Wa_1607297627 2019-10-15 18:25:45 +01:00
intel_workarounds.h drm/i915: Convert gt workarounds to intel_gt 2019-06-21 13:48:25 +01:00
Makefile drm/i915: use upstream version of header tests 2019-07-30 12:11:57 +03:00
mock_engine.c drm/i915/selftests: Add the mock engine to the gt->engine[] 2019-10-18 14:53:48 +01:00
mock_engine.h
selftest_context.c drm/i915: Pass in intel_gt at some for_each_engine sites 2019-10-18 00:06:27 +01:00
selftest_engine_cs.c drm/i915: Rename engines to match their user interface 2019-08-07 14:30:55 +01:00
selftest_engine_heartbeat.c drm/i915/gt: Replace hangcheck by heartbeats 2019-10-23 23:52:10 +01:00
selftest_engine_pm.c drm/i915: Pass in intel_gt at some for_each_engine sites 2019-10-18 00:06:27 +01:00
selftest_engine.c drm/i915: Defer final intel_wakeref_put to process context 2019-08-08 21:28:51 +01:00
selftest_engine.h drm/i915: Defer final intel_wakeref_put to process context 2019-08-08 21:28:51 +01:00
selftest_gt_pm.c drm/i915: Extract GT ring management 2019-10-20 20:45:18 +01:00
selftest_hangcheck.c drm/i915/selftests: Flush interrupts before disabling tasklets 2019-10-24 09:18:52 +01:00
selftest_llc.c drm/i915: Extract GT ring management 2019-10-20 20:45:18 +01:00
selftest_llc.h drm/i915: Extract GT ring management 2019-10-20 20:45:18 +01:00
selftest_lrc.c drm/i915/execlists: Cancel banned contexts on schedule-out 2019-10-23 23:52:10 +01:00
selftest_reset.c drm/i915/selftests: Flush interrupts before disabling tasklets 2019-10-24 09:18:52 +01:00
selftest_timeline.c drm/i915: Pass in intel_gt at some for_each_engine sites 2019-10-18 00:06:27 +01:00
selftest_workarounds.c drm/i915: Pass in intel_gt at some for_each_engine sites 2019-10-18 00:06:27 +01:00