Stephen Boyd 348c898cb8 Fix overflow in the mpll driver on 32bits arch ... -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEhTN4patJkYmDQpdpAVGjkwQWlNEFAlpGfZkACgkQAVGjkwQW lNHk5g/7Bn6ZOL0M4qd7jhrNw9pL41jQUu/f6RiWpOfeAO/99MiByFHbgFWE2K/b H8KpxgOIz5vQPRw9Moly8yfKXoxYgR0AjMgr6G1499dkrbOb7DF9Fe0mLp8wkrdL RiwiiqXBG3vwS1VNLgP5OZGX38CNSK2p16lEqL6/w4ePUDat1FxQKMQVUJER4dY+ 8kFm1EHrGrulge26ZiOsX5Nyl290xixWz4Zrjuuo/FUswHykaJNxA3C4itKCrFhS yD6eZNREQajSOrKY3wWEPxSwkME7KamES+bwzMF8VtC7Hf+H85dw4ZAGXGz0f+Iz LIDrdtdosDHIDI+EIlquDaN9A+0h281V3nfwBBXx+y3WOzhIzS0/sUDvaIQMVDk5 tXuVnkFCsC/ZmXOiUtXzfEezJgeWBXNXMK42+LILChPsDHeq4QbO8PG1tFVOIh+U 8PI+mkxTRRl4h360jcpvbs151sP1Q2+xx3fP797lKz4yBPkDMxrZpPfc09R3/hi9 FSDnPOGkgC3GMGQJzW2xnccDLeNqgBvQxXz5/yFcd1MxriDUb1HD8T1C/ctaiLje GJPy/+Avhgfk08xwWLLW8hUxZesXFQblKk/XvVcuF2FMPovizvng3Q5T62m2eEZa BzExUnBlEd6cyvMLHLW4BnRpAyv7lO5aCEwyLegSx1oyNhE543I= =p22g -----END PGP SIGNATURE----- Merge tag 'meson-clk-for-v4.16-3' of git://github.com/BayLibre/clk-meson into clk-meson Pull Amlogic clk driver update from Jerome Brunet: - Fix overflow in the mpll driver on 32bits arch * tag 'meson-clk-for-v4.16-3' of git://github.com/BayLibre/clk-meson: clk: meson: mpll: use 64-bit maths in params_from_rate		2018-01-02 17:51:29 -08:00
..
axg.c	clk: meson-axg: make local symbol axg_gp0_params_table static	2017-12-28 10:42:07 -08:00
axg.h	clk: meson-axg: add clock controller drivers	2017-12-14 10:19:37 +01:00
clk-audio-divider.c	clk: meson: add audio clock divider support	2017-04-07 16:50:44 +02:00
clk-cpu.c	clk: meson8b: clean up cpu clocks	2016-06-22 18:02:35 -07:00
clk-mpll.c	clk: meson: mpll: use 64-bit maths in params_from_rate	2017-12-23 23:14:20 +01:00
clk-pll.c	clk: meson: Add support for parameters for specific PLLs	2017-04-04 12:05:12 -07:00
clkc.h	clk: meson: make the spinlock naming more specific	2017-12-14 10:12:41 +01:00
gxbb-aoclk-32k.c	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
gxbb-aoclk-regmap.c	clk: meson: gxbb-aoclk: Switch to regmap for register access	2017-08-04 18:02:01 +02:00
gxbb-aoclk.c	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
gxbb-aoclk.h	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
gxbb.c	clk: meson: make the spinlock naming more specific	2017-12-14 10:12:41 +01:00
gxbb.h	clk: meson: gxbb: Add VPU and VAPB clockids	2017-10-20 10:24:30 +02:00
Kconfig	clk: meson-axg: add clock controller drivers	2017-12-14 10:19:37 +01:00
Makefile	clk: meson-axg: add clock controller drivers	2017-12-14 10:19:37 +01:00
meson8b.c	clk: meson: make the spinlock naming more specific	2017-12-14 10:12:41 +01:00
meson8b.h	clk: meson: meson8b: register the built-in reset controller	2017-08-04 18:01:58 +02:00