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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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clk: meson: gxbb-aoclk: Switch to regmap for register access
Switch the aoclk driver to use the new bindings and switch all the registers access to regmap only. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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3b3025625f
commit
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@ -4,4 +4,4 @@
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obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o
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46
drivers/clk/meson/gxbb-aoclk-regmap.c
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46
drivers/clk/meson/gxbb-aoclk-regmap.c
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@ -0,0 +1,46 @@
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/*
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* Copyright (c) 2017 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/clk-provider.h>
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#include <linux/bitfield.h>
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#include <linux/regmap.h>
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#include "gxbb-aoclk.h"
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static int aoclk_gate_regmap_enable(struct clk_hw *hw)
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{
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struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw);
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return regmap_update_bits(gate->regmap, AO_RTI_GEN_CNTL_REG0,
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BIT(gate->bit_idx), BIT(gate->bit_idx));
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}
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static void aoclk_gate_regmap_disable(struct clk_hw *hw)
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{
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struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw);
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regmap_update_bits(gate->regmap, AO_RTI_GEN_CNTL_REG0,
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BIT(gate->bit_idx), 0);
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}
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static int aoclk_gate_regmap_is_enabled(struct clk_hw *hw)
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{
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struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw);
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unsigned int val;
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int ret;
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ret = regmap_read(gate->regmap, AO_RTI_GEN_CNTL_REG0, &val);
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if (ret)
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return ret;
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return (val & BIT(gate->bit_idx)) != 0;
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}
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const struct clk_ops meson_aoclk_gate_regmap_ops = {
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.enable = aoclk_gate_regmap_enable,
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.disable = aoclk_gate_regmap_disable,
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.is_enabled = aoclk_gate_regmap_is_enabled,
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};
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@ -56,16 +56,19 @@
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/init.h>
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#include <dt-bindings/clock/gxbb-aoclkc.h>
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#include <dt-bindings/reset/gxbb-aoclkc.h>
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#include "gxbb-aoclk.h"
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static DEFINE_SPINLOCK(gxbb_aoclk_lock);
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struct gxbb_aoclk_reset_controller {
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struct reset_controller_dev reset;
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unsigned int *data;
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void __iomem *base;
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struct regmap *regmap;
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};
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static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
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@ -74,9 +77,8 @@ static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
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struct gxbb_aoclk_reset_controller *reset =
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container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
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writel(BIT(reset->data[id]), reset->base);
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return 0;
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return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
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BIT(reset->data[id]));
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}
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static const struct reset_control_ops gxbb_aoclk_reset_ops = {
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@ -84,13 +86,12 @@ static const struct reset_control_ops gxbb_aoclk_reset_ops = {
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};
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#define GXBB_AO_GATE(_name, _bit) \
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static struct clk_gate _name##_ao = { \
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.reg = (void __iomem *)0, \
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static struct aoclk_gate_regmap _name##_ao = { \
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.bit_idx = (_bit), \
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.lock = &gxbb_aoclk_lock, \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name "_ao", \
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.ops = &clk_gate_ops, \
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.ops = &meson_aoclk_gate_regmap_ops, \
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.parent_names = (const char *[]){ "clk81" }, \
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.num_parents = 1, \
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.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
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@ -113,7 +114,7 @@ static unsigned int gxbb_aoclk_reset[] = {
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[RESET_AO_IR_BLASTER] = 23,
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};
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static struct clk_gate *gxbb_aoclk_gate[] = {
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static struct aoclk_gate_regmap *gxbb_aoclk_gate[] = {
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[CLKID_AO_REMOTE] = &remote_ao,
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[CLKID_AO_I2C_MASTER] = &i2c_master_ao,
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[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao,
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@ -136,24 +137,23 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
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static int gxbb_aoclkc_probe(struct platform_device *pdev)
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{
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struct resource *res;
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void __iomem *base;
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int ret, clkid;
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struct device *dev = &pdev->dev;
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struct gxbb_aoclk_reset_controller *rstc;
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struct device *dev = &pdev->dev;
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struct regmap *regmap;
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int ret, clkid;
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rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
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if (!rstc)
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return -ENOMEM;
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/* Generic clocks */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
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if (IS_ERR(regmap)) {
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dev_err(dev, "failed to get regmap\n");
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return -ENODEV;
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}
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/* Reset Controller */
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rstc->base = base;
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rstc->regmap = regmap;
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rstc->data = gxbb_aoclk_reset;
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rstc->reset.ops = &gxbb_aoclk_reset_ops;
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rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
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@ -161,10 +161,10 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
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ret = devm_reset_controller_register(dev, &rstc->reset);
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/*
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* Populate base address and register all clks
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* Populate regmap and register all clks
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*/
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for (clkid = 0; clkid < gxbb_aoclk_onecell_data.num; clkid++) {
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gxbb_aoclk_gate[clkid]->reg = base;
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for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
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gxbb_aoclk_gate[clkid]->regmap = regmap;
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ret = devm_clk_hw_register(dev,
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gxbb_aoclk_onecell_data.hws[clkid]);
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@ -177,7 +177,7 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
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}
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static const struct of_device_id gxbb_aoclkc_match_table[] = {
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{ .compatible = "amlogic,gxbb-aoclkc" },
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{ .compatible = "amlogic,meson-gx-aoclkc" },
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{ }
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};
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26
drivers/clk/meson/gxbb-aoclk.h
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26
drivers/clk/meson/gxbb-aoclk.h
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@ -0,0 +1,26 @@
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/*
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* Copyright (c) 2017 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __GXBB_AOCLKC_H
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#define __GXBB_AOCLKC_H
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/* AO Configuration Clock registers offsets */
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#define AO_RTI_GEN_CNTL_REG0 0x40
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struct aoclk_gate_regmap {
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struct clk_hw hw;
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unsigned bit_idx;
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struct regmap *regmap;
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spinlock_t *lock;
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};
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#define to_aoclk_gate_regmap(_hw) \
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container_of(_hw, struct aoclk_gate_regmap, hw)
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extern const struct clk_ops meson_aoclk_gate_regmap_ops;
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#endif /* __GXBB_AOCLKC_H */
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