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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 16:20:55 +07:00
clk: meson8b: clean up cpu clocks
Remove the cpu clock registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. Ninja rename a5_clk to cpu_clk to better align with cpufreq convention. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
This commit is contained in:
Michael Turquette
parent
6282a2da09
commit
55d42c40dd
@ -51,13 +51,6 @@
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#include "clkc.h"
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struct meson_clk_cpu {
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struct notifier_block clk_nb;
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const struct clk_div_table *div_table;
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struct clk_hw hw;
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void __iomem *base;
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u16 reg_off;
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};
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#define to_meson_clk_cpu_hw(_hw) container_of(_hw, struct meson_clk_cpu, hw)
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#define to_meson_clk_cpu_nb(_nb) container_of(_nb, struct meson_clk_cpu, clk_nb)
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@ -119,6 +112,7 @@ static unsigned long meson_clk_cpu_recalc_rate(struct clk_hw *hw,
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return parent_rate / div;
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}
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/* FIXME MUX1 & MUX2 should be struct clk_hw objects */
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static int meson_clk_cpu_pre_rate_change(struct meson_clk_cpu *clk_cpu,
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struct clk_notifier_data *ndata)
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{
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@ -140,6 +134,7 @@ static int meson_clk_cpu_pre_rate_change(struct meson_clk_cpu *clk_cpu,
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return 0;
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}
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/* FIXME MUX1 & MUX2 should be struct clk_hw objects */
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static int meson_clk_cpu_post_rate_change(struct meson_clk_cpu *clk_cpu,
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struct clk_notifier_data *ndata)
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{
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@ -161,7 +156,7 @@ static int meson_clk_cpu_post_rate_change(struct meson_clk_cpu *clk_cpu,
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* PLL clock is to be changed. We use the xtal input as temporary parent
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* while the PLL frequency is stabilized.
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*/
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static int meson_clk_cpu_notifier_cb(struct notifier_block *nb,
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int meson_clk_cpu_notifier_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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@ -176,68 +171,8 @@ static int meson_clk_cpu_notifier_cb(struct notifier_block *nb,
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return notifier_from_errno(ret);
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}
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static const struct clk_ops meson_clk_cpu_ops = {
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const struct clk_ops meson_clk_cpu_ops = {
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.recalc_rate = meson_clk_cpu_recalc_rate,
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.round_rate = meson_clk_cpu_round_rate,
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.set_rate = meson_clk_cpu_set_rate,
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};
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struct clk *meson_clk_register_cpu(const struct clk_conf *clk_conf,
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void __iomem *reg_base,
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spinlock_t *lock)
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{
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struct clk *clk;
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struct clk *pclk;
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struct meson_clk_cpu *clk_cpu;
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struct clk_init_data init;
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int ret;
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clk_cpu = kzalloc(sizeof(*clk_cpu), GFP_KERNEL);
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if (!clk_cpu)
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return ERR_PTR(-ENOMEM);
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clk_cpu->base = reg_base;
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clk_cpu->reg_off = clk_conf->reg_off;
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clk_cpu->div_table = clk_conf->conf.div_table;
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clk_cpu->clk_nb.notifier_call = meson_clk_cpu_notifier_cb;
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init.name = clk_conf->clk_name;
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init.ops = &meson_clk_cpu_ops;
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init.flags = clk_conf->flags | CLK_GET_RATE_NOCACHE;
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init.flags |= CLK_SET_RATE_PARENT;
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init.parent_names = clk_conf->clks_parent;
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init.num_parents = 1;
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clk_cpu->hw.init = &init;
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pclk = __clk_lookup(clk_conf->clks_parent[0]);
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if (!pclk) {
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pr_err("%s: could not lookup parent clock %s\n",
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__func__, clk_conf->clks_parent[0]);
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ret = -EINVAL;
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goto free_clk;
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}
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ret = clk_notifier_register(pclk, &clk_cpu->clk_nb);
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if (ret) {
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pr_err("%s: failed to register clock notifier for %s\n",
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__func__, clk_conf->clk_name);
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goto free_clk;
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}
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clk = clk_register(NULL, &clk_cpu->hw);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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goto unregister_clk_nb;
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}
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return clk;
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unregister_clk_nb:
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clk_notifier_unregister(pclk, &clk_cpu->clk_nb);
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free_clk:
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kfree(clk_cpu);
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return ERR_PTR(ret);
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}
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@ -140,10 +140,6 @@ void __init meson_clk_register_clks(const struct clk_conf *clk_confs,
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clk = meson_clk_register_composite(clk_conf,
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clk_base);
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break;
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case CLK_CPU:
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clk = meson_clk_register_cpu(clk_conf, clk_base,
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&clk_lock);
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break;
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default:
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clk = NULL;
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}
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@ -69,6 +69,14 @@ struct meson_clk_pll {
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#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw)
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struct meson_clk_cpu {
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struct clk_hw hw;
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void __iomem *base;
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u16 reg_off;
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struct notifier_block clk_nb;
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const struct clk_div_table *div_table;
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};
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struct composite_conf {
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struct parm mux_parm;
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struct parm div_parm;
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@ -84,7 +92,6 @@ struct composite_conf {
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enum clk_type {
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CLK_COMPOSITE,
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CLK_CPU,
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};
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struct clk_conf {
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@ -101,17 +108,6 @@ struct clk_conf {
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} conf;
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};
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#define CPU(_ro, _ci, _cn, _cp, _dt) \
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{ \
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.reg_off = (_ro), \
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.clk_type = CLK_CPU, \
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.clk_id = (_ci), \
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.clk_name = (_cn), \
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.clks_parent = (_cp), \
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.num_parents = ARRAY_SIZE(_cp), \
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.conf.div_table = (_dt), \
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} \
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#define COMPOSITE(_ro, _ci, _cn, _cp, _f, _c) \
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{ \
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.reg_off = (_ro), \
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@ -127,8 +123,8 @@ struct clk_conf {
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struct clk **meson_clk_init(struct device_node *np, unsigned long nr_clks);
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void meson_clk_register_clks(const struct clk_conf *clk_confs,
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unsigned int nr_confs, void __iomem *clk_base);
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struct clk *meson_clk_register_cpu(const struct clk_conf *clk_conf,
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void __iomem *reg_base, spinlock_t *lock);
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int meson_clk_cpu_notifier_cb(struct notifier_block *nb, unsigned long event,
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void *data);
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/* shared data */
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extern spinlock_t clk_lock;
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@ -136,5 +132,6 @@ extern spinlock_t clk_lock;
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/* clk_ops */
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extern const struct clk_ops meson_clk_pll_ro_ops;
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extern const struct clk_ops meson_clk_pll_ops;
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extern const struct clk_ops meson_clk_cpu_ops;
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#endif /* __CLKC_H */
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@ -15,6 +15,7 @@
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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@ -110,7 +111,6 @@ static const struct clk_div_table cpu_div_table[] = {
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{ /* sentinel */ },
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};
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PNAME(p_cpu_clk) = { "sys_pll" };
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PNAME(p_clk81) = { "fclk_div3", "fclk_div4", "fclk_div5" };
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PNAME(p_mali) = { "fclk_div3", "fclk_div4", "fclk_div5",
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"fclk_div7", "zero" };
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@ -286,9 +286,19 @@ static struct clk_fixed_factor meson8b_fclk_div7 = {
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},
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};
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static struct meson_clk_cpu meson8b_cpu_clk = {
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.reg_off = MESON8B_REG_SYS_CPU_CNTL1,
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.div_table = cpu_div_table,
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.clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk",
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.ops = &meson_clk_cpu_ops,
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.parent_names = (const char *[]){ "sys_pll" },
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.num_parents = 1,
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},
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};
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static const struct clk_conf meson8b_clk_confs[] __initconst = {
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CPU(MESON8B_REG_SYS_CPU_CNTL1, CLKID_CPUCLK, "a5_clk", p_cpu_clk,
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cpu_div_table),
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COMPOSITE(MESON8B_REG_HHI_MPEG, CLKID_CLK81, "clk81", p_clk81,
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CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED, &clk81_conf),
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COMPOSITE(MESON8B_REG_MALI, CLKID_MALI, "mali", p_mali,
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@ -314,6 +324,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
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[CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
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[CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
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[CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
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[CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
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},
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.num = CLK_NR_CLKS,
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};
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@ -328,6 +339,8 @@ static void __init meson8b_clkc_init(struct device_node *np)
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{
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void __iomem *clk_base;
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int ret, clkid, i;
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struct clk_hw *parent_hw;
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struct clk *parent_clk;
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if (!meson_clk_init(np, CLK_NR_CLKS))
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return;
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@ -343,6 +356,9 @@ static void __init meson8b_clkc_init(struct device_node *np)
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for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
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meson8b_clk_plls[i]->base = clk_base;
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/* Populate the base address for CPU clk */
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meson8b_cpu_clk.base = clk_base;
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/*
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* register all clks
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* CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
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@ -358,12 +374,37 @@ static void __init meson8b_clkc_init(struct device_node *np)
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goto unregister;
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}
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/*
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* Register CPU clk notifier
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*
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* FIXME this is wrong for a lot of reasons. First, the muxes should be
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* struct clk_hw objects. Second, we shouldn't program the muxes in
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* notifier handlers. The tricky programming sequence will be handled
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* by the forthcoming coordinated clock rates mechanism once that
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* feature is released.
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*
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* Furthermore, looking up the parent this way is terrible. At some
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* point we will stop allocating a default struct clk when registering
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* a new clk_hw, and this hack will no longer work. Releasing the ccr
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* feature before that time solves the problem :-)
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*/
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parent_hw = clk_hw_get_parent(&meson8b_cpu_clk.hw);
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parent_clk = parent_hw->clk;
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ret = clk_notifier_register(parent_clk, &meson8b_cpu_clk.clk_nb);
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if (ret) {
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pr_err("%s: failed to register clock notifier for cpu_clk\n",
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__func__);
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goto unregister_clk_nb;
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}
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meson_clk_register_clks(meson8b_clk_confs,
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ARRAY_SIZE(meson8b_clk_confs),
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clk_base);
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return;
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/* FIXME remove after converting to platform_driver/devm_clk_register */
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unregister_clk_nb:
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clk_notifier_unregister(parent_clk, &meson8b_a5_clk.clk_nb);
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unregister:
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for (clkid = CLK_NR_CLKS - 1; clkid >= 0; clkid--)
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clk_hw_unregister(meson8b_hw_onecell_data.hws[clkid]);
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