Jun Lei 1621f4c417 drm/amd/display: always use 4 dp lanes for dml ... [why] current DML logic uses currently trained setting for number of dp lanes in DML calculations. this is obviously flawed since just because 1 lane is in use doesn't mean only 1 lane can be used this causes mode validation to fail depending on current state, which is incorrect [how] DML should always assume 4 lanes are available. validation of bandwidth is not supposed to be handled by DML, since we do link validation without DML already also, DML is expecting there to be a copy of the max state, this state is removed when update_bounding_box is called to update actual SKU clocks. fix this as well by duping last state. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Eric Yang <eric.yang2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-06-22 09:34:12 -05:00
..
amdgpu_dm	drm/amd/display: Add power down display on boot flag	2019-06-22 09:34:10 -05:00
dc	drm/amd/display: always use 4 dp lanes for dml	2019-06-22 09:34:12 -05:00
include	drm/amd/display: add dsc_passthrough_support bit in dpcd struct	2019-06-22 09:34:12 -05:00
modules	drm/amd/display: Integrate color transform3x4 with 3dlut tm	2019-06-22 09:34:12 -05:00
Kconfig	drm/amd/display: enable DSC support by default	2019-06-22 09:34:08 -05:00
Makefile	drm/amd/display: move clk_mgr files to right place	2019-05-31 10:39:31 -05:00
TODO