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1621f4c417
[why] current DML logic uses currently trained setting for number of dp lanes in DML calculations. this is obviously flawed since just because 1 lane is in use doesn't mean only 1 lane can be used this causes mode validation to fail depending on current state, which is incorrect [how] DML should always assume 4 lanes are available. validation of bandwidth is not supposed to be handled by DML, since we do link validation without DML already also, DML is expecting there to be a copy of the max state, this state is removed when update_bounding_box is called to update actual SKU clocks. fix this as well by duping last state. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Eric Yang <eric.yang2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
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