Commit Graph

810637 Commits

Author SHA1 Message Date
Paul Burton
f6cab793d4
MIPS: Remove custom MIPS32 __kernel_fsid_t type
For MIPS32 kernels we have a custom definition of __kernel_fsid_t. This
differs from the asm-generic version used by all other architectures &
MIPS64 in one way - it declares the val field as an array of long,
rather than an array of int. Since int & long have identical size &
alignment when targeting MIPS32 anyway, this makes little sense.

Beyond the pointlessness this causes problems for code which prints
entries from the val array, for example the fanotify_encode_fid()
function [1]. If such code uses a format specified suited to an int then
it encounters compiler warnings when building for MIPS32, such as:

  In file included from include/linux/kernel.h:14:0,
                   from include/linux/list.h:9,
                   from include/linux/preempt.h:11,
                   from include/linux/spinlock.h:51,
                   from include/linux/fdtable.h:11,
                   from fs/notify/fanotify/fanotify.c:3:
  fs/notify/fanotify/fanotify.c: In function 'fanotify_encode_fid':
  include/linux/kern_levels.h:5:18: warning: format '%x' expects argument
    of type 'unsigned int', but argument 2 has type 'long int' [-Wformat=]

Remove the custom __kernel_fsid_t definition & make use of the
asm-generic version which will have an identical layout in memory
anyway, in order to remove the inconsistency with other architectures.

One possible regression this could cause if is any code is attempting to
print entries from the val array with a long-sized format specifier, in
which case it would begin seeing compiler warnings when built against
kernel headers including this change. Since such code is exceedingly
rare, and would have to be MIPS32-specific to expect a long, this seems
to be a problem that it's extremely unlikely anyone will encounter.

[1] https://lore.kernel.org/linux-mips/CAOQ4uxiEkczB7PNCXegFC-eYb9zAGaio_o=OgHAJHFd7eavBxA@mail.gmail.com/T/#mb43103277c79ef06b884359209e817db1c136140

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Amir Goldstein <amir73il@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jan Kara <jack@suse.cz>
Cc: linux-arch@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
2019-03-14 11:31:20 -07:00
Petr Štetiar
cdb8faa00e
mips: bcm47xx: Enable USB power on Netgear WNDR3400v2
Eric has reported on OpenWrt's bug tracking system[1], that he's not
able to use USB devices on his WNDR3400v2 device after the boot, until
he turns on GPIO #21 manually through sysfs.

1. https://bugs.openwrt.org/index.php?do=details&task_id=2170

Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Reported-by: Eric Bohlman <ericbohlman@gmail.com>
Tested-by: Eric Bohlman <ericbohlman@gmail.com>
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Signed-off-by: Paul Burton <paul.burton@mips.com>
2019-03-11 15:34:17 -07:00
Archer Yan
47c25036b6
MIPS: Fix kernel crash for R6 in jump label branch function
Insert Branch instruction instead of NOP to make sure assembler don't
patch code in forbidden slot. In jump label function, it might
be possible to patch Control Transfer Instructions(CTIs) into
forbidden slot, which will generate Reserved Instruction exception
in MIPS release 6.

Signed-off-by: Archer Yan <ayan@wavecomp.com>
Reviewed-by: Paul Burton <paul.burton@mips.com>
[paul.burton@mips.com:
  - Add MIPS prefix to subject.
  - Mark for stable from v4.0, which introduced r6 support, onwards.]
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: stable@vger.kernel.org # v4.0+
2019-03-11 11:11:11 -07:00
Yasha Cherikovsky
3f0a53bc64
MIPS: Ensure ELF appended dtb is relocated
This fixes booting with the combination of CONFIG_RELOCATABLE=y
and CONFIG_MIPS_ELF_APPENDED_DTB=y.

Sections that appear after the relocation table are not relocated
on system boot (except .bss, which has special handling).

With CONFIG_MIPS_ELF_APPENDED_DTB, the dtb is part of the
vmlinux ELF, so it must be relocated together with everything else.

Fixes: 069fd76627 ("MIPS: Reserve space for relocation table")
Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: stable@vger.kernel.org # v4.7+
2019-03-11 11:08:31 -07:00
Yifeng Li
5f5f67da97
mips: loongson64: lemote-2f: Add IRQF_NO_SUSPEND to "cascade" irqaction.
Timekeeping IRQs from CS5536 MFGPT are routed to i8259, which then
triggers the "cascade" IRQ on MIPS CPU. Without IRQF_NO_SUSPEND in
cascade_irqaction, MFGPT interrupts will be masked in suspend mode,
and the machine would be unable to resume once suspended.

Previously, MIPS IRQs were not disabled properly, so the original
code appeared to work. Commit a3e6c1eff5 ("MIPS: IRQ: Fix disable_irq on
CPU IRQs") uncovers the bug. To fix it, add IRQF_NO_SUSPEND to
cascade_irqaction.

This commit is functionally identical to 0add9c2f1c ("MIPS:
Loongson-3: Add IRQF_NO_SUSPEND to Cascade irqaction"), but it forgot
to apply the same fix to Loongson2.

Signed-off-by: Yifeng Li <tomli@tomli.me>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-kernel@vger.kernel.org
Cc: stable@vger.kernel.org # v3.19+
2019-03-11 11:07:12 -07:00
Hauke Mehrtens
aeb669d41f
MIPS: lantiq: Remove separate GPHY Firmware loader
The separate GPHY Firmware loader driver is not used any more, the GPHY
firmware is now loaded by the GSWIP switch driver which also makes use
of the GPHY.
Remove the old unused GPHY firmware loader driver.

The GPHY firmware is useless without an Ethernet and switch driver, it
should not harm if loading this does not work for system using an old
device tree.
I am not aware of any vendor separating the device tree from the kernel
binary, it should be ok to remove this.

The code and the functionality form this separate GPHY firmware loader
was added to the gswip driver in commit 14fceff477 ("net: dsa: Add
Lantiq / Intel DSA driver for vrx200")

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: john@phrozen.org
Cc: netdev@vger.kernel.org
2019-02-25 14:17:10 -08:00
Paul Cercueil
15205fc054
MIPS: ingenic: Add support for appended devicetree
Add support for booting the kernel from an externally-appended
devicetree, if no devicetree was built-in.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
2019-02-21 15:55:41 -08:00
Thomas Bogendoerfer
69a07a41d9
MIPS: SGI-IP27: rework HUB interrupts
This commit rearranges the HUB interrupt code by using MIPS_IRQ_CPU
interrupt handling code and modern Linux IRQ framework features to get
rid of global arrays. It also adds support for irq affinity setting.

Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
2019-02-19 12:46:03 -08:00
Thomas Bogendoerfer
2c86562047
MIPS: SGI-IP27: do boot CPU init later
To make use of per_cpu variables in interrupt code per_cpu_init() must
be done after setup_per_cpu_areas(). This is achieved by calling it
in smp_prepare_boot_cpu() via a new smp_ops method.

Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
2019-02-19 12:46:03 -08:00
Thomas Bogendoerfer
9707b7e639
MIPS: SGI-IP27: do xtalk scanning later
Move xtalk scanning to a later boot stage to be able using things like
kmalloc and friends.

Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
2019-02-19 12:46:02 -08:00
Thomas Bogendoerfer
ab68280ec2
MIPS: SGI-IP27: use pr_info/pr_emerg and pr_cont to fix output
Topology and NMI output needs pr_cont() to look the way it was in the
old days of printk.

Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
2019-02-19 12:46:02 -08:00
Thomas Bogendoerfer
a44d924c81
MIPS: SGI-IP27: clean up bridge access and header files
Introduced bridge_read/bridge_write/bridge_set/bridge_clr for accessing
bridge register and get rid of volatile declarations. Also removed
all typedefs from arch/mips/include/asm/pci/bridge.h and cleaned up
language in arch/mips/pci/ops-bridge.c

Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
2019-02-19 12:46:02 -08:00
Thomas Bogendoerfer
db0e7d4e42
MIPS: SGI-IP27: get rid of volatile and hubreg_t
Replace hub register access with __raw_readq/__raw_writeq and get
rid of hubreg_t completely. Also remove no longer (probably never
used) used defines

Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
2019-02-19 12:46:02 -08:00
Liu Xiang
72faa7a773
MIPS: irq: Allocate accurate order pages for irq stack
The irq_pages is the number of pages for irq stack, but not the
order which is needed by __get_free_pages().
We can use get_order() to calculate the accurate order.

Signed-off-by: Liu Xiang <liu.xiang6@zte.com.cn>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Fixes: fe8bd18ffe ("MIPS: Introduce irq_stack")
Cc: linux-mips@vger.kernel.org
Cc: stable@vger.kernel.org # v4.11+
2019-02-19 12:45:01 -08:00
Paul Burton
d411da06ab
MIPS: dma-noncoherent: Remove bogus condition in dma_sync_phys()
Commit e36863a550 ("MIPS: HIGHMEM DMA on noncoherent MIPS32
processors") introduced code which:

  1) Calculates an offset within a page, by ANDing an address
     with ~PAGE_MASK.

  2) Checks whether that offset is >= PAGE_SIZE.

This check can never evaluate true, making the code it guards
unreachable. smatch spots bogus arithmetic resulting from the
impossible condition, resulting in the following warning:

  arch/mips/mm/dma-noncoherent.c:125
    dma_sync_phys() warn: mask and shift to zero

Fix this by removing the impossible to satisfy condition & the
unreachable code it guards.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Christoph Hellwig <hch@lst.de>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Robin Murphy <robin.murphy@arm.com>
2019-02-19 12:17:43 -08:00
Paul Burton
66b6572a14
MIPS: eBPF: Remove REG_32BIT_ZERO_EX
REG_32BIT_ZERO_EX and REG_64BIT are always handled in exactly the same
way, and reg_val_propagate_range() never actually sets any register to
type REG_32BIT_ZERO_EX.

Remove the redundant & unused REG_32BIT_ZERO_EX.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Daniel Borkmann <daniel@iogearbox.net>
Cc: Martin KaFai Lau <kafai@fb.com>
Cc: Song Liu <songliubraving@fb.com>
Cc: Yonghong Song <yhs@fb.com>
Cc: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Jiong Wang <jiong.wang@netronome.com>
2019-02-19 12:17:41 -08:00
Paul Burton
bdc18902ea
MIPS: eBPF: Always return sign extended 32b values
The function prototype used to call JITed eBPF code (ie. the type of the
struct bpf_prog bpf_func field) returns an unsigned int. The MIPS n64
ABI that MIPS64 kernels target defines that 32 bit integers should
always be sign extended when passed in registers as either arguments or
return values.

This means that when returning any value which may not already be sign
extended (ie. of type REG_64BIT or REG_32BIT_ZERO_EX) we need to perform
that sign extension in order to comply with the n64 ABI. Without this we
see strange looking test failures from test_bpf.ko, such as:

  test_bpf: #65 ALU64_MOV_X:
    dst = 4294967295 jited:1 ret -1 != -1 FAIL (1 times)

Although the return value printed matches the expected value, this is
only because printf is only examining the least significant 32 bits of
the 64 bit register value we returned. The register holding the expected
value is sign extended whilst the v0 register was set to a zero extended
value by our JITed code, so when compared by a conditional branch
instruction the values are not equal.

We already handle this when the return value register is of type
REG_32BIT_ZERO_EX, so simply extend this to also cover REG_64BIT.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Fixes: b6bd53f9c4 ("MIPS: Add missing file for eBPF JIT.")
Cc: stable@vger.kernel.org # v4.13+
Cc: linux-mips@vger.kernel.org
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Daniel Borkmann <daniel@iogearbox.net>
Cc: Martin KaFai Lau <kafai@fb.com>
Cc: Song Liu <songliubraving@fb.com>
Cc: Yonghong Song <yhs@fb.com>
Cc: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Jiong Wang <jiong.wang@netronome.com>
2019-02-19 12:17:28 -08:00
Paul Burton
462fb81b26
MIPS: CM: Fix indentation
mips_cm_error_report() contains a function call that's incorrectly
indented a level further than it ought to be. Remove a tab from the
start of both affected lines.

Signed-off-by: Paul Burton <paul.burton@mips.com>
2019-02-15 14:22:44 -08:00
Rafał Miłecki
63f7541ce5
MIPS: BCM47XX: Fix/improve Buffalo WHR-G54S support
1) Fix reset button support which is active *high*
2) Specify LEDs colors

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
2019-02-11 13:29:33 -08:00
Aaro Koskinen
3d2521810e
MIPS: OCTEON: program rx/tx-delay always from DT
Program rx/tx-delay always from DT.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-07 15:22:38 -08:00
Aaro Koskinen
1836c2b246
MIPS: OCTEON: delete board-specific link status
Delete board-specific link status. This info should now come from
the DT only.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-07 15:22:35 -08:00
Aaro Koskinen
154ca3f74f
MIPS: OCTEON: don't lie about interface type of CN3005 board
The fixed-link node in the DT should now take care of the link status,
so this hack can be deleted.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-07 15:22:34 -08:00
Aaro Koskinen
2c0756d306
MIPS: OCTEON: warn if deprecated link status is being used
Warn if deprecated link status is being used.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-07 15:22:32 -08:00
Aaro Koskinen
565485b8b5
MIPS: OCTEON: add fixed-link nodes to in-kernel device tree
Currently OCTEON ethernet falls back to phyless operation on
boards where we have no known PHY address or a fixed-link node.
Add fixed-link support for boards that need it, so we can clean up
the platform code and ethernet driver from some legacy code.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-07 15:22:30 -08:00
Paul Burton
3315b6b336
MIPS: Delete unused flush_cache_sigtramp()
Commit adcc81f148 ("MIPS: math-emu: Write-protect delay slot emulation
pages") left flush_cache_sigtramp() unused. Delete the dead code.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: linux-mips@vger.kernel.org
2019-02-07 12:59:45 -08:00
Paul Burton
c7e2d71dda
MIPS: Fix set_pte() for Netlogic XLR using cmpxchg64()
Commit 46011e6ea3 ("MIPS: Make set_pte() SMP safe.") introduced an
open-coded version of cmpxchg() within set_pte(), that always operated
on a value the size of an unsigned long. That is, it used ll/sc
instructions when CONFIG_32BIT=y or lld/scd instructions when
CONFIG_64BIT=y.

This was broken for configurations in which pte_t is larger than an
unsigned long (with the exception of XPA configurations which have a
different implementation of set_pte()), because we no longer update the
whole PTE. Indeed commit 46011e6ea3 ("MIPS: Make set_pte() SMP safe.")
notes:

> The case of CONFIG_64BIT_PHYS_ADDR && CONFIG_CPU_MIPS32 is *not*
> handled.

In practice this affects Netlogic XLR/XLS systems including
nlm_xlr_defconfig.

Commit 82f4f66ddf ("MIPS: Remove open-coded cmpxchg() in set_pte()")
then replaced this open-coded version of cmpxchg() with an actual call
to cmpxchg(). Unfortunately the configurations mentioned above then fail
to build because cmpxchg() can only operate on values 32 bits or smaller
in size, resulting in:

  arch/mips/include/asm/cmpxchg.h:166:11: error:
    call to '__cmpxchg_called_with_bad_pointer' declared with
    attribute error: Bad argument size for cmpxchg

One option that would fix the build failure & restore the previous
behaviour would be to cast the pte pointer to a pointer to unsigned
long, so that cmpxchg() would operate on just 32 bits of the PTE as it
has been since commit 46011e6ea3 ("MIPS: Make set_pte() SMP safe.").
That feels like an ugly hack though, and the behaviour of set_pte() is
likely a little broken.

Instead we take advantage of the fact that the affected configurations
already know at compile time that the CPU will support 64 bits (ie. have
hardcoded cpu_has_64bits in cpu-feature-overrides.h) in order to allow
cmpxchg64() to be used in these configurations. set_pte() then makes use
of cmpxchg64() when necessary.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Fixes: 46011e6ea3 ("MIPS: Make set_pte() SMP safe.")
Fixes: 82f4f66ddf ("MIPS: Remove open-coded cmpxchg() in set_pte()")
2019-02-06 14:59:24 -08:00
Paul Burton
6782f26c0d
MIPS: Export mm switching functions used by KVM
KVM makes use of check_switch_mmu_context(), check_mmu_context() &
get_new_mmu_context() which are no longer static inline functions in a
header. As such they need to be exported for KVM to successfully build
as a module, which was previously overlooked. Add the missing exports.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Fixes: 4ebea49ce2 ("MIPS: mm: Un-inline get_new_mmu_context")
Fixes: 42d5b84657 ("MIPS: mm: Unify ASID version checks")
2019-02-05 11:44:44 -08:00
Paul Burton
62c2766cf6
MIPS: Loongson32: Remove DMA & NAND devices from ls1b/board.c
Commit 7b3415f581 ("MIPS: Loongson32: Remove unused platform devices")
removed the definitions of platform devices which have no in tree
drivers from common Loongson32 code, but missed their removal from
Loongson 1B board code in arch/mips/loongson32/ls1b/board.c. This causes
build failures due to the missing declarations of ls1x_dma_pdev,
ls1x_nand_pdev & their associated *_set_platdata functions.

Remove the dead code from arch/mips/loongson32/ls1b/board.c to fix the
build.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Fixes: 7b3415f581 ("MIPS: Loongson32: Remove unused platform devices")
2019-02-04 14:44:33 -08:00
Paul Burton
d6c2fba5e7
MIPS: Loongson32: Fix config brokenness; select SYS_SUPPORTS_32BIT_KERNEL
Commit a96d68ba3b ("MIPS: Loongson32: clarify we don't support MIPS16
and merge configs") attempted to reduce duplication in Kconfig by
consolidating some selects common to Loongson 1B & 1C CPUs under
CPU_LOONGSON1. Unfortunately it clearly wasn't tested because by
removing SYS_SUPPORTS_32BIT_KERNEL it prevented 32BIT from being enabled
leading to all sorts of strange build errors from a kernel configured to
build as neither 32 nor 64 bit.

Both loongson1b_defconfig & loongson1c_defconfig failed to build due to
this problem.

Revert the cleanup portions of commit a96d68ba3b ("MIPS: Loongson32:
clarify we don't support MIPS16 and merge configs"), keeping only its
removal of the selection of SYS_SUPPORTS_MIPS16.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Fixes: a96d68ba3b ("MIPS: Loongson32: clarify we don't support MIPS16 and merge configs")
2019-02-04 14:44:06 -08:00
Paul Burton
9ae1f262cd
MIPS: Don't select ARCH_HAS_SYNC_DMA_FOR_CPU when DMA is coherent
Commit f263f2a2c6 ("MIPS: Compile post DMA flush only when needed")
pushed the selection of ARCH_HAS_SYNC_DMA_FOR_CPU down to various
SYS_HAS_CPU_* Kconfig entries corresponding to CPUs for which
cpu_needs_post_dma_flush() might return true, but unfortunately missed
the fact that some of these CPUs can be used in configurations with
DMA_NONCOHERENT=n. When this is the case the kernel build does not
include our definition of arch_sync_dma_for_cpu() from
arch/mips/mm/dma-noncoherent.c and the build fails with a link error.

One example of this problem is ip27_defconfig:

  kernel/dma/direct.o: In function `dma_direct_sync_single_for_cpu':
  direct.c:(.text+0x6c): undefined reference to `arch_sync_dma_for_cpu'
  kernel/dma/direct.o: In function `dma_direct_sync_sg_for_cpu':
  direct.c:(.text+0x1f0): undefined reference to `arch_sync_dma_for_cpu'
  kernel/dma/direct.o: In function `dma_direct_alloc':
  direct.c:(.text+0xc20): undefined reference to `arch_dma_alloc'
  kernel/dma/direct.o: In function `dma_direct_free':
  direct.c:(.text+0xc3c): undefined reference to `arch_dma_free'
  make[1]: *** [Makefile:1021: vmlinux] Error 1
  make: *** [Makefile:152: sub-make] Error 2

Fix this by selecting ARCH_HAS_SYNC_DMA_FOR_CPU only when
DMA_NONCOHERENT is also selected. The SYS_HAS_CPU_BMIPS5000 case is left
as-is because systems with that CPU always select DMA_NONCOHERENT
anyway.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Fixes: f263f2a2c6 ("MIPS: Compile post DMA flush only when needed")
2019-02-04 13:58:07 -08:00
Paul Burton
afd375dc23
MIPS: Enable hugepage support for MIPS64r6
Our hugepage support already exists for MIPS64 CPUs, and is already
enabled for older architecture revisions. There's nothing MIPSr6
specific involved, and our hugepage support already works fine for
MIPS64r6 CPUs such as the I6500, so allow it to be selected in Kconfig.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:55 -08:00
Paul Burton
82f4f66ddf
MIPS: Remove open-coded cmpxchg() in set_pte()
set_pte() contains an open coded version of cmpxchg() - it atomically
replaces the buddy pte's value if it is currently zero. Simplify the
code considerably by just using cmpxchg() instead of reinventing it.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:48 -08:00
Paul Burton
c8790d657b
MIPS: MemoryMapID (MMID) Support
Introduce support for using MemoryMapIDs (MMIDs) as an alternative to
Address Space IDs (ASIDs). The major difference between the two is that
MMIDs are global - ie. an MMID uniquely identifies an address space
across all coherent CPUs. In contrast ASIDs are non-global per-CPU IDs,
wherein each address space is allocated a separate ASID for each CPU
upon which it is used. This global namespace allows a new GINVT
instruction be used to globally invalidate TLB entries associated with a
particular MMID across all coherent CPUs in the system, removing the
need for IPIs to invalidate entries with separate ASIDs on each CPU.

The allocation scheme used here is largely borrowed from arm64 (see
arch/arm64/mm/context.c). In essence we maintain a bitmap to track
available MMIDs, and MMIDs in active use at the time of a rollover to a
new MMID version are preserved in the new version. The allocation scheme
requires efficient 64 bit atomics in order to perform reasonably, so
this support depends upon CONFIG_GENERIC_ATOMIC64=n (ie. currently it
will only be included in MIPS64 kernels).

The first, and currently only, available CPU with support for MMIDs is
the MIPS I6500. This CPU supports 16 bit MMIDs, and so for now we cap
our MMIDs to 16 bits wide in order to prevent the bitmap growing to
absurd sizes if any future CPU does implement 32 bit MMIDs as the
architecture manuals suggest is recommended.

When MMIDs are in use we also make use of GINVT instruction which is
available due to the global nature of MMIDs. By executing a sequence of
GINVT & SYNC 0x14 instructions we can avoid the overhead of an IPI to
each remote CPU in many cases. One complication is that GINVT will
invalidate wired entries (in all cases apart from type 0, which targets
the entire TLB). In order to avoid GINVT invalidating any wired TLB
entries we set up, we make sure to create those entries using a reserved
MMID (0) that we never associate with any address space.

Also of note is that KVM will require further work in order to support
MMIDs & GINVT, since KVM is involved in allocating IDs for guests & in
configuring the MMU. That work is not part of this patch, so for now
when MMIDs are in use KVM is disabled.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:41 -08:00
Paul Burton
535113896e
MIPS: Add GINVT instruction helpers
Add a family of ginvt_* functions making it easy to emit a GINVT
instruction to globally invalidate TLB entries. We make use of the
_ASM_MACRO infrastructure to support emitting the instructions even if
the assembler isn't new enough to support them natively.

An associated STYPE_GINV definition & sync_ginv() function are added to
emit a sync instruction of type 0x14, which operates as a completion
barrier for these new GINVT (and GINVI) instructions.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:35 -08:00
Paul Burton
0b317c389c
MIPS: mm: Add set_cpu_context() for ASID assignments
When we gain MMID support we'll be storing MMIDs as atomic64_t values
and accessing them via atomic64_* functions. This necessitates that we
don't use cpu_context() as the left hand side of an assignment, ie. as a
modifiable lvalue. In preparation for this introduce a new
set_cpu_context() function & replace all assignments with cpu_context()
on their left hand side with an equivalent call to set_cpu_context().

To enforce that cpu_context() should not be used for assignments, we
rewrite it as a static inline function.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:33 -08:00
Paul Burton
42d5b84657
MIPS: mm: Unify ASID version checks
Introduce a new check_mmu_context() function to check an mm's ASID
version & get a new one if it's outdated, and a
check_switch_mmu_context() function which additionally sets up the new
ASID & page directory. Simplify switch_mm() & various
get_new_mmu_context() callsites in MIPS KVM by making use of the new
functions, which will help reduce the amount of code that requires
modification to gain MMID support.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:30 -08:00
Paul Burton
4ebea49ce2
MIPS: mm: Un-inline get_new_mmu_context
In preparation for adding MMID support to get_new_mmu_context() which
will increase the size of the function somewhat, move it from
asm/mmu_context.h into a C file.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:28 -08:00
Paul Burton
7e8556d06a
MIPS: mm: Split obj-y to a file per line
Split always-included objects to one per line in order to make it easier
to modify the list of included objects.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:26 -08:00
Paul Burton
558ec8ad71
MIPS: mm: Remove local_flush_tlb_mm()
All 3 variants of local_flush_tlb_mm() are now effectively simple calls
to drop_mmu_context(). Remove them and use drop_mmu_context() directly.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:24 -08:00
Paul Burton
f7908a007e
MIPS: mm: Remove redundant preempt_disable in local_flush_tlb_mm()
The r4k variant of local_flush_tlb_mm() wraps its call to
drop_mmu_context() with a preempt_disable() & preempt_enable() pair, but
this is redundant since drop_mmu_context() disables interrupts and from
Documentation/preempt-locking.txt:

  Note that you do not need to explicitly prevent preemption if you are
  holding any locks or interrupts are disabled, since preemption is
  implicitly disabled in those cases.

Remove the redundant preempt_disable() & preempt_enable() calls.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:22 -08:00
Paul Burton
6067d47e36
MIPS: mm: Move drop_mmu_context() comment into appropriate block
drop_mmu_context() is preceded by a comment indicating what happens if
the mm provided is currently active on the local CPU. Move that comment
into the block that executes in this case, adjusting slightly to reflect
its new location.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:20 -08:00
Paul Burton
c9b2a3dc24
MIPS: mm: Consolidate drop_mmu_context() has-ASID checks
If an mm does not have an ASID on the local CPU then drop_mmu_context()
is always redundant, since there's no context to "drop". Various callers
of drop_mmu_context() check whether the mm has been allocated an ASID
before making the call. Move that check into drop_mmu_context() and
remove it from callers to simplify them.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:18 -08:00
Paul Burton
67741ba3ba
MIPS: mm: Avoid HTW stop/start when dropping an inactive mm
If drop_mmu_context() is called with an mm that is not currently active
on the local CPU then there's no need for us to stop & start a hardware
page table walker because it can't be fetching entries for the ASID
corresponding to the mm we're operating on.

Move the htw_stop() & htw_start() calls into the block which we run only
if the mm is currently active, in order to avoid the redundant work.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:16 -08:00
Paul Burton
4739f7dd99
MIPS: mm: Remove redundant get_new_mmu_context() cpu argument
get_new_mmu_context() accepts a cpu argument, but implicitly assumes
that this is always equal to smp_processor_id() by operating on the
local CPU's TLB & icache.

Remove the cpu argument and have get_new_mmu_context() call
smp_processor_id() instead.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:14 -08:00
Paul Burton
9a27324fde
MIPS: mm: Remove redundant drop_mmu_context() cpu argument
The drop_mmu_context() function accepts a cpu argument, but it
implicitly expects that this is always equal to smp_processor_id() by
allocating & configuring an ASID on the local CPU when the mm is active
on the CPU indicated by the cpu argument.

All callers do provide the value of smp_processor_id() to the cpu
argument.

Remove the redundant argument and have drop_mmu_context() call
smp_processor_id() itself, making it clearer that the cpu variable
always represents the local CPU.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:12 -08:00
Paul Burton
c653bd04f7
MIPS: mm: Define activate_mm() using switch_mm()
MIPS has separate definitions of activate_mm() & switch_mm() which are
identical apart from switch_mm() checking that the ASID is valid before
acquiring a new one.

We know that when activate_mm() is called cpu_context(X, mm) will be
zero, and this will never be considered a valid ASID because we never
allow the ASID version number to be zero, instead beginning with version
1 using asid_first_version(). Therefore switch_mm() will always allocate
a new ASID when called for a new task, meaning that it will behave
identically to activate_mm().

Take advantage of this to remove the duplication & define activate_mm()
using switch_mm() just like many other architectures do.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-02-04 10:56:09 -08:00
Aaro Koskinen
ce680c8c99
MIPS: OCTEON: delete unused cvmx-smix-defs.h
Delete unused cvmx-smix-defs.h.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-01-28 15:17:41 -08:00
Aaro Koskinen
6aa08988f1
MIPS: OCTEON: delete SMI/MDIO enable
SMI/MDIO enable is handled by the OCTEON MDIO driver, so we can delete
the duplicated functionality from the platform code.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
2019-01-28 15:17:39 -08:00
Masahiro Yamada
a0f0b69f2c
MIPS: remove meaningless generic-(CONFIG_GENERIC_CSUM) += checksum.h
This line is weird in multiple ways.

(CONFIG_GENERIC_CSUM) might be a typo of $(CONFIG_GENERIC_CSUM).

Even if you add '$' to it, $(CONFIG_GENERIC_CSUM) is never evaluated
to 'y' because scripts/Makefile.asm-generic does not include
include/config/auto.conf. So, the asm-generic wrapper of checksum.h
is never generated.

Even if you manage to generate it, it is never included by anyone
because MIPS has the checkin header with the same file name:

  arch/mips/include/asm/checksum.h

As you see in the top Makefile, the checkin headers are included before
generated ones.

  LINUXINCLUDE    := \
                  -I$(srctree)/arch/$(SRCARCH)/include \
                  -I$(objtree)/arch/$(SRCARCH)/include/generated \
                  ...

Commit 4e0748f5be ("MIPS: Use generic checksum functions for MIPS R6")
already added the asm-generic fallback code in the checkin header:

  #ifdef CONFIG_GENERIC_CSUM
  #include <asm/generic/checksum.h>
  #else
    ...
  #endif

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-kernel@vger.kernel.org
2019-01-22 17:35:57 -08:00
Jiaxun Yang
7e280f6b05
MIPS: Loongson32: Revert ISA level to MIPS32R2
GS232 core have implemented all necessary mips32r2 instructions.
Serval missing FP instructions can be emulated by kernel.

The issue of di instruction have been solved.
Thus we revert the ISA level back to MIPS32R2.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: keguang.zhang@gmail.com
2019-01-22 17:32:23 -08:00