mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 15:01:13 +07:00
MIPS: Delete unused flush_cache_sigtramp()
Commit adcc81f148 ("MIPS: math-emu: Write-protect delay slot emulation
pages") left flush_cache_sigtramp() unused. Delete the dead code.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: linux-mips@vger.kernel.org
This commit is contained in:
Paul Burton
parent
c7e2d71dda
commit
3315b6b336
@ -25,7 +25,6 @@
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*
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* MIPS specific flush operations:
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*
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* - flush_cache_sigtramp() flush signal trampoline
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* - flush_icache_all() flush the entire instruction cache
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* - flush_data_cache_page() flushes a page from the data cache
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* - __flush_icache_user_range(start, end) flushes range of user instructions
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@ -110,7 +109,6 @@ extern void copy_from_user_page(struct vm_area_struct *vma,
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struct page *page, unsigned long vaddr, void *dst, const void *src,
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unsigned long len);
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extern void (*flush_cache_sigtramp)(unsigned long addr);
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extern void (*flush_icache_all)(void);
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extern void (*local_flush_data_cache_page)(void * addr);
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extern void (*flush_data_cache_page)(unsigned long addr);
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@ -127,23 +127,6 @@ static void octeon_flush_icache_range(unsigned long start, unsigned long end)
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}
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/**
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* Flush the icache for a trampoline. These are used for interrupt
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* and exception hooking.
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*
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* @addr: Address to flush
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*/
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static void octeon_flush_cache_sigtramp(unsigned long addr)
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{
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struct vm_area_struct *vma;
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down_read(¤t->mm->mmap_sem);
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vma = find_vma(current->mm, addr);
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octeon_flush_icache_all_cores(vma);
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up_read(¤t->mm->mmap_sem);
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}
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/**
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* Flush a range out of a vma
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*
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@ -289,7 +272,6 @@ void octeon_cache_init(void)
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flush_cache_mm = octeon_flush_cache_mm;
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flush_cache_page = octeon_flush_cache_page;
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flush_cache_range = octeon_flush_cache_range;
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flush_cache_sigtramp = octeon_flush_cache_sigtramp;
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flush_icache_all = octeon_flush_icache_all;
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flush_data_cache_page = octeon_flush_data_cache_page;
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flush_icache_range = octeon_flush_icache_range;
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@ -274,30 +274,6 @@ static void r3k_flush_data_cache_page(unsigned long addr)
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{
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}
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static void r3k_flush_cache_sigtramp(unsigned long addr)
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{
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unsigned long flags;
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pr_debug("csigtramp[%08lx]\n", addr);
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flags = read_c0_status();
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write_c0_status(flags&~ST0_IEC);
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/* Fill the TLB to avoid an exception with caches isolated. */
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asm( "lw\t$0, 0x000(%0)\n\t"
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"lw\t$0, 0x004(%0)\n\t"
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: : "r" (addr) );
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write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
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asm( "sb\t$0, 0x000(%0)\n\t"
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"sb\t$0, 0x004(%0)\n\t"
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: : "r" (addr) );
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write_c0_status(flags);
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}
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static void r3k_flush_kernel_vmap_range(unsigned long vaddr, int size)
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{
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BUG();
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@ -331,7 +307,6 @@ void r3k_cache_init(void)
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__flush_kernel_vmap_range = r3k_flush_kernel_vmap_range;
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flush_cache_sigtramp = r3k_flush_cache_sigtramp;
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local_flush_data_cache_page = local_r3k_flush_data_cache_page;
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flush_data_cache_page = r3k_flush_data_cache_page;
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@ -937,119 +937,6 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
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}
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#endif /* CONFIG_DMA_NONCOHERENT */
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struct flush_cache_sigtramp_args {
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struct mm_struct *mm;
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struct page *page;
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unsigned long addr;
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};
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/*
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* While we're protected against bad userland addresses we don't care
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* very much about what happens in that case. Usually a segmentation
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* fault will dump the process later on anyway ...
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*/
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static void local_r4k_flush_cache_sigtramp(void *args)
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{
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struct flush_cache_sigtramp_args *fcs_args = args;
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unsigned long addr = fcs_args->addr;
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struct page *page = fcs_args->page;
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struct mm_struct *mm = fcs_args->mm;
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int map_coherent = 0;
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void *vaddr;
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unsigned long ic_lsize = cpu_icache_line_size();
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unsigned long dc_lsize = cpu_dcache_line_size();
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unsigned long sc_lsize = cpu_scache_line_size();
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/*
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* If owns no valid ASID yet, cannot possibly have gotten
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* this page into the cache.
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*/
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if (!has_valid_asid(mm, R4K_HIT))
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return;
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if (mm == current->active_mm) {
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vaddr = NULL;
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} else {
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/*
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* Use kmap_coherent or kmap_atomic to do flushes for
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* another ASID than the current one.
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*/
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map_coherent = (cpu_has_dc_aliases &&
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page_mapcount(page) &&
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!Page_dcache_dirty(page));
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if (map_coherent)
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vaddr = kmap_coherent(page, addr);
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else
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vaddr = kmap_atomic(page);
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addr = (unsigned long)vaddr + (addr & ~PAGE_MASK);
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}
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R4600_HIT_CACHEOP_WAR_IMPL;
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if (!cpu_has_ic_fills_f_dc) {
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if (dc_lsize)
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vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
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: protected_writeback_dcache_line(
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addr & ~(dc_lsize - 1));
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if (!cpu_icache_snoops_remote_store && scache_size)
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vaddr ? flush_scache_line(addr & ~(sc_lsize - 1))
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: protected_writeback_scache_line(
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addr & ~(sc_lsize - 1));
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}
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if (ic_lsize)
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vaddr ? flush_icache_line(addr & ~(ic_lsize - 1))
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: protected_flush_icache_line(addr & ~(ic_lsize - 1));
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if (vaddr) {
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if (map_coherent)
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kunmap_coherent();
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else
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kunmap_atomic(vaddr);
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}
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if (MIPS4K_ICACHE_REFILL_WAR) {
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__asm__ __volatile__ (
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".set push\n\t"
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".set noat\n\t"
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".set "MIPS_ISA_LEVEL"\n\t"
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#ifdef CONFIG_32BIT
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"la $at,1f\n\t"
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#endif
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#ifdef CONFIG_64BIT
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"dla $at,1f\n\t"
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#endif
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"cache %0,($at)\n\t"
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"nop; nop; nop\n"
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"1:\n\t"
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".set pop"
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:
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: "i" (Hit_Invalidate_I));
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}
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if (MIPS_CACHE_SYNC_WAR)
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__asm__ __volatile__ ("sync");
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}
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static void r4k_flush_cache_sigtramp(unsigned long addr)
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{
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struct flush_cache_sigtramp_args args;
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int npages;
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down_read(¤t->mm->mmap_sem);
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npages = get_user_pages_fast(addr, 1, 0, &args.page);
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if (npages < 1)
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goto out;
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args.mm = current->mm;
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args.addr = addr;
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r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_sigtramp, &args);
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put_page(args.page);
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out:
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up_read(¤t->mm->mmap_sem);
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}
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static void r4k_flush_icache_all(void)
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{
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if (cpu_has_vtag_icache)
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@ -1978,7 +1865,6 @@ void r4k_cache_init(void)
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__flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
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flush_cache_sigtramp = r4k_flush_cache_sigtramp;
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flush_icache_all = r4k_flush_icache_all;
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local_flush_data_cache_page = local_r4k_flush_data_cache_page;
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flush_data_cache_page = r4k_flush_data_cache_page;
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@ -2033,7 +1919,6 @@ void r4k_cache_init(void)
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/* I$ fills from D$ just by emptying the write buffers */
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flush_cache_page = (void *)b5k_instruction_hazard;
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flush_cache_range = (void *)b5k_instruction_hazard;
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flush_cache_sigtramp = (void *)b5k_instruction_hazard;
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local_flush_data_cache_page = (void *)b5k_instruction_hazard;
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flush_data_cache_page = (void *)b5k_instruction_hazard;
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flush_icache_range = (void *)b5k_instruction_hazard;
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@ -2052,7 +1937,6 @@ void r4k_cache_init(void)
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flush_cache_mm = (void *)cache_noop;
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flush_cache_page = (void *)cache_noop;
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flush_cache_range = (void *)cache_noop;
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flush_cache_sigtramp = (void *)cache_noop;
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flush_icache_all = (void *)cache_noop;
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flush_data_cache_page = (void *)cache_noop;
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local_flush_data_cache_page = (void *)cache_noop;
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@ -290,25 +290,6 @@ static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
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}
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}
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static void tx39_flush_cache_sigtramp(unsigned long addr)
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{
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unsigned long ic_lsize = current_cpu_data.icache.linesz;
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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unsigned long config;
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unsigned long flags;
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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/* disable icache (set ICE#) */
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local_irq_save(flags);
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config = read_c0_conf();
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write_c0_conf(config & ~TX39_CONF_ICE);
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TX39_STOP_STREAMING();
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protected_flush_icache_line(addr & ~(ic_lsize - 1));
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write_c0_conf(config);
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local_irq_restore(flags);
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}
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static __init void tx39_probe_cache(void)
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{
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unsigned long config;
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@ -368,7 +349,6 @@ void tx39_cache_init(void)
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flush_icache_range = (void *) tx39h_flush_icache_all;
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local_flush_icache_range = (void *) tx39h_flush_icache_all;
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flush_cache_sigtramp = (void *) tx39h_flush_icache_all;
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local_flush_data_cache_page = (void *) tx39h_flush_icache_all;
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flush_data_cache_page = (void *) tx39h_flush_icache_all;
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@ -397,7 +377,6 @@ void tx39_cache_init(void)
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__flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
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flush_cache_sigtramp = tx39_flush_cache_sigtramp;
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local_flush_data_cache_page = local_tx39_flush_data_cache_page;
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flush_data_cache_page = tx39_flush_data_cache_page;
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@ -47,7 +47,6 @@ void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
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EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range);
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/* MIPS specific cache operations */
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void (*flush_cache_sigtramp)(unsigned long addr);
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void (*local_flush_data_cache_page)(void * addr);
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void (*flush_data_cache_page)(unsigned long addr);
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void (*flush_icache_all)(void);
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