For Tegra boards, the device-tree alias serial0 is used for the console
and so add the stdout-path information so that the console no longer
needs to be passed via the kernel boot parameters.
For tegra132-norrin the alias serial0 is not defined and so add this.
This has been tested on tegra132-norrin and tegra210-p2371-0000.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Remove the "#power-domain-cells" property which was incorrectly
included by commit e53095857166 ("arm64: tegra: Add Tegra210
support").
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add gpio-keys nodes for the volumn controls, lid switch, tablet mode and
power button.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
[treding@nvidia.com: use symbolic names for input types and codes]
[treding@nvidia.com: use wakeup-source instead of gpio-key,wakeup]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a gpio-keys device tree node to represent the Power, Volume Up and
Volume Down keys found on Jetson TX1.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add initial device-tree support for Google Pixel C (a.k.a. Smaug) based
upon Tegra210 SoC with 3 GiB of LPDDR4 RAM.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Though the keyboard and other driver will continue to support the legacy
"gpio-key,wakeup", "nvidia,wakeup-source" boolean property to enable the
wakeup source, "wakeup-source" is the new standard binding.
This patch replaces all the legacy wakeup properties with the unified
"wakeup-source" property in order to avoid any further copy-paste
duplication.
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The comment about the 8250 vs. APB DMA-enabled UART devices that was
added for Tegra20 and Tegra30 in commit b6551bb933 ("ARM: tegra: dts:
add aliases and DMA requestor for serial controller") introduced a typo
that has since spread to various other DTS include files. Fix all
occurrences of this typo.
Suggested-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses with
more than one cell.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The GeekBox contains an MXM3 module with a Rockchip RK3368 SoC.
Some connectors are available directly on the module.
This adds initial support, namely serial, USB, GMAC, eMMC, IR and TSADC.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add minimal DT files for the Amlogic P20x development boards, based on
the Amlogic S905/GXBB SoC.
Cc: Andreas Färber <afaerber@suse.de>
Cc: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Add minimal DT files for the Hardkernel ODROID-C2 board based on the
Amlogic S905/GXBB SoC.
Used the other gxbb boards from Andreas Färber as a starting point.
Cc: Andreas Färber <afaerber@suse.de>
Cc: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Apparently, it's not valid to have an alias point to a disabled device.
Fix this by moving the aliases that are used (serial0) into the files
that use them, and remove aliases to disabled devices (serial1).
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Resolve the following warnings from new dtc by adding the unit address:
DTC arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dtb
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
DTC arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dtb
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
DTC arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dtb
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
Fixes: cc733bc906 ("ARM64: dts: amlogic: Add Tronsmart Vega S95 configs")
Signed-off-by: Andreas Färber <afaerber@suse.de>
The LS1043a-QDS board is a high-performance computing, evaluation,
development, and test platform supporting the LS1043a SoC.
shawn.guo: sort the entries in Makefile alphabetcially
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The PCI memory windows available in vulcan.dtsi are limited to 128MB
for 32-bit BARs, and 4GB for 64-bit BARs. Given the memory mapped IO
space available in arm64, these windows can be increased substantially
to support more use cases.
The change increases the 32-bit window to 256MB and the 64-bit window
to 128 GB. The firmware on vulcan boards will use these ranges as well.
PCI IO windows are not supported on Vulcan, so remove them instead of
keeping an unused value.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Drop superfluous #address-cells and #size-cells.
Use KEY_POWER define for 116.
Rename sub-nodes to avoid new dtc warnings.
Reported-by: Julien Chauveau <chauveau.julien@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Julien Chauveau <chauveau.julien@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds mailbox device nodes in dts.
Mailbox is used by the Rockchip CPU cores to communicate
requests to MCU processor.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch adds TMU node, related temprature sensor and triping
point data for Atlas cpu core found on exynos7 SoC.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Adds CAN controller nodes for r8a7795.
Note: CAN channel register base address mentioned in R-Car Gen3 Hardware
User Manual v0.5E is incorrect. The corrected base addresses are:
CAN Channel 0 - 0xe6c30000
CAN Channel 1 - 0xe6c38000
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Adds external CAN clock node for r8a7795. This clock can be used as
fCAN clock of CAN and CAN FD controller.
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Since 16ccaf5bb5 ("pinctrl: sh-pfc: Accept standard function, pins and
groups properties") renesas pfc drivers accept generic "function", "pins"
and "groups" properties.
This patch updates the kzm9g device tree to use the generic properties.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Only one of "broken-cd" and "non-removable" should be supplied
according to Documentation/devicetree/bindings/mmc/mmc.txt.
Obviously emmc and sdio-wifi are non-removable devices, while
broken-cd is for removable device whose card detect pin is broken.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch fixes the incorrect Over-temperature protection pin.
since the rk3368 io list said the otp pin is gpio0a3.
Anyway, that should be fixed in here.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Here are some final updates for ARM SoC specific dts files:
* The i.MX changes were sent relatively late, and had a dependency
on the clk tree, so I delayed that a bit. Support for the new
i.MX6qp SoC and a couple of new boards is added in this branch.
* Uniphier renames a few files to match the final product names
that were decided by the company, kudos to the kernel developer(s)
for getting support upstream before the product release.
Also two boards are added. The patches were posted early enough
and nice overall, but we forgot to apply them and decided to
give it some more time in linux-next
* at91 has two small bug fixes.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIVAwUAVvQeGGCrR//JCVInAQLZSw//fuKWje/vigu4a8M8zQ9O3gN/8Elebq8E
OTY73jjpUfsJsRrqLPt9vmhrMsZ4raOIvG47B3ptwzvlV5ToRnlKEyyaYe200oxZ
5x+3i1jg20XRfTXwgusnENI+nqFO32VDaqSpYhUk6b1603RSzjFi+e0SydJaV78a
3GDDe9Y9lB7e5U/0BWBltPgKTQLrjyk7F32I33fcj3RInVi2NrmijXWic1eersyr
U0wHThKVGEHQSid+ZlSYZt0JnzotqCOpA+Pj3SrVCFdA9nOXT1lz1RTqSgNLhjfO
oXBKUWy0Ld1Ayjplg55Z7+QzOnn/JttHtumFYYu2OZcbSGr2AGWmKixR3j9Fvo8Y
X1xdo8eObMhxOrJIejy4NSC+xq/9Z7ur5mRcSMtfkmB1osirZrU9gevu6sBzV1Ha
ea3wFDaoXmmIjA0d5rQirR4XhDV7zs0rfbLPJd6Av6MuTw/hF6VYpEyKVUUzOqld
+jpDKweJhI64wKZ5oQ6AahCPV9LoQrTMk8ElJX07ndLSnYXAXz8B44O4It5b13fH
3UiWPX1tOV1HIed6z8zWUp77N5C5SeyNPtMcdvusf5/hS6gopgxGN3mqKmOUMLeO
iwX2krBpuXWj+3T/FjqSFdUrHAzbmjTIgqv70dreqj4DTkmeYr9BoInjWtzgZ6c0
bUPwJ93kFDc=
=p5al
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull more ARM DT changes from Arnd Bergmann:
"Here are some final updates for ARM SoC specific dts files:
- The i.MX changes were sent relatively late, and had a dependency on
the clk tree, so I delayed that a bit. Support for the new i.MX6qp
SoC and a couple of new boards is added in this branch.
- Uniphier renames a few files to match the final product names that
were decided by the company, kudos to the kernel developer(s) for
getting support upstream before the product release. Also two
boards are added. The patches were posted early enough and nice
overall, but we forgot to apply them and decided to give it some
more time in linux-next
- at91 has two small bug fixes"
* tag 'armsoc-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits)
ARM: dts: at91: sama5d4 Xplained: don't disable hsmci regulator
ARM: dts: at91: sama5d3 Xplained: don't disable hsmci regulator
ARM: dts: uniphier: add pinmux node for I2C ch4
ARM: dts: uniphier: add @{address} to EEPROM node
ARM: dts: uniphier: add PH1-Pro4 Sanji board support
ARM: dts: uniphier: add PH1-Pro4 Ace board support
ARM: dts: uniphier: enable I2C channel 2 of ProXstream2 Gentil board
ARM: dts: uniphier: add EEPROM node for ProXstream2 Gentil board
ARM: dts: uniphier: add reference clock nodes
ARM: dts: uniphier: rework UniPhier System Bus nodes
ARM: dts: uniphier: factor out ranges property of support card
arm64: dts: uniphier: rename PH1-LD10 to PH1-LD20
ARM: dts: imx53-qsb: Fix gpio button polarity
ARM: dts: vfxxx: Add DAC node for Vybrid SoC
ARM: dts: imx6q: add missing links between ipu2 and mipi dsi
ARM: dts: imx: Add support for Advantech/GE B850v3
ARM: dts: imx: Add support for Advantech/GE B650v3
ARM: dts: imx: Add support for Advantech/GE B450v3
ARM: dts: imx: Add support for Advantech/GE Bx50v3
ARM: dts: imx: Add Advantech BA-16 Qseven module
...
This time with:
* Updates for the Exynos IOMMU driver to make use of default
domains and to add support for the SYSMMU v5
* New Mediatek IOMMU driver
* Support for the ARMv7 short descriptor format in the
io-pgtable code
* Default domain support for the ARM SMMU
* Couple of other small fixes all over the place
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJW7/7rAAoJECvwRC2XARrjKvgP/2sgR6lzIGksKpZRNNNoyJEp
PbFt3zxBvIPYow6rQtfMqU82FAi6psq+EVKq+M0EOeJrjFGawwWpN9H/e0ZCs5Z/
/s6DIljRFKrbty59eFsHn57Pd+302Pt0GkwnSgdgBJD7FimozyyeMJnAOs5gPjYT
jF2ajV9FYa5rIRrMsSD2KjLKgBb3xVsgUlW72NU2WwldnOB6fSsfg4ll01kbzTon
IQENT5ywk9zZFouLyrX6EvcvowHslO/sZhGe3Py9qOOHpu9roW7EE7rEGYdabn47
PGpw8O5NOeSrQNzlmhXje5tuKxkh33DV55s7vVcaOy66kWbYExJGoz1/V7Vju4n1
pok82L3N8eauMs3xqNOiQMV8UsWIXOzdMMaGypM18pCVKMaAUiz9vO9rLSmR4Z20
IYFiX0yBXhc1AXMnrRlq/xR2WjBX2L2s0VguvYoSssdmJUZ9aKYxsurF8Ylqpm+1
wymOj+gjM056DqAXcYBVg4ZPOEezRjnUe2qD8lZ4et3xOVUL3LXRi8FmacztEB97
chUSB5mur/XRy6bOVI2l1uRQaqdfErgbCey0fa9N/SWKSHKWtAfR6CYYVpoR6m0L
H/xL7yCn6jUEoadKxZyTKnX8GIN6wNcZdI+58OOMz3sjlmWs69wgdPt8Xx2RNHpm
7caf/9sTdpUeh+V2fySD
=uiAk
-----END PGP SIGNATURE-----
Merge tag 'iommu-updates-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU updates from Joerg Roedel:
- updates for the Exynos IOMMU driver to make use of default domains
and to add support for the SYSMMU v5
- new Mediatek IOMMU driver
- support for the ARMv7 short descriptor format in the io-pgtable code
- default domain support for the ARM SMMU
- couple of other small fixes all over the place
* tag 'iommu-updates-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (41 commits)
iommu/ipmmu-vmsa: Add r8a7795 DT binding
iommu/mediatek: Check for NULL instead of IS_ERR()
iommu/io-pgtable-armv7s: Fix kmem_cache_alloc() flags
iommu/mediatek: Fix handling of of_count_phandle_with_args result
iommu/dma: Fix NEED_SG_DMA_LENGTH dependency
iommu/mediatek: Mark PM functions as __maybe_unused
iommu/mediatek: Select ARM_DMA_USE_IOMMU
iommu/exynos: Use proper readl/writel register interface
iommu/exynos: Pointers are nto physical addresses
dts: mt8173: Add iommu/smi nodes for mt8173
iommu/mediatek: Add mt8173 IOMMU driver
memory: mediatek: Add SMI driver
dt-bindings: mediatek: Add smi dts binding
dt-bindings: iommu: Add binding for mediatek IOMMU
iommu/ipmmu-vmsa: Use ARCH_RENESAS
iommu/exynos: Support multiple attach_device calls
iommu/exynos: Add Maintainers entry for Exynos SYSMMU driver
iommu/exynos: Add support for v5 SYSMMU
iommu/exynos: Update device tree documentation
iommu/exynos: Add support for SYSMMU controller with bogus version reg
...
- Initial support for ARMv8.1 CPU PMUs
- Support for the CPU PMU in Cavium ThunderX
- CPU PMU support for systems running 32-bit Linux in secure mode
- Support for the system PMU in ARM CCI-550 (Cache Coherent Interconnect)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCgAGBQJW794rAAoJELescNyEwWM0O5IH/0ejoUjip3n4dFZnSzAbQQZe
VxCy3DXW5gS8YaswwX2dFw9K772/BpHlazq8AIJIhaR+b+Zzl5t0iOc12HluDilV
pMvi0JTCxwJhsEiKZnP0cVAU9HM6MAgtMOEegkd/YNESKQey30NeDtIcz/pQfTUV
28AF71+w5VPj/1EpHEEhHQsASRIx7eDbKzThzdlb8PnDS0o23QJhL9HjVTNIAlB8
BGxrUBKtBu0eH2Hx33vNjc7UYx1WZQlCk5cAaXevA8mbFXzYaMQI2Cel2nbNMO9i
eu5zPkDUCG7dq16PxK6IgM4AsDCtmmDuckLdN6UEQWYxkLbb2qHNRKtj0bKB8Sk=
=E4PE
-----END PGP SIGNATURE-----
Merge tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm[64] perf updates from Will Deacon:
"I have another mixed bag of ARM-related perf patches here.
It's about 25% CPU and 75% interconnect, but with drivers/bus/
languishing without an obvious maintainer or tree, Olof and I agreed
to keep all of these PMU patches together. I suspect a whole load of
code from drivers/bus/arm-* can be moved under drivers/perf/, so
that's on the radar for the future.
Summary:
- Initial support for ARMv8.1 CPU PMUs
- Support for the CPU PMU in Cavium ThunderX
- CPU PMU support for systems running 32-bit Linux in secure mode
- Support for the system PMU in ARM CCI-550 (Cache Coherent Interconnect)"
* tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (26 commits)
drivers/perf: arm_pmu: avoid NULL dereference when not using devicetree
arm64: perf: Extend ARMV8_EVTYPE_MASK to include PMCR.LC
arm-cci: remove unused variable
arm-cci: don't return value from void function
arm-cci: make private functions static
arm-cci: CoreLink CCI-550 PMU driver
arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMU
arm-cci: CCI-500: Work around PMU counter writes
arm-cci: Provide hook for writing to PMU counters
arm-cci: Add helper to enable PMU without synchornising counters
arm-cci: Add routines to save/restore all counters
arm-cci: Get the status of a counter
arm-cci: write_counter: Remove redundant check
arm-cci: Delay PMU counter writes to pmu::pmu_enable
arm-cci: Refactor CCI PMU enable/disable methods
arm-cci: Group writes to counter
arm-cci: fix handling cpumask_any_but return value
arm-cci: simplify sysfs attr handling
drivers/perf: arm_pmu: implement CPU_PM notifier
arm64: dts: Add Cavium ThunderX specific PMU
...
The arm64 device tree changes make up an increasing portion of
the overall changes, so they are kept separate from the 32-bit
devicetree changes and from the other arm64 updates.
Newly added SoCs and boards are:
- 96Boards Husky board
- AMD Overdrive board
- Amlogic S905 SoC and related Tronsmart boxes
- Annapurna Labs Alpine family and development board
- Broadcom Vulcan servers
- Broadcom Northstar 2 SoC
- Marvell Armada 3700 family and development board
- Qualcomm MSM8996 SoC
Additional devices are enabled for existing platforms from
Applied Micro, Hisilicon, Mediatek, Qualcomm, and Renesas and
there are a couple of other updates for Rockchip, Xilinx and
NXP/Freescale.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIUAwUAVu67Q2CrR//JCVInAQL0ng/47UBpXwVw1V5zm9lUIA1oluo/cKgFyGsi
G8wOzoMwmZocDKXC7mONS6c6AjeqszTNQ8V2j2ieU7G7S+moi8SnTcc8pJKD26HL
KvsxGtnfKXFAfZkJ8iERxHmZojHN93EF01P3R+pEIlKzFs+8Mx66VbUp2mVEMrHR
wClzoW1n49kdpQhGuGeryFufAgUd/OKG2VDosCDR5hpoTNYWenuIQB5VHtiow08U
9SVEBUW6YxDV3hiyt4Vd5FvrPT/PJEPchmnscgC8L/sVD57XeH5h68GE4mDplc68
QxzFqDAHuInPS/p6h9zFALawh8lXvu+ERTt6XZqGxzvhEkifx6grOBVCaVSbfpct
JLzFUZKcGXDLekVq0GQWj7ZCQnWeRSdtIGBtoaEzLzjZ0aGeSeN0nuldWFRx3Eml
3eTpHsyLOtjsSjZcdSWtzSBbN2OuymvSKfjdHfqANbpsUYZREI/HXNg/WLCzhsbr
o7VQig/dkSQ+Od39omKk1AP5adLpCdUc0nm2omdUJRVEuJ0l9fLp3Td4nZTtOPle
Vbf5lYHGAMCrgzPEJnMxtUb1XlstQdij2FEYTeqUqHyZ1kZNaGOaWWgXNW6ORyn9
eOav61eWwZ0qvppaQKzv7rIV5qtP5Zg3kLvsNvQpWhr3ev14n0rvFu1RAy/yz2gR
zMtRVagq/w==
=izw3
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Arnd Bergmann:
"The arm64 device tree changes make up an increasing portion of the
overall changes, so they are kept separate from the 32-bit devicetree
changes and from the other arm64 updates.
Newly added SoCs and boards are:
- 96Boards Husky board
- AMD Overdrive board
- Amlogic S905 SoC and related Tronsmart boxes
- Annapurna Labs Alpine family and development board
- Broadcom Vulcan servers
- Broadcom Northstar 2 SoC
- Marvell Armada 3700 family and development board
- Qualcomm MSM8996 SoC
Additional devices are enabled for existing platforms from Applied
Micro, Hisilicon, Mediatek, Qualcomm, and Renesas and there are a
couple of other updates for Rockchip, Xilinx and NXP/Freescale"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (102 commits)
ARM64: dts: amlogic: Add Tronsmart Vega S95 configs
Documentation: devicetree: amlogic: Document Tronsmart Vega S95 boards
ARM64: dts: Prepare configs for Amlogic Meson GXBaby
Documentation: devicetree: amlogic: Document Meson GXBaby
devicetree: bindings: Add vendor prefix for Tronsmart
arm64: dts: qcom: Fix MPP's function used for LED control
arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsi
arm64: dts: add the Alpine v2 EVP
arm64: dts: marvell: re-order Device Tree nodes for Armada AP806
arm64: dts: marvell: update Armada AP806 clock description
arm64: dts: marvell: add Device Tree files for Armada 7K/8K
arm64: dts: apm: Add DT node for X-Gene v2 SLIMpro Mailbox I2C Driver
arm64: dts: apm: Mailbox device tree node for APM X-Gene v2 platform.
arm64: dts: apm: Add DT node for X-Gene v1 SLIMpro Mailbox I2C Driver
arm64: dts: apm: mailbox device tree node for APM X-Gene platform.
arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platforms
arm64: dts: apm: Update GPIO standby controller DT node for X-Gene v2 platforms
arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platforms
arm64: dts: salvator-x: enable USB 2.0 Host of channel 1 and 2
arm64: dts: salvator-x: enable usb2_phy of channel 1 and 2
...
These are all the updates to device tree files for 32-bit platforms,
plus a couple of related 64-bit updates:
New SoC support:
- Allwinner A83T
- Axis Artpec-6 SoC
- Mediatek MT7623 SoC
- TI Keystone K2G SoC
- ST Microelectronics stm32f469
New board or machine support:
- ARM Juno R2
- Buffalo Linkstation LS-QVL and LS-GL
- Cubietruck plus
- D-Link DIR-885L
- DT support for ARM RealView PB1176 and PB11MPCore
- Google Nexus 7
- Homlet v2
- Itead Ibox
- Lamobo R1
- LG Optimus Black
- Logicpd dm3730
- Raspberry Pi Model A
Other changes include
- Lots of updates for Qualcomm APQ8064, MSM8974 and others
- Improved support for Nokia N900 and other OMAP machines
- Common clk support for lpc32xx
- HDLCD display on ARM
- Improved stm32f429 support
- Improved Renesas device support, r8a779x and others
- Lots of Rockchip updates
- Samsung cleanups
- ADC support for Atmel SAMA5D2
- BCM2835 (Raspberry Pi) improvements
- Broadcom Northstar Plus enhancements
- OMAP GPMC rework
- Several improvements for Atmel SAMA5D2 / Xplained
- Global change to remove inofficial "arm,amba-bus" compatible string
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIVAwUAVu67PmCrR//JCVInAQIZlA//UV7DK8tHNvLCuHBX8MnW5xxljUWFCoFp
Zsi9LJj+KDIE+rpY65n75+il+rT1ZcgaITzH+Qvaq75f51ZwW7HY5jHiPYsINa80
oMtbdWlnpNIH48jD5yMKaDTE8md7lZ8tgA//6aw1doDx2LYX4D1QRG6XI1OC6E62
OjlzXkTTe50Aowi6aMQz4PZQM89m09FT0aw/Qsokh0fcW8oXhXcJSlFgLF/tZUYs
VU4oWshUX2/VW3ShXlAJdrItpdDIogwZtDS7xKXmk6AHfapLb7s4HuEOInqbeOa7
QWTjtoVj6ZHyeVptyn6kj5+xOdL4bXAT4Kg2TctF1iv0I6XG8CKflNqOJt2wLR1M
DP0VQXK0TmKCeI+vbRhniLRP7EPYp4N9KFAe6M6aVP3nKYX81EqWdtPjuwp7GxAC
sIGad2ocynKW4Eb4xOD2/5EwzkhwHv7SPQTCyCyQo8ILGN5MOSBZJOC1kXATTtbq
u7LbOLyFMeWPJFYZyPxe79MwiX0dfJekrZYQ1tYL3MEQqQNmbY6+r+6QLMhT+iSj
SE1oBaAReOuZUquiBEt398OvdfQ/n+F5BasKKCojXuhueNO3+rY7mT5X/vmOs2eh
CUpfl766CixaZmF6p8es1Qeu64ASODbPiOw3Dv5Cgwcbfy/C3b3ccty0zazlOaNJ
Sm6VXU3RavA=
=RLUc
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"These are all the updates to device tree files for 32-bit platforms,
plus a couple of related 64-bit updates:
New SoC support:
- Allwinner A83T
- Axis Artpec-6 SoC
- Mediatek MT7623 SoC
- TI Keystone K2G SoC
- ST Microelectronics stm32f469
New board or machine support:
- ARM Juno R2
- Buffalo Linkstation LS-QVL and LS-GL
- Cubietruck plus
- D-Link DIR-885L
- DT support for ARM RealView PB1176 and PB11MPCore
- Google Nexus 7
- Homlet v2
- Itead Ibox
- Lamobo R1
- LG Optimus Black
- Logicpd dm3730
- Raspberry Pi Model A
Other changes include
- Lots of updates for Qualcomm APQ8064, MSM8974 and others
- Improved support for Nokia N900 and other OMAP machines
- Common clk support for lpc32xx
- HDLCD display on ARM
- Improved stm32f429 support
- Improved Renesas device support, r8a779x and others
- Lots of Rockchip updates
- Samsung cleanups
- ADC support for Atmel SAMA5D2
- BCM2835 (Raspberry Pi) improvements
- Broadcom Northstar Plus enhancements
- OMAP GPMC rework
- Several improvements for Atmel SAMA5D2 / Xplained
- Global change to remove inofficial "arm,amba-bus" compatible
string"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (350 commits)
ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"
ARM: dts: artpec: dual-license on artpec6.dtsi
ARM: dts: ux500: add synaptics RMI4 for Ux500 TVK DT
arm64: dts: juno/vexpress: fix node name unit-address presence warnings
arm64: dts: foundation-v8: add SBSA Generic Watchdog device node
ARM: dts: at91: sama5d2 Xplained: add leds node
ARM: dts: at91: sama5d2 Xplained: add user push button
ARM: dts: at91: sama5d2 Xplained: set pin muxing for usb gadget and usb host
ARM: dts: stm32f429: Enable Ethernet on Eval board
ARM: dts: omap3-sniper: TWL4030 keypad support
Revert "ARM: dts: DRA7: Add dt nodes for PWMSS"
ARM: dts: dm814x: dra62x: Disable wait pin monitoring for NAND
ARM: dts: dm814x: dra62x: Fix NAND device nodes
ARM: dts: stm32f429: Add Ethernet support
ARM: dts: stm32f429: Add system config bank node
ARM: dts: at91: sama5d2: add nand0 and nfc0 nodes
ARM: dts: at91: sama5d2: add dma properties to UART nodes
ARM: dts: at91: sama5d2 Xplained: Correct the macb irq pinctrl node
ARM: dts: exynos: Don't overheat the Odroid XU3-Lite on high load
ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs
...
Here's our branch of ARM64 contents for this merge window, now
containing all ARM64 changes other than device tree files.
- Various new platforms get added
- Allwinner A64 SoC
- Annapurna Labs Alpine SoCs
- Broadcom Vulcan
- Marvell Armada 3700 SoCs
- Amlogic S905
- Various defconfig changes to enable platform specific drivers
This branch includes the clk git tree to resolve a build-time
dependency.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIVAwUAVu67KmCrR//JCVInAQKo+xAAnyjdtGviIade2NX+8dpkBvFVkaZMJVK6
l4DEhM/zYLYToAaP8NHBq14NmcM0dVUF58yop5FG2oJyoJSnFYdeaSYgJG3P+pO9
gza5Hh5FKy/yjbsO589d0rzJrK9dTYI9xAViSNei9JU6nKdQD7PIwP3DnzSMKIzW
sekOJArAT9r2L51XlbBd0oo1GGGvH9tQW2ImBs7l5RXnuXxcudIlwpBwSNRg1b9C
89V3vPdUse6j6jemxk4ZVZud7z9HqDGqBxUx1TC+tA0dWxIymMpQneLqM+/CNgdC
fmhg1sYKsOMxHSiJc4zYpmjDU6miaq1c+/wQMbOoOR6hdKGZupd4cclepzNswc/M
wukuxrcMwdXRaSSvPGrefKWGA6OppFl3rbporhoOG0QUaOHzm63Acjppq3/hxx5h
Ffawp/wO8AmKEQDmA6bj/RecoWJ1Z3aEs3AWThqKyJ2I5gvRdO6OkziTVl3S4x9v
tPL+pe/i7NuHw0rviYGYuE/n8LS48a7cGoRkdkDVHHGi+A/ArfoqVbY0HG3YiIy3
xMebvSSAxUjlNtO2AOrLjKAHr15ieuJggny5N8LlfdKx08RF15wd2eaom0yr8Vc/
mqXTw4wX2KuuYCW3GatJwqYu5Av8wuY1Ma1pYIpEUgq4nY4OId0izSjn0oVlivYx
/po9snlvFpc=
=fO+Q
-----END PGP SIGNATURE-----
Merge tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC 64-bit changes from Arnd Bergmann:
"Here's our branch of ARM64 contents for this merge window, now
containing all ARM64 changes other than device tree files.
- Various new platforms get added:
* Allwinner A64 SoC
* Annapurna Labs Alpine SoCs
* Broadcom Vulcan
* Marvell Armada 3700 SoCs
* Amlogic S905
- Various defconfig changes to enable platform specific drivers
This branch includes the clk git tree to resolve a build-time
dependency"
* tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits)
arm64: defconfig: Increase MMC_BLOCK_MINORS to 16
arm64: defconfig: Add Qualcomm sdhci and restart functionality
ARM64: Enable Amlogic Meson GXBaby platform
arm64: defconfig: Enable Samsung MFD and related configs
arm64: alpine: select the Alpine MSI controller driver
arm64: defconfig: enable the Alpine family
arm64: add Alpine SoC family
arm64: defconfig: Enable exynos thermal config
arm64: add defconfig options for Allwinner SoCs
arm64: defconfig: Enable DesignWare APB GPIO controller
arm64: defconfig: Add Renesas R-Car Gen3 USB 2.0 phy driver support
arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS
clk: samsung: Don't build ARMv8 clock drivers on ARMv7
MAINTAINERS: Add entry for Broadcom Vulcan SoC
arm64: cputype info for Broadcom Vulcan
arm64: Broadcom Vulcan support
arm64: defconfig: Add Broadcom Vulcan to defconfig
arm64: update ARCH_MVEBU for Marvell Armada 7K/8K support
Documentation: arm: add Marvell Armada 7K and 8K families
Documentation: arm: add link to Armada 38x Functional Spec
...
Pull networking updates from David Miller:
"Highlights:
1) Support more Realtek wireless chips, from Jes Sorenson.
2) New BPF types for per-cpu hash and arrap maps, from Alexei
Starovoitov.
3) Make several TCP sysctls per-namespace, from Nikolay Borisov.
4) Allow the use of SO_REUSEPORT in order to do per-thread processing
of incoming TCP/UDP connections. The muxing can be done using a
BPF program which hashes the incoming packet. From Craig Gallek.
5) Add a multiplexer for TCP streams, to provide a messaged based
interface. BPF programs can be used to determine the message
boundaries. From Tom Herbert.
6) Add 802.1AE MACSEC support, from Sabrina Dubroca.
7) Avoid factorial complexity when taking down an inetdev interface
with lots of configured addresses. We were doing things like
traversing the entire address less for each address removed, and
flushing the entire netfilter conntrack table for every address as
well.
8) Add and use SKB bulk free infrastructure, from Jesper Brouer.
9) Allow offloading u32 classifiers to hardware, and implement for
ixgbe, from John Fastabend.
10) Allow configuring IRQ coalescing parameters on a per-queue basis,
from Kan Liang.
11) Extend ethtool so that larger link mode masks can be supported.
From David Decotigny.
12) Introduce devlink, which can be used to configure port link types
(ethernet vs Infiniband, etc.), port splitting, and switch device
level attributes as a whole. From Jiri Pirko.
13) Hardware offload support for flower classifiers, from Amir Vadai.
14) Add "Local Checksum Offload". Basically, for a tunneled packet
the checksum of the outer header is 'constant' (because with the
checksum field filled into the inner protocol header, the payload
of the outer frame checksums to 'zero'), and we can take advantage
of that in various ways. From Edward Cree"
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1548 commits)
bonding: fix bond_get_stats()
net: bcmgenet: fix dma api length mismatch
net/mlx4_core: Fix backward compatibility on VFs
phy: mdio-thunder: Fix some Kconfig typos
lan78xx: add ndo_get_stats64
lan78xx: handle statistics counter rollover
RDS: TCP: Remove unused constant
RDS: TCP: Add sysctl tunables for sndbuf/rcvbuf on rds-tcp socket
net: smc911x: convert pxa dma to dmaengine
team: remove duplicate set of flag IFF_MULTICAST
bonding: remove duplicate set of flag IFF_MULTICAST
net: fix a comment typo
ethernet: micrel: fix some error codes
ip_tunnels, bpf: define IP_TUNNEL_OPTS_MAX and use it
bpf, dst: add and use dst_tclassid helper
bpf: make skb->tc_classid also readable
net: mvneta: bm: clarify dependencies
cls_bpf: reset class and reuse major in da
ldmvsw: Checkpatch sunvnet.c and sunvnet_common.c
ldmvsw: Add ldmvsw.c driver code
...
During the review process of the UniPhier System Bus driver
(drivers/bus/uniphier.c), the current binding of the System Bus
Controller turned out to be no good. In order to make the driver
really usable, we have to switch over to the new binding defined by
Documentation/devicetree/bindings/bus/uniphier-system-bus.txt.
The old binding will be still supported for a while to keep the
backward compatibility.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This property is used in common by several boards. Move it to the
common place (uniphier-support-card.dtsi). If necessary, each board
can still override the property.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Due to the company's awful projecting, this chip has been renamed to
PH1-LD20. It has not been shipped yet, this change would have no
impact on our customers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Initial page table creation reworked to avoid breaking large block
mappings (huge pages) into smaller ones. The ARM architecture requires
break-before-make in such cases to avoid TLB conflicts but that's not
always possible on live page tables
- Kernel virtual memory layout: the kernel image is no longer linked to
the bottom of the linear mapping (PAGE_OFFSET) but at the bottom of
the vmalloc space, allowing the kernel to be loaded (nearly) anywhere
in physical RAM
- Kernel ASLR: position independent kernel Image and modules being
randomly mapped in the vmalloc space with the randomness is provided
by UEFI (efi_get_random_bytes() patches merged via the arm64 tree,
acked by Matt Fleming)
- Implement relative exception tables for arm64, required by KASLR
(initial code for ARCH_HAS_RELATIVE_EXTABLE added to lib/extable.c but
actual x86 conversion to deferred to 4.7 because of the merge
dependencies)
- Support for the User Access Override feature of ARMv8.2: this allows
uaccess functions (get_user etc.) to be implemented using LDTR/STTR
instructions. Such instructions, when run by the kernel, perform
unprivileged accesses adding an extra level of protection. The
set_fs() macro is used to "upgrade" such instruction to privileged
accesses via the UAO bit
- Half-precision floating point support (part of ARMv8.2)
- Optimisations for CPUs with or without a hardware prefetcher (using
run-time code patching)
- copy_page performance improvement to deal with 128 bytes at a time
- Sanity checks on the CPU capabilities (via CPUID) to prevent
incompatible secondary CPUs from being brought up (e.g. weird
big.LITTLE configurations)
- valid_user_regs() reworked for better sanity check of the sigcontext
information (restored pstate information)
- ACPI parking protocol implementation
- CONFIG_DEBUG_RODATA enabled by default
- VDSO code marked as read-only
- DEBUG_PAGEALLOC support
- ARCH_HAS_UBSAN_SANITIZE_ALL enabled
- Erratum workaround Cavium ThunderX SoC
- set_pte_at() fix for PROT_NONE mappings
- Code clean-ups
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW6u95AAoJEGvWsS0AyF7xMyoP/3x2O6bgreSQ84BdO4JChN4+
RQ9OVdX8u2ItO9sgaCY2AA6KoiBuEjGmPl/XRuK0I7DpODTtRjEXQHuNNhz8AelC
hn4AEVqamY6Z5BzHFIjs8G9ydEbq+OXcKWEdwSsBhP/cMvI7ss3dps1f5iNPT5Vv
50E/kUz+aWYy7pKlB18VDV7TUOA3SuYuGknWV8+bOY5uPb8hNT3Y3fHOg/EuNNN3
DIuYH1V7XQkXtF+oNVIGxzzJCXULBE7egMcWAm1ydSOHK0JwkZAiL7OhI7ceVD0x
YlDxBnqmi4cgzfBzTxITAhn3OParwN6udQprdF1WGtFF6fuY2eRDSH/L/iZoE4DY
OulL951OsBtF8YC3+RKLk908/0bA2Uw8ftjCOFJTYbSnZBj1gWK41VkCYMEXiHQk
EaN8+2Iw206iYIoyvdjGCLw7Y0oakDoVD9vmv12SOaHeQljTkjoN8oIlfjjKTeP7
3AXj5v9BDMDVh40nkVayysRNvqe48Kwt9Wn0rhVTLxwdJEiFG/OIU6HLuTkretdN
dcCNFSQrRieSFHpBK9G0vKIpIss1ZwLm8gjocVXH7VK4Mo/TNQe4p2/wAF29mq4r
xu1UiXmtU3uWxiqZnt72LOYFCarQ0sFA5+pMEvF5W+NrVB0wGpXhcwm+pGsIi4IM
LepccTgykiUBqW5TRzPz
=/oS+
-----END PGP SIGNATURE-----
Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Catalin Marinas:
"Here are the main arm64 updates for 4.6. There are some relatively
intrusive changes to support KASLR, the reworking of the kernel
virtual memory layout and initial page table creation.
Summary:
- Initial page table creation reworked to avoid breaking large block
mappings (huge pages) into smaller ones. The ARM architecture
requires break-before-make in such cases to avoid TLB conflicts but
that's not always possible on live page tables
- Kernel virtual memory layout: the kernel image is no longer linked
to the bottom of the linear mapping (PAGE_OFFSET) but at the bottom
of the vmalloc space, allowing the kernel to be loaded (nearly)
anywhere in physical RAM
- Kernel ASLR: position independent kernel Image and modules being
randomly mapped in the vmalloc space with the randomness is
provided by UEFI (efi_get_random_bytes() patches merged via the
arm64 tree, acked by Matt Fleming)
- Implement relative exception tables for arm64, required by KASLR
(initial code for ARCH_HAS_RELATIVE_EXTABLE added to lib/extable.c
but actual x86 conversion to deferred to 4.7 because of the merge
dependencies)
- Support for the User Access Override feature of ARMv8.2: this
allows uaccess functions (get_user etc.) to be implemented using
LDTR/STTR instructions. Such instructions, when run by the kernel,
perform unprivileged accesses adding an extra level of protection.
The set_fs() macro is used to "upgrade" such instruction to
privileged accesses via the UAO bit
- Half-precision floating point support (part of ARMv8.2)
- Optimisations for CPUs with or without a hardware prefetcher (using
run-time code patching)
- copy_page performance improvement to deal with 128 bytes at a time
- Sanity checks on the CPU capabilities (via CPUID) to prevent
incompatible secondary CPUs from being brought up (e.g. weird
big.LITTLE configurations)
- valid_user_regs() reworked for better sanity check of the
sigcontext information (restored pstate information)
- ACPI parking protocol implementation
- CONFIG_DEBUG_RODATA enabled by default
- VDSO code marked as read-only
- DEBUG_PAGEALLOC support
- ARCH_HAS_UBSAN_SANITIZE_ALL enabled
- Erratum workaround Cavium ThunderX SoC
- set_pte_at() fix for PROT_NONE mappings
- Code clean-ups"
* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (99 commits)
arm64: kasan: Fix zero shadow mapping overriding kernel image shadow
arm64: kasan: Use actual memory node when populating the kernel image shadow
arm64: Update PTE_RDONLY in set_pte_at() for PROT_NONE permission
arm64: Fix misspellings in comments.
arm64: efi: add missing frame pointer assignment
arm64: make mrs_s prefixing implicit in read_cpuid
arm64: enable CONFIG_DEBUG_RODATA by default
arm64: Rework valid_user_regs
arm64: mm: check at build time that PAGE_OFFSET divides the VA space evenly
arm64: KVM: Move kvm_call_hyp back to its original localtion
arm64: mm: treat memstart_addr as a signed quantity
arm64: mm: list kernel sections in order
arm64: lse: deal with clobbered IP registers after branch via PLT
arm64: mm: dump: Use VA_START directly instead of private LOWEST_ADDR
arm64: kconfig: add submenu for 8.2 architectural features
arm64: kernel: acpi: fix ioremap in ACPI parking protocol cpu_postboot
arm64: Add support for Half precision floating point
arm64: Remove fixmap include fragility
arm64: Add workaround for Cavium erratum 27456
arm64: mm: Mark .rodata as RO
...
Tronsmart Vega S95 Pro, Meta and Telos TV boxes.
- Add new DTS to enable support for the boards
- Add documentation for compatibles and vendor prefix
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW3W22AAoJELyGR0S84or4ijgQAMDR2a/sg9b9fzxFD8nH5BMn
HFGgIWc+JDhzUYdslaeBPadDiJGeKysekcs4dvOvtuOpL2bcDIjJSU07XsZavY/0
kUirDCMCDc7S0VSA2r7qgOBspaGWrYgYuc/P6ilwsiD+H7vOQIQkQtEn5wJU+pD5
rpFfg/0OjE27YFDmq+9WfZMf1AzNvkH17XyeozP/gZZa3PWqbdP0nkj0o9JxdTcG
WHwoq43OBOClGzufFWQQEnGzxR0n3hzqfCSU+spSBmoKFhhYqw8xtyIow9FFbMMR
oFQNFTfpVaJm/FqFsqcdplpMYHMUlLjFjWyVJWk48gyvl7mykdWTyHWgN7bETObJ
QKUQVYSzkgeQ4KTYWqfqLsa6PDlzt4zjzLqRzEb/3MvACX+zpFqSBH8rjobG/Her
EcHOE068lHj0bzi8Tohm0YzIvvnJLKeb8n9fJmPSnQzlBdTbKqh3Aps917ZTMbqt
/E2UWT0iSnNG4Ln3UG7rAnbg1xDHXL5YYX/D0r5h5ckD5v+ItsjlG4acehOuNkzb
rFMIoWwzfLFaYqJIjCvi7yNK5IfsppTqWIc/fhmOeXHnS5NtGIcmiQhReh8xac7u
N4Mn9ZP4hT/5xBk3MV/McX/qNdQkUmv9C+Kg7xb4GiqmA3q8TsjOnrYHj2tQxHSl
L1Fz8eeFQSRqWIBC+Y6a
=KmAy
-----END PGP SIGNATURE-----
Merge tag 'for-v4.6/gxbb-dt' of https://github.com/carlocaione/linux-meson into next/dt64
This series adds initial support for the Amlogic S905 based
Tronsmart Vega S95 Pro, Meta and Telos TV boxes.
- Add new DTS to enable support for the boards
- Add documentation for compatibles and vendor prefix
* tag 'for-v4.6/gxbb-dt' of https://github.com/carlocaione/linux-meson:
ARM64: dts: amlogic: Add Tronsmart Vega S95 configs
Documentation: devicetree: amlogic: Document Tronsmart Vega S95 boards
ARM64: dts: Prepare configs for Amlogic Meson GXBaby
Documentation: devicetree: amlogic: Document Meson GXBaby
devicetree: bindings: Add vendor prefix for Tronsmart
Signed-off-by: Olof Johansson <olof@lixom.net>
The compatible string "simple-bus" is well defined in ePAPR, while
I see no documentation for the "arm,amba-bus" arnywhere in ePAPR or
Documentation/devicetree/.
DT is also used by other projects than Linux kernel. It is not a
good idea to rely on such an unofficial binding.
This commit
- replaces "arm,amba-bus" with "simple-bus"
- drops "arm,amba-bus" where it is used along with "simple-bus"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Add support for SBSA Generic Watchdog on foundation models
2. Fix node name unit-address presence/absence mismatch warnings in
all the device trees
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJW3vnXAAoJEABBurwxfuKY1CcP/iGb7aS31UUOvmQzzFZg8hKq
Jgms1P1KGohD4cjN9DKWR4HOa/1s5LfEqifY92Y4BOmninWZdQmhUYJnUbFF6qT+
I4Z3Bs05RZGnMcaGM8zseWjk5C9cvtTAU/mAVpWtxqJnodVte0FtbFA/2E7N0hZU
Dh4sbK12CTYYnafZf9ilWo75TlE86OwSGHCprAFRIcypqDD6xsWU0c3gpFeLixxH
CHWe7m66IPO8C9wYBYzUHHumT275K2IZS05mV0yBpQWAZC4upQjt7GION5wSMvxT
DTqHSwRge0SL7zaj1YOP6MpRApYXhFpRr8nSsdU84H4TlvxgyMzzSqet4Ou1W4He
lE9RaHk9ISreeqb+7cLv4sDz1R4h+PrxE5GknC/+WR9bvXhdN8DS75y9zT3HACiE
W1glLb+5B7cR/hr0Otbm7iEB0WickLtCLdQ6usAkqBOmFI0VaOGJeod1oRWrFh8Z
TQ2csrhE073akutdOEnVCTzHO94BR3ElYHAVYmdnvNMgeinrd1C+2I5Ce0rs4BIT
OoMPA8ed11dASj4p496qIL7Stkzd3sYV72vQKV+EOk8m8i2YjkSbBj9aEWdDzzI5
o9pvNHA1Bts84nc0SVa2a7XDI/RFxREUBwUVhFieSA2PRJSL+YVvpPSwVBNnuFWq
cE681DOj4e9RBsW74WgU
=uO7I
-----END PGP SIGNATURE-----
Merge tag 'vexpress-for-v4.6/dt-updates-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt
Additional updates for ARM VExpress/Juno platforms
1. Add support for SBSA Generic Watchdog on foundation models
2. Fix node name unit-address presence/absence mismatch warnings in
all the device trees
* tag 'vexpress-for-v4.6/dt-updates-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno/vexpress: fix node name unit-address presence warnings
arm64: dts: foundation-v8: add SBSA Generic Watchdog device node
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Remove separate ARCH_EXYNOS7 symbol and consolidate it into
one ARCH_EXYNOS.
This depends on clk tree: removal of last presence of ARCH_EXYNOS7.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJWz5PsAAoJEME3ZuaGi4PX49cP/jhU8jtgdXvzysVITUPi5Ukv
Rl82rmCrrX//z6n2LpHaqG/bg1ynOeaRa8TLYU/4gQ53fORmk4UgtqNvC54/2+KX
2CNdNko85oX7DIc2nr5RwTNEBspYh0lTvChZtzQqoKVRdMJSiv2Ms5FcnMNYDt5q
xGlQoriTCzlZjt2q6hjlmSZgy8RIn1EeiwsnP3DzmdiX+POgpItfwKln9Ci7E+oz
xGa4N/rdQOA0MeV/wizDyWcaCi8HJSDQfMBq6rvx/NtYSGmJORUggFjmmhfp6wAr
tuVMflDX20ZoDrP5XptbHapoTtOpQny/D7TiFhWvNZc59zpLei1GJOUOhWdq1PVH
om2D59GZ+cNEzDSM/frJiT7VzB32/d479T8DfrwzUahDC2bj+yDPfSK73T72cERs
/eBORjYrjM3h9IEwB4DbE6QrxHondXw3B2PQLq4+40w2sE4efupkiBn6vVKUIT9S
Za2n6l1W1D2XQawz37Ya2/rAybkMaTIURgsRXE/Oe7GKz11pS3oRmYSeDWcOnMsw
PnVL6uTz5zAtoVRygkRVmPv0JUzZgxlNMKfHy7O1zzhSLBtNwXtzGRNyFO+k1yIk
FoWly5/o0mYvW+yU1i5lgBi9Zh5aB5Guq7qsqMoGgDC18u7v+GGAcFhNtwKAXUPy
UDf3Ut2RSTitQnyNyl5m
=XcED
-----END PGP SIGNATURE-----
Merge tag 'samsung-soc64-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/arm64
Samsung Exynos ARM64 improvements for v4.6:
1. Remove separate ARCH_EXYNOS7 symbol and consolidate it into
one ARCH_EXYNOS.
This depends on clk tree: removal of last presence of ARCH_EXYNOS7.
* tag 'samsung-soc64-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS
clk: samsung: Don't build ARMv8 clock drivers on ARMv7
clk: samsung: Enable COMPILE_TEST for Samsung clocks
clk: Move vendor's Kconfig into CCF menu section
clk: mediatek: Fix memory leak on clock init fail
clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h
clk: xgene: Remove return from void function
clk: xgene: Add SoC and PMD PLL clocks with v2 hardware
Documentation: Update APM X-Gene clock binding for v2 hardware
clk: s2mps11: remove redundant code
clk: s2mps11: remove redundant static variables declaration
clk: s2mps11: allocate only one structure for clock init
clk: s2mps11: merge two for loops in one
clk-divider: make sure read-only dividers do not write to their register
clk: tango4: rename ARCH_TANGOX to ARCH_TANGO
clk: scpi: Fix checking return value of platform_device_register_simple()
clk: mvebu: Mark ioremapped memory as __iomem
Signed-off-by: Olof Johansson <olof@lixom.net>
Add support for the Armada 7K and 8K SoCs and the Armada 8040 DB board
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlbQX0wACgkQCwYYjhRyO9V9nwCgqk3LOUVjtyjGxd4YU8iHzEBe
B+oAoKMMiTTb/yqcwMdN+l1B5RMOxW4o
=fs9N
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-4.6-2' of git://git.infradead.org/linux-mvebu into next/dt64
mvebu dt64 for 4.6 (part 2)
Add support for the Armada 7K and 8K SoCs and the Armada 8040 DB board
* tag 'mvebu-dt64-4.6-2' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: re-order Device Tree nodes for Armada AP806
arm64: dts: marvell: update Armada AP806 clock description
arm64: dts: marvell: add Device Tree files for Armada 7K/8K
Signed-off-by: Olof Johansson <olof@lixom.net>
Commit fa38a82096a1 ("scripts/dtc: Update to upstream version
53bf130b1cdd") added warnings on node name unit-address presence/absence
mismatch in device trees.
This patch fixes those warning on all the juno/vexpress platforms where
unit-address is present in node name while the reg/ranges property is
not present. It also adds unit-address to all smb bus node.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This can be a example of adding SBSA Generic Watchdog device node
into some dts files for the Soc which contains SBSA Generic Watchdog.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Fu Wei <fu.wei@linaro.org>
[edited subject and moved change to dtsi file]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Add Device Trees for Tronsmart Vega S95 Pro, Meta and Telos TV boxes.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Carlo Caione <carlo@endlessm.com>
This patch set includes:
+ A change in compatible string of X-Gene v2 SoC
PLL DT node to reflect the v2 hardware
+ Update DT fields for X-Gene v1 and v2 standby
GPIO controllers
+ Update declaration of power button GPIO for
X-Gene v1 and X-Gene v2 platforms
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJWz64GAAoJEB11UG/BVQ/gv9EQAInTeIVKnzsmUwBrP0EKxq3H
T1scbrUMhRsOfCQc04xJFt35c684IdvI9chVMtIe1QZZaDQYRbfj/TjZxqOZRxSw
/gU/QnFM2R6G41Pnu8UxFFp1oMJGob8mcDKFgmNa30+a9Qsd0mXt0q9qjtTIwlCK
pg3vvpiAUlqBlREel8ahhF+NZ9k/ubMVa8NQGyLridpDtm27J6eCe3zWCX7WhQY/
lqIVUiCtpb3lNRxaV1zgzlmci1r24pdUKc46GkswxlAdrHwtqZY/AQkdkuhZdQ3t
0JM1x3/TI6MmQk7nRYVlYV7W/yhQotyMm+o1csO4I/Jk6SNpUVGLHF5BtfMaNXT9
bEz42gq+3qUn6m9NI7afjokfXNpH9mnfpAzP9ckuHFU2uG23cNXM1ciXFV4b6r07
Vep7eAS6/cOTsWkYKQ0vkOzz7H279oAtyZ5FMubx7xX+GLRsoKDOfvJOL5fFhLoo
vJ3+0AxQQ1EAYfGVj3b5Q9mKsCdVKZro6e41WAzZCwDNwE7siz7PpCXRkJuUrOJR
wlkQVbu/gH0G82MzZjMlzwqGP5+kWeipgUKJecqw2wwaClMeH7268pw8ffvDAnCh
pFRGqEo1xfLiLbwUny9Wnoa5/PnRD4yDstq2x/6Rf5sxFIrs7JG5R6ZbNtEagSAO
fChptrHeqEB3Mkxtw3oU
=ASg+
-----END PGP SIGNATURE-----
Merge tag 'xgene-dts-for-v4.6-part1' of https://github.com/AppliedMicro/xgene-next into next/dt64
Merge "First part of X-Gene DT changes queued for v4.6" from Duc Dang:
This patch set includes:
+ A change in compatible string of X-Gene v2 SoC
PLL DT node to reflect the v2 hardware
+ Update DT fields for X-Gene v1 and v2 standby
GPIO controllers
+ Update declaration of power button GPIO for
X-Gene v1 and X-Gene v2 platforms
* tag 'xgene-dts-for-v4.6-part1' of https://github.com/AppliedMicro/xgene-next:
arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platforms
arm64: dts: apm: Update GPIO standby controller DT node for X-Gene v2 platforms
arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platforms
arm64: dts: apm: Update X-Gene standby GPIO controller DTS entries
arm64: dts: apm: Update Merlin DT PCP PLL clock node for v2 hardware
The qcom-spmi-mpp driver is now using string "digital" to denote
old "normal" functionality. Update DTS file.
Also update the powersource.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Merge "Broadcom soc-arm64 changes for 4.6" from Florian Fainelli:
This pull request contains Broadcom ARM64-based SoC/platform changes:
- Anup, Ray and Dhanajay enable COMMON_CLK_IPROC, PINCTRL and GPIOLIB for iProc
SoCs to get the corresponding iProc-based drivers to be available and work
- Zi adds support for Broadcom's Vulcan processor by adding a reference
board Device Tree file along with a config ARCH_VULCAN symbol
- Jayachandran C. adds the Broadcom implementor ID and part ID for the Vulcan
processors
* tag 'arm-soc/for-4.6/soc-arm64' of http://github.com/Broadcom/stblinux:
arm64: cputype info for Broadcom Vulcan
arm64: Broadcom Vulcan support
arm64: Select COMMON_CLK_IPROC, PINCTRL and GPIOLIB for iProc SoCs
Merge "Broadcom devicetree-arm64 changes for 4.6" from Florian Fainelli:
This pull request contains Broadcom ARM64-based SoCs device tree changes:
- Anup adds additional nodes to the Broadcom Northstart 2 Device Trees: SDHCI
(iProc-compatible), ARM SP804 timers, ARM SP805 watchdog
- Anup also adds a binding documentation for the ARM SP805 watchdog since there
was not one in tree before
- Ray adds PCIE root complex nodes to the Northstar 2 Device Tree nodes, using
the iProc-compatible binding
- Jayachandran C. adds binding documentation for the Broadcom Vulcan processors and
reference platforms
* tag 'arm-soc/for-4.6/devicetree-arm64' of http://github.com/Broadcom/stblinux:
dt-bindings: Add documentation for Broadcom Vulcan
arm64: dts: Add PCIe0 and PCIe4 DT nodes for NS2
arm64: dts: Add ARM SP805 watchdog DT node for NS2
dt-bindings: watchdog: Add ARM SP805 DT bindings
arm64: dts: Add ARM SP804 timer DT nodes for NS2
arm64: dts: Add SDHCI DT node for NS2
Following the addition of the Alpine MSIX controller driver, add the
corresponding node in the Alpine v2 device tree.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Extract clock information from EP108
- Sort GPIO node
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlbO/SIACgkQykllyylKDCEL9QCfdcFczSmk3OWvubtp1/d7YoMs
MhoAn33UBIqTGcmYgpRljfhWWStW1eRE
=wlZ0
-----END PGP SIGNATURE-----
Merge tag 'zynqmp-dt-for-4.6' of https://github.com/Xilinx/linux-xlnx into next/dt64
Merge "ARM: Xilinx ZynqMP dt patches for v4.6" from Michal Simek:
- Extract clock information from EP108
- Sort GPIO node
* tag 'zynqmp-dt-for-4.6' of https://github.com/Xilinx/linux-xlnx:
ARM64: zynqmp: Extract clock information from EP108
ARM64: zynqmp: Keep gpio node alphabetically sorted
The DT nodes representing the XOR engines were not placed at the
proper location to comply with the requirement of ordering DT nodes by
their unit address. This commit fixes this mistake.
[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:']
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Following the review from the DT maintainers, the DT binding for the
clocks has changed, and we now use a DFX server node exposing a
syscon, with the clock nodes being subnodes of the DFX server
node. This commit therefore updates the AP806 Device Tree file to use
this new DT binding.
[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:']
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit adds the base Device Tree files for the Armada 7K and 8K
SoCs, as well as the Armada 8040 DB board.
The Armada 7020, 7040 (7K family) and 8020, 8040 (8K family) are
composed of:
- An AP806 block that contains the CPU core and a few basic
peripherals. The AP806 is available in dual core configurations
(used in 7020 and 8020) and quad core configurations (used in 8020
and 8040).
- One or two CP110 blocks that contain all the high-speed interfaces
(SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP110,
and the 8K family chips have two CP110, giving them twice the
number of HW interfaces.
In order to represent this from a Device Tree point of view, this
commit creates the following hierarchy:
* armada-ap806.dtsi - definitions common to dual/quad ap806
* armada-ap806-dual.dtsi - description of the two CPUs
* armada-7020.dtsi - description of the 7020 SoC
* armada-8020.dtsi - description of the 8020 SoC
* armada-ap806-quad.dtsi - description of the four CPUs
* armada-7040.dtsi - description of the 7040 SoC
* armada-7040-db.dts - description of the 7040 board
* armada-8040.dtsi - description of the 8040 SoC
The CP110 blocks are not described yet, and will be part of future
patch series.
[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:']
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This patch updates gpio-keys node that supports power-off for
X-Gene v2 Merlin board to adapt with new changes in xgene-gpio-sb
driver (to support configuring some GPIO pins as interrupt pins).
Signed-off-by: Quan Nguyen <qnguyen@apm.com>
Signed-off-by: Duc Dang <dhdang@apm.com>
xgene-gpio-sb driver now supports configuring some GPIO pins
as interrupt pins. This patch adds the required fields for GPIO
standby controller DT node of X-Gene v2 platform to work with
this new driver change.
Signed-off-by: Quan Nguyen <qnguyen@apm.com>
Signed-off-by: Duc Dang <dhdang@apm.com>
This patch updates gpio-keys node that supports power-off for
X-Gene v1 Mustang board to adapt with new changes in xgene-gpio-sb
driver (to support configuring some GPIO pins as interrupt pins).
Signed-off-by: Duc Dang <dhdang@apm.com>
We should set SW15 to pin 2-3 side on the board before we use CN9
as USB host or peripheral.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This board has a MAX3355 chip. However, we cannot use the extcon/max3355
driver because the ID pin doesn't connect to a gpio pin (in other words,
it connects to the SoC specific pin).
And, the phy-rcar-gen3-usb2 driver cannot handle such a chip for now.
So, this patch enables usb2_phy of channel 1 and 2.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the exposed SD card slots. The on-board eMMC needs to wait until we
fixed the 8bit support.
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[wsa: squashed some fixes and added mmc-caps]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch updates the digital voltage levels from corner values to
microvolts as we are going to use s1 regulator directly for vddcx
instead of s1_corner.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
This patch enables the lpass on DB410C. LPASS is used as cpu dai for
both analog and digital audio.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
This patch adds manual pull up setting for usb otg indicating that the
vbus is vbus is not routed to USB controller/phy therefore enables
pull-up explicitly before starting controller.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
This patch add the iommu/larbs nodes for mt8173
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
This patch adds poweroff button device node to support
poweroff feature on hip05 d02 board.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
There are two dw GPIO controllers in hip05 peri sub, this patch
adds the corresponding device tree nodes.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
There are four subsystems in hip05 soc, peri/m3/pcie/dsa,
each subsystem has one its, append them under gicv3 node.
They will be used by hisilicon mbigen.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Instead of using the generic armv8-pmuv3 compatibility, use
the more specific Cortex A57 compatibility.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus
share one L2 cache, add them to the dtsi file so that the cache
hierarchy can be probed.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Device tree part of the Armada 3700 support:
- binding for the Armada 3700 SoCs
- device tree files for the SoCs and a board
- tidy up the Marvell related files
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlbEltYACgkQCwYYjhRyO9UZxACgi1NcAIrem831BSMOHVRBphAB
qT8An3bCV/tPx2QYz0kKYmGfyb7VtTzo
=IdEY
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-4.6-1' of git://git.infradead.org/linux-mvebu into next/dt64
mvebu dt64 for 4.6 (part 1)
Device tree part of the Armada 3700 support:
- binding for the Armada 3700 SoCs
- device tree files for the SoCs and a board
- tidy up the Marvell related files
* tag 'mvebu-dt64-4.6-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: add the Marvell Armada 3700 family and a development board
devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC family
Documentation: dt: Tidy up the Marvell related files
Documentation: dt-bindings: Add a new compatible for the Armada 3700
Signed-off-by: Olof Johansson <olof@lixom.net>
The patch adds LS2085a to PCIe compatible to fix the compatibility
issue when using firmware with LS2085a compatible property.
Signed-off-by: Minghuan Lian <minghuan.lian@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This is a fix-up patch based on the review comment from
Arnd regarding:
* fix ccn504 address in the node name
* remove kcs interrupt-name
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
gpio-key,wakeup to the more generic wakeup-source property.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCAAGBQJWuwVbAAoJEPOmecmc0R2B5b4H/j869d1n99jqv+we15c0B87e
bYjNk9UKW4me+rrpU4PLBVyj15KYj+otAS/aB9S5Z+GckRWHLIB4FppE+cCyqAvb
jmLle+vrMcni23AfbVB9nBzcx/PpE+G0NB9s/PDo07B4MxpeShvYDCW/x3u7ak2r
VotY8hqp3SI7JVXskknmiJtaxA9RI+CpVPucBJ6SZL5CYFgLSYqo0JiW7ArRWoeb
/vdbmMN+9CwbYAaWPzkVgPvCTNqsKJeP3K05u+zxOqV++YIva8H2Ml59euxC3CsY
0IssrCVb0iwlBEF+Lxya/tJJe7lZ5iTcjfE/NMI4lmxvFTUFNMKt8v79kLIKEx0=
=+Sh9
-----END PGP SIGNATURE-----
Merge tag 'v4.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
Define the tuning-related mmc clocks and move from
gpio-key,wakeup to the more generic wakeup-source property.
* tag 'v4.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: replace gpio-key,wakeup with wakeup-source property
arm64: dts: rockchip: add rk3368 tuning clk for emmc and sdmmc
Signed-off-by: Olof Johansson <olof@lixom.net>
1. GICv3 support on Foundation models
2. Support for Juno R2 board
3. Support for ARM HDLCD on all Juno platforms
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJWuxfzAAoJEABBurwxfuKYF3cP/0rJX1WsVPtJZthVoA0+elTp
ruRl2vnzxnlrGG93dpWH3HKx4o56En9AIwKHacHkVKcfoSsC3YSTFS3KD34eweFy
GYJQxtK+eEXZnR3zxbDpyaj2bo/VqFHULB1o8WXJWSs5IAhS4eKeWLoDe/38AsV7
GXKjoL7Gxi3znS+fZObUwBKrLSUGEgEMJp4I0tX7T1GE0sCPg5aW+ApoHfD4HYC6
LgKaRuKfaJNrjDETIQ2TqSUuwJobT/xoYjSGPr2cMthBfPUvACXu7+fBFwpfmHct
EAmNnxBI6f3RuuDuxCFATIMfPPOrEslyFCYBcWhwOtl0r1Y6rq+J/P9AYB3xRqYG
KzYN33Wo87wwn8y0TULXkRrs9s0WddtulgmH/IrSKby7w7U4sCGmMcNv37kjCRGJ
oKsSKSAag3g7kBAJEFP4X7tMwG2tl4koUmWvyZO2ihsXt1tHUYQcBLzUdw1N/pNk
hkQjOr1BRLgEYh451QdBDzcV+QBTgDe3DaG6WpI6RNFuGnKYsqaCyh5qiZGCbvD4
7dGquR+EBakaEEKjzVIqTva77SB0ZwVAsNgPbgXK0ibqfGuWSQq58GqwWh4Nv0cf
Xzfihicwsak6swohmn6n5/u3gywekOsoHd1OVrb24cfFHLXcqaLOz7Rs+sFZp93v
bxHKj68IUAhzU+awmPB9
=r0q6
-----END PGP SIGNATURE-----
Merge tag 'vexpress-for-v4.6/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt
Few updates for ARM VExpress/Juno platforms
1. GICv3 support on Foundation models
2. Support for Juno R2 board
3. Support for ARM HDLCD on all Juno platforms
* tag 'vexpress-for-v4.6/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: Add HDLCD support on Juno platforms
Documentation: drm: Add DT bindings for ARM HDLCD
arm64: dts: Add support for Juno r2 board
arm64: dts: move juno pcie-controller to base file
arm64: dts: add .dts for GICv3 Foundation model
arm64: dts: split Foundation model dts to put the GIC separately
arm64: dts: Foundation model: increase GICC region to allow EOImode=1
arm64: dts: prepare foundation-v8.dts to cope with GICv3
Signed-off-by: Olof Johansson <olof@lixom.net>
Add the RPM Clock Controller DT node and include the necessary header
file for clocks.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The #size-cells for the pmics are 0, but we specify a size in the
reg property so that MPP and GPIO modules can figure out how many
pins there are. Now that we've done that by counting irqs, we can
remove the size elements in the reg properties and be DT
compliant.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add #power-domain-cells property for both the gcc and mmcc
clock controller nodes as they both supports power domains (gdsc's)
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds real regulators and pinctrl nodes for sdhc_1.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
To be consistent with other nodes move sdhci node under the soc node,
rather than using lable references.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
96boards mezzanine boards on LS expansion require 1.8v as per 96boards
specifications, so enable the corresponding regulators and make them
always-on.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds label to smd rpm regulators so that the board level file
can use the label directly to populate the regulators, rather than
having deep nesting.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
s2 is spmi controller regulator on msm8916 according to downstream 3.10
kernel, so remove it from the dt to avoid confusion an use of it.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2mA drive strenght is not enough to drive chipselect low on hardware
configurations with level shifters, 16mA should give good range to
allow such configurations to work.
This issue was noticed while testing spi on db410c with sensor board.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch removes redundant pins from spi pinconf as these are already
specified in pinconf_cs.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds aliases to spi device so that it can get proper bus
number rather than a random number.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The msm8916 SoC has an L2 cache for all 4 CPUs. Add it to the
dtsi file so that the cache hierarchy can be probed.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Use the standard name for clock controller nodes instead of a
qcom specific name.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the gpio and MPP devices to the pm8994 pmic dts.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the skeleton nodes for the PMICs found on msm8996-mtp
devices.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add initial device tree support for the Qualcomm MSM8996 SoC and
MTP8996 evaluation board.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Conflicts:
drivers/net/phy/bcm7xxx.c
drivers/net/phy/marvell.c
drivers/net/vxlan.c
All three conflicts were cases of simple overlapping changes.
Signed-off-by: David S. Miller <davem@davemloft.net>
The ARMv8 Exynos family SoCs in Linux kernel are currently:
- Exynos5433 (controlled by ARCH_EXYNOS),
- Exynos7 (controlled by ARCH_EXYNOS7).
It duplicates Kconfig symbols unnecessarily, so consolidate them into
one ARCH_EXYNOS. Future SoCs could fall also under the ARCH_EXYNOS
symbol.
The commit should not bring any visible functional change.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Andi Shyti <andi.shyti@samsung.com>
Add a configuration option and a device tree for Broadcom's Vulcan
ARM64 processor. vulcan.dtsi has the on-chip blocks like the PCIe
controller, GICv3 with ITS, PMU, system timer and the pl011 UART.
vulcan-eval.dts has definitions for a basic evaluation board.
Vulcan's processor cores support the ARMv8.1 instruction set and
will use "brcm,vulcan" as the compatible property. The firmware
has PSCI 0.2 support for cpu wakeup.
Signed-off-by: Zi Shen Lim <zlim@broadcom.com>
[ updated and split dts - jchandra@broadcom.com ]
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
MT8173 E1 chip has one bug that if turn off USB power domain, vcore
power will also be off, thus cause modules using vcore power domain
fail, like MMC. The E1 chip only found on MT8173-evb board and this
board only has E1 chip, so implement this as a board specific
workaround.
Pwrapper use vcore power, so add pwrapper using USB power domain to
keep USB power domain not to zero and disabled.
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Besides the distributor and the CPU interface the GIC-400 additionally
supports the virtual interface control blocks and the virtual CPU interfaces.
Add the physical base addresses and size for these.
See
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0471b/index.html
-> 3.2. GIC-400 register map
and Linux kernel's
Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
for more details.
For the at GICH Virtual interface control blocks at 0xf1040000 cover the
whole 128kB (0x20000) range. This is done based on the advice from Marc
Zyngier http://www.spinics.net/lists/arm-kernel/msg483139.html
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add initial dtsi files to support Marvell Armada 3700 SoC with Cortex-A53
CPUs. There are two members in this family: the Armada 3710 (Single CPU)
and the Armada 3720 (Dual CPUs).
It also adds a dts file for the Marvell Armada 3720 DB board.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add a single r8a7795 INTC-EX device node to support
external IRQ pins IRQ0 -> IRQ5.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a device node for the Cortex-A53 L2 cache-controller.
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the missing "cache-unified" and "cache-level" properties to the
Cortex-A57 cache-controller node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Use GIC_* defines for GIC interrupt cells in r8a7795 device tree.
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add "snps,quirk-frame-length-adjustment" property to USB3 node for
erratum A009116. This property provides value of GFLADJ_30MHZ for post
silicon frame length adjustment.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add "snps,quirk-frame-length-adjustment" property to
USB3 node for erratum A009116. This property provides
value of GFLADJ_30MHZ for post silicon frame length
adjustment.
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch enables PCIe0 and PCIe4 for NS2 by adding
appropriate DT nodes in NS2 DT.
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
We have one ARM SP805 watchdog instance on NS2 for non-secure software
hence this patch adds appropriate watchdog DT node in NS2 DT.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Pramod KUMAR <pramodku@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
We have four ARM SP804 dual-mode timer instances in NS2 SoC
hence this patch adds appropriate DT nodes for NS2.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Pramod KUMAR <pramodku@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The IPROC SDHCI driver works fine for SDIO 3.0 on NS2 so let's enable
it for NS2 SoC in NS2 DT.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
ARM's Juno platforms have two HDLCD controllers, each linked to an NXP
TDA19988 HDMI transmitter that provides output encoding. Add them
to the device tree.
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
Keyboard driver for GPIO buttons(gpio-keys) checks for the legacy
"gpio-key,wakeup" boolean property to enable gpio buttons as wakeup
source.
Few dts files assign value "1" to gpio-key,wakeup and in one instance a
value "0" is assigned probably assuming it won't be enabled as a wakeup
source. Since the presence of the boolean property indicates it is
enabled, value of "0" have no value.
This patch replaces the legacy "gpio-key,wakeup" with the unified
"wakeup-source" property which inturn fixes the above mentioned issue.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The PCIe controller is found on all Juno SoC version. However it's not
functional on R0 due to some hardware bug.
In preparation to add Juno R2 support, this patch moves the
pcie-controller defination to base DTS file. It's marked as disabled by
default and is enabled for Juno R1 explicitly.
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The ARMv8 Foundation model sports a command line parameter to use
a GICv3 emulation instead of the default GICv2 interrupt controller.
Add a new .dts file which reuses most of the definitions of the
existing model while just adding the required properties for the
GICv3 node.
This allows the public Foundation model to run with a GICv3.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The ARMv8 Foundation model can be run with a GICv2 or a GICv3.
To prepare for the GICv3 version of the .dts without code duplication,
move most of the nodes of the existing DT (except the GIC) into an
include file and just keep that include statement and the GIC node in
the current foundation-v8.dts.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The Foundation model GIC mapping is wrong, as the GICC region should
be 8kB instead of 4kB (the model implements the GICv2 architecture).
This defect prevents the driver from switching to EOImode==1.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
To prepare the ARM foundation model to support GICv3, we adjust
the #address-cells property of the current GICv2 node to be
compatible with the two cells required for GICv3 later.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Add device tree file for AMD/Linaro 96Boards Enterprise Edition Server
(Husky) Board. This is based on the AMD Seattle Rev.B0 system
Signed-off-by: Leo Duran <leo.duran@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add device tree files for AMD Overdrive boards which comes with
AMD Seattle Revision B0 and B1 SOCs.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add AMD XGBE device tree file, which is available in AMD Seattle RevB.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add new GPIO device nodes and fix clock on gpio0.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add new SATA1 device node, and fix the register range size of SATA0.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
