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Merge tag 'arm-soc/for-4.6/soc-arm64' of http://github.com/Broadcom/stblinux into next/arm64
Merge "Broadcom soc-arm64 changes for 4.6" from Florian Fainelli: This pull request contains Broadcom ARM64-based SoC/platform changes: - Anup, Ray and Dhanajay enable COMMON_CLK_IPROC, PINCTRL and GPIOLIB for iProc SoCs to get the corresponding iProc-based drivers to be available and work - Zi adds support for Broadcom's Vulcan processor by adding a reference board Device Tree file along with a config ARCH_VULCAN symbol - Jayachandran C. adds the Broadcom implementor ID and part ID for the Vulcan processors * tag 'arm-soc/for-4.6/soc-arm64' of http://github.com/Broadcom/stblinux: arm64: cputype info for Broadcom Vulcan arm64: Broadcom Vulcan support arm64: Select COMMON_CLK_IPROC, PINCTRL and GPIOLIB for iProc SoCs
This commit is contained in:
Arnd Bergmann
commit
ebb7c983b5
@ -9,6 +9,9 @@ config ARCH_ALPINE
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config ARCH_BCM_IPROC
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bool "Broadcom iProc SoC Family"
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select COMMON_CLK_IPROC
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select PINCTRL
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select ARCH_REQUIRE_GPIOLIB
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help
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This enables support for Broadcom iProc based SoCs
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@ -145,6 +148,11 @@ config ARCH_VEXPRESS
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This enables support for the ARMv8 software model (Versatile
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Express).
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config ARCH_VULCAN
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bool "Broadcom Vulcan SOC Family"
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help
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This enables support for Broadcom Vulcan SoC Family
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config ARCH_XGENE
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bool "AppliedMicro X-Gene SOC Family"
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help
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@ -1,4 +1,5 @@
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dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb
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dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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33
arch/arm64/boot/dts/broadcom/vulcan-eval.dts
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33
arch/arm64/boot/dts/broadcom/vulcan-eval.dts
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@ -0,0 +1,33 @@
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/*
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* dts file for Broadcom (BRCM) Vulcan Evaluation Platform
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*
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* Copyright (c) 2013-2016 Broadcom
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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/dts-v1/;
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#include "vulcan.dtsi"
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/ {
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model = "Broadcom Vulcan Eval Platform";
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compatible = "brcm,vulcan-eval", "brcm,vulcan-soc";
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memory {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
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<0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */
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};
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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144
arch/arm64/boot/dts/broadcom/vulcan.dtsi
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144
arch/arm64/boot/dts/broadcom/vulcan.dtsi
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@ -0,0 +1,144 @@
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/*
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* dtsi file for Broadcom (BRCM) Vulcan processor
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*
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* Copyright (c) 2013-2016 Broadcom
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* Author: Zi Shen Lim <zlim@broadcom.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Broadcom Vulcan";
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compatible = "brcm,vulcan-soc";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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/* just 4 cpus now, 128 needed in full config */
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "brcm,vulcan", "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "brcm,vulcan", "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "brcm,vulcan", "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "brcm,vulcan", "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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gic: interrupt-controller@400080000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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#redistributor-regions = <1>;
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reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */
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<0x04 0x01000000 0x0 0x1000000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gicits: gic-its@40010000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */
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};
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clk125mhz: uart_clk125mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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clock-output-names = "clk125mhz";
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};
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pci {
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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#interrupt-cells = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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/* ECAM at 0x3000_0000 - 0x4000_0000 */
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reg = <0x0 0x30000000 0x0 0x10000000>;
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reg-names = "PCI ECAM";
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/* IO 0x4000_0000 - 0x4001_0000 */
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ranges = <0x01000000 0 0x40000000 0 0x40000000 0 0x00010000
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/* MEM 0x4800_0000 - 0x5000_0000 */
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0x02000000 0 0x48000000 0 0x48000000 0 0x08000000
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/* MEM64 pref 0x6_0000_0000 - 0x7_0000_0000 */
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0x43000000 6 0x00000000 6 0x00000000 1 0x00000000>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map =
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/* addr pin ic icaddr icintr */
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<0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&gicits>;
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dma-coherent;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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uart0: serial@402020000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x04 0x02020000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk125mhz>;
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clock-names = "apb_pclk";
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};
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};
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};
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@ -65,6 +65,7 @@
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#define ARM_CPU_IMP_ARM 0x41
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#define ARM_CPU_IMP_APM 0x50
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#define ARM_CPU_IMP_CAVIUM 0x43
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#define ARM_CPU_IMP_BRCM 0x42
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#define ARM_CPU_PART_AEM_V8 0xD0F
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#define ARM_CPU_PART_FOUNDATION 0xD00
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@ -75,6 +76,8 @@
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#define CAVIUM_CPU_PART_THUNDERX 0x0A1
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#define BRCM_CPU_PART_VULCAN 0x516
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#ifndef __ASSEMBLY__
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/*
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