- A series of changes for dra7 and am572 to use generic
MMC vqmmc regulator
- Clean-up tps65217 internal interrupts to define them
only in tps65217.dtsi
- Add dra7 iodelay pinctrl driver configuration
- Add buzzer support for am437x-gp-evm
- Disable HDMI CEC internal pull-ups as it seems that
all boards have an external pull for these
- Remove unnecessary interrupt-parent for omap3
- Configure droid 4 vaudio regulator initial mode and
add vibrator
- Enable NAND dma prefetch for am335x-evm, am437x and dra7
- Add pcie1 dt node for EP mode for am57x and dra7
- Add support for new dra76x SoCs and dra76x-evm
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlmTJfQRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXNA1A/+MLAg3q4K9IKWGTXbus9yBoKk8w2WFbSs
Yz/tzzOaNNhXdv3JdXh3f8O8wpID8LnxSblM001olks7Q9KSHMSyd0MUm4SgEQk2
hyFnEZU3e1eAe86LEDMTJNnKLLdCx3+RZHLvaRy3iHVIWBVZQmwD4l5daCt6iA0N
Yoy77MHkgJ0hnFrvcXr3e5+UzZR4g0JvS0T63sEQ5FbX6Uf4NTp67ubTYN3d/Zb9
E+GhPiNsOPeecVzDZR/C1eT7xasBf7qEl9qfJlglVPV8cVsZ6FUzsQb/aYixKaO2
fw1spQ3dpG9Scoi1AlU8AjapZXq8ocwS57L4kXRzlkm8ce6fj8a0aChX3jGKJMNx
RPdfjRRUOjvQt5Jg1VCh1J3Rr6xtQv05fkcowHfyVrhVxIa/mlnFv2qIb6N4u+Ra
nXIYTiBxxwHeiy/nwz+mjcvbOe12Jj9E7DAidrxxr/cpNeRbZMz9w5vI2rJ3sUbK
+DYWTVMhE0+TYZIFNPRM8tEyem/3omrpIQyM2K4IYk/E2b0aMF6UXlJP+i8dvL8o
01Ad2Gzr/Z9seD0YrhYJVM+LmR/qOn/10gKmtznOKM2trGxb4suq3mdSx/RMmneC
gGl0ltudVh0s1jWts/51H+BDYZ2J3DbJRDJAahIAkVEBfQCl6LRjyO4goi+SCaLq
z8out2VsHA0=
=zikX
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.14/dt-v3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Pull "Device tree changes for omaps for v4.14 merge window" from Tony Lindgren:
- A series of changes for dra7 and am572 to use generic
MMC vqmmc regulator
- Clean-up tps65217 internal interrupts to define them
only in tps65217.dtsi
- Add dra7 iodelay pinctrl driver configuration
- Add buzzer support for am437x-gp-evm
- Disable HDMI CEC internal pull-ups as it seems that
all boards have an external pull for these
- Remove unnecessary interrupt-parent for omap3
- Configure droid 4 vaudio regulator initial mode and
add vibrator
- Enable NAND dma prefetch for am335x-evm, am437x and dra7
- Add pcie1 dt node for EP mode for am57x and dra7
- Add support for new dra76x SoCs and dra76x-evm
* tag 'omap-for-v4.14/dt-v3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (25 commits)
ARM: dts: nokia n900: update dts with camera support
ARM: dts: Add support for dra76-evm
ARM: dts: Add support for dra76x family of devices
ARM: dts: DRA7: Add pcie1 dt node for EP mode
ARM: dts: am335x: add support for Moxa UC-8100-ME-T open platform
ARM: dts: dra7xx: Enable NAND dma prefetch by default
ARM: dts: am437xx: Enable NAND dma prefetch by default
ARM: dts: am335x-evm: Enable NAND dma prefetch by default
ARM: dts: omap4-droid4: Add vibrator
ARM: dts: motorola-cpcap-mapphone: set initial mode for vaudio
ARM: dts: omap3: Remove needless interrupt-parent property
ARM: dts: Disable HDMI CEC internal pull-ups
ARM: dts: am437x-gp-evm: Add support for buzzer
ARM: dts: Add dra7 iodelay configuration
ARM: dts: tps65217: Add power button interrupt to the common tps65217.dtsi file
ARM: dts: tps65217: Add charger interrupts to the common tps65217.dtsi file
ARM: dts: omap*: Replace deprecated "vmmc_aux" with "vqmmc"
ARM: dts: am572x-idk: Fix GPIO polarity for MMC1 card detect
ARM: dts: am571x-idk: Fix GPIO polarity for MMC1 card detect
ARM: dts: dra7: Add "max-frequency" property to MMC dt nodes
...
Add arm_global_timer node on Armada 38x
Fix PCI bus dtc warnings on mvebu 32 bits device tree files
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlmNhZUACgkQCwYYjhRyO9VwCACgpK2SLzw3pfmFMpaRZqPf7yqQ
eVoAmwf/qVDF+pPs8GIzyxyBJP7C27SR
=9oc8
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt-4.14-1' of git://git.infradead.org/linux-mvebu into next/dt
Pull "mvebu dt for 4.14 (part 1)" from Gregory CLEMENT:
Add arm_global_timer node on Armada 38x
Fix PCI bus dtc warnings on mvebu 32 bits device tree files
* tag 'mvebu-dt-4.14-1' of git://git.infradead.org/linux-mvebu:
ARM: dts: armada-38x: Add arm_global_timer node
ARM: dts: marvell: fix PCI bus dtc warnings
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJZiayzAAoJEEEQszewGV1zqQoQAIaywuQGNO/nugEzQiUSdTte
s8prIJOGZBHB9bqpWZt+R1C7euVZ6qSV7lKhacHBStJsT2Ev2w3/4VtDNODFEP6X
0IpfeqEZT+AIrDerZFQL/T6hNciT8QqNATrrCAj64XdmvFY7UJutVqF8anJid6Zv
y0pJ+n4sS41UnW60PCH9O0TPVnc7fZyzh6d5kqzs3vH96jxnIWokYsTipuH9wW2/
76RWyzjGv5Kb9iFAe9qWop2JamfWsPvqrHJjy6pJzv9RKPKi7eWHuruMg6lCqMJb
pAOuIDWNRjPK/JxyxUNGOoz3jBqM0J3xoyOnBBXa/rlBbMk0+TcwcoNjlxyxPMjD
pyCHF1iUakqKqTdQI7My3CsxiZUqPqycNVgW5P95z/jg6FUMxOMdK2Y4uRLi5luh
rOLIkjjZVcDE1VFytB4yiaiiCcqeKwHw70C6p2xL7IT8ZyfWwHMKbis9NFfEoST0
orrgh+wI9y7v2W3pxs8jj2DRwNSTcohXaruxEnBbRX5rrUQSD45hKQHt4IvbUPfo
NwFxIqrydQXsK6ARuRr1euyIZ3EpOx4JVJsa+zE5W8UO8YzAhWRG2vJx8NbSCijy
W0Ji2gWtxCPjDj4kppxb04S0Tz+/hdkA979/4ctxu2iWAMvJyb+K9+L7IiYN1cUt
p/lV2/P8A/lxQ2YMU8qe
=SWBN
-----END PGP SIGNATURE-----
Merge tag 'gemini-dts-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt
Pull "Gemini DTS updates for ARM SoC take one" from Linus Walleij:
* tag 'gemini-dts-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: gemini: add pin control set-up for the SoC
ARM: dts: Add DTS file for D-Link DIR-685
ARM: dts: gemini: Switch to using macros
nodes. The rv1108 gains support for sd-cards on the evaluation board and
the general nodes get a bit of cosmetic. On rk3288 the evb gains support
saradc and the adc-key connected to it while some more boards also get
their mali gpu enabled (fennec, evb, tinker).
The biggest set of changes can be found on the rk3228/rk3229 combo this
time. It gets core support for efuse, sdmmc, sdio, io-domans and spdif
as well as a separate rk3229.dtsi that will keep the slight differences
between the two brothers rk3228/rk3229. The evaluation board also gets
some attention and abled nodes (regulators, io-domains, emmc, tsadc keys)
But I think the most interesting change is the cpu enable-method for it.
Instead of using the older in-kernel method, we're now also moving to
handling this in firmware via the psci interface on 32bit Rockchip socs.
In a recently merged pull request [0] support for the rk3228/rk3229 was
added to OP-TEE including the psci support and it seems supporting other
32bit Rockchip socs that way is also planned for the future.
[0] https://github.com/OP-TEE/optee_os/pull/1666
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlmERL4QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgbNLB/9Sgm6PAZtdObqta1nEjvp/5XFLlRTUuUFv
OSC0us+/22buKByODPBjnZonPUgxH95/7apaAoj+Deevms39C55nNS05GBa4sF5O
dRz1I5ZBl8LshZXs/IpS8+SjMs5zmtJfeWHw6NImqQzusXpkfoP3C9/ZDMw9XfCn
sE8Yi2EPlZAOlzI9Jqq9t1669JOQIjiDNFC6SvI9DZU37pb8olkBXMxt2VjT8Nb9
KJtpnVFFY4lisjaCG+BwhuBWPIy1aY5/gKVRNYGUdISAM2eHNpNxlLI0JYaA75Xh
Jn8sZArvM08nM/pLJdJvCo3sOvR8BsEX99O+tyd0Px58dMq9XsKd
=tCke
-----END PGP SIGNATURE-----
Merge tag 'v4.14-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Pull "Rockchip dts32 changes for 4.14" from Heiko Stübner:
Removal of the deprectated num-slots property from all Rockchip dw-mmc
nodes. The rv1108 gains support for sd-cards on the evaluation board and
the general nodes get a bit of cosmetic. On rk3288 the evb gains support
saradc and the adc-key connected to it while some more boards also get
their mali gpu enabled (fennec, evb, tinker).
The biggest set of changes can be found on the rk3228/rk3229 combo this
time. It gets core support for efuse, sdmmc, sdio, io-domans and spdif
as well as a separate rk3229.dtsi that will keep the slight differences
between the two brothers rk3228/rk3229. The evaluation board also gets
some attention and abled nodes (regulators, io-domains, emmc, tsadc keys)
But I think the most interesting change is the cpu enable-method for it.
Instead of using the older in-kernel method, we're now also moving to
handling this in firmware via the psci interface on 32bit Rockchip socs.
In a recently merged pull request [0] support for the rk3228/rk3229 was
added to OP-TEE including the psci support and it seems supporting other
32bit Rockchip socs that way is also planned for the future.
[0] https://github.com/OP-TEE/optee_os/pull/1666
* tag 'v4.14-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (23 commits)
ARM: dts: rockchip: fix property-ordering in rv1108 mmc nodes
ARM: dts: rockchip: enable sdmmc for rv1108 evb
ARM: dts: rockchip: add efuse device node for rk3228
ARM: dts: rockchip: add gpio power-key for rk3229-evb
ARM: dts: rockchip: enable tsadc for rk3229-evb
ARM: dts: rockchip: enable eMMC for rk3229-evb
ARM: dts: rockchip: enable io-domain for rk3229-evb
ARM: dts: rockchip: add cpu-supply property for cpu node of rk3229-evb
ARM: dts: rockchip: add regulator nodes for rk3229-evb
ARM: dts: rockchip: add sdmmc and sdio nodes for rk3228 SoC
ARM: dts: rockchip: fix compatible string for eMMC node of rk3228 SoC
ARM: dts: rockchip: add cpu enable method for rk3228 SoC
ARM: dts: rockchip: remove num-slots from all platforms
ARM: dts: rockchip: Add io-domain node for rk3228
ARM: dts: rockchip: add basic dtsi file for RK3229 SoC
ARM: dts: rockchip: enable adc key for rk3288-evb
ARM: dts: rockchip: enable saradc for rk3288-evb
ARM: dts: rockchip: enable ARM Mali GPU on rk3288-fennec
ARM: dts: rockchip: enable ARM Mali GPU on rk3288-evb
ARM: dts: rockchip: enable ARM Mali GPU on rk3288-tinker
...
Changes of note:
* Add pin controller support to the RZ/G1M (r8a7743) SoC and
RZ/A1 (r7s72100) SoCs now that the driver is available in v4.13-rc1.
* Add GPIO support to the RZ/G1M (r8a7743) SoC now that the driver
is availabe in v4.13-rc1.
* Enable MMCIF0 and Ethernet AVB support on the RZ/G1M (r8a7743) SoC and
the iWave-RZG1M-20M Qseven SOM. This depends on newly added pin
controller support noted above.
* Use R-Car Gen 2 fallback binding for vin nodes
This makes binding use consistent across R-Car Gen 2 SoCs.
It does not have any run-time effect
* Use SMP jump stub SRAM region from DT on R-Car Gen 2 SoCs
Geert Uytterhoeven says, "The R-Car Gen2 platform code for CPU core
bringup needs to copy a jump stub to on-SoC SRAM. Currently it uses a
hardcoded address pointing to ICRAM1."
* Add Inter Connect RAM to R-Car Gen 2 and RZ/G1 SoCs
Geert Uytterhoeven says, "R-Car Gen2 and RZ/G1 SoCs contain two or three
blocks of SRAM, which can be used for several purposes. One such purpose
is holding a jump stub for CPU core bringup."
* Use generic compatible string for I2C EEPROM for RZ/A1 (r7s72100) SoC
and koelsch board.
This is part of a tree-wide cleanup by Javier Martinez Canillas
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZf0jrAAoJENfPZGlqN0++0NoQAJyij1gZPrjbRWOYiFPohcxg
bWuGACKs8BH4CRoOIDR/jpLnqHM2Ikt8k1FjND/T52RQUMb5fvDPKl3C79S2Ck6p
WedFcS2E4wLBMzMx2lcEDWDiu9tEoje7BN302jcobMN6BThGVymmj1fMh8MP2rXP
cIT+ROifovlGGjWxSbzI0CIjeY2/LjSO5hJKBbawIaZVO3+9wPG7A1sdYQKnb2k2
I8k5WP3jCS4qfBKZ8i1/QG5UwJ5wNrXGXQKsgvFIJ1+vshqpSLA6ED8T42jtB4x1
NBpzsv3omL9/tlSUhOkSyht2xBLuxap/G43QePexCc88DdrWcvmMHYlCa1Mhmngg
/9L2869yQZ232eEVVdUxwl4maKc7mp+xRPJoS69NA6sCzZXMlPmmBtu53Exxo8+2
9/cKrTbIoofTYRR9SjjHRBFOrc+Eh4qlN3t6r+Qs2oVhD8Ae1o77bkiHdMZ4wxzM
7pnwbo91z8WsMCK5UsslULCMqOCRWKr8ehoIUjOb5nLColiF2P/SIxMX97WwnirI
1iw5w284KXQvyHaufXhfUBY3khtWfxOkUZ4h7qy9u7P8VBN9fH2W66XUoNMjC5rY
D8f6cPT467iPjm81GyFQ0OdM0amI8ieCMvd3/wnC5liwZXCHfIUCezm8cMRph46f
LMvkFJtxe5H0cD8AzyFA
=jQvt
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Pull "Renesas ARM Based SoC DT Updates for v4.14" from Simon Horman:
Changes of note:
* Add pin controller support to the RZ/G1M (r8a7743) SoC and
RZ/A1 (r7s72100) SoCs now that the driver is available in v4.13-rc1.
* Add GPIO support to the RZ/G1M (r8a7743) SoC now that the driver
is availabe in v4.13-rc1.
* Enable MMCIF0 and Ethernet AVB support on the RZ/G1M (r8a7743) SoC and
the iWave-RZG1M-20M Qseven SOM. This depends on newly added pin
controller support noted above.
* Use R-Car Gen 2 fallback binding for vin nodes
This makes binding use consistent across R-Car Gen 2 SoCs.
It does not have any run-time effect
* Use SMP jump stub SRAM region from DT on R-Car Gen 2 SoCs
Geert Uytterhoeven says, "The R-Car Gen2 platform code for CPU core
bringup needs to copy a jump stub to on-SoC SRAM. Currently it uses a
hardcoded address pointing to ICRAM1."
* Add Inter Connect RAM to R-Car Gen 2 and RZ/G1 SoCs
Geert Uytterhoeven says, "R-Car Gen2 and RZ/G1 SoCs contain two or three
blocks of SRAM, which can be used for several purposes. One such purpose
is holding a jump stub for CPU core bringup."
* Use generic compatible string for I2C EEPROM for RZ/A1 (r7s72100) SoC
and koelsch board.
This is part of a tree-wide cleanup by Javier Martinez Canillas
* tag 'renesas-dt-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (38 commits)
ARM: dts: iwg20m: Correct indentation of mmcif0 properties
ARM: dts: rskrza1: Add LED0 pin support
ARM: dts: rskrza1: Add SDHI1 pin group
ARM: dts: rskrza1: Add Ethernet pin group
ARM: dts: rskrza1: Add SCIF2 pin group
ARM: dts: genmai: Add ethernet pin group
ARM: dts: genmai: Add user led device nodes
ARM: dts: genmai: Add RIIC2 pin group
ARM: dts: genmai: Add SCIF2 pin group
ARM: dts: r7s72100: Add pin controller node
ARM: dts: iwg20m: Add MMCIF0 support
ARM: dts: r8a7794: Use R-Car Gen 2 fallback binding for vin nodes
ARM: dts: r8a7791: Use R-Car Gen 2 fallback binding for vin nodes
ARM: dts: r8a7790: Use R-Car Gen 2 fallback binding for vin nodes
ARM: dts: r8a7743: Add MMCIF0 support
ARM: dts: r8a7794: Reserve SRAM for the SMP jump stub
ARM: dts: r8a7793: Reserve SRAM for the SMP jump stub
ARM: dts: r8a7792: Reserve SRAM for the SMP jump stub
ARM: dts: r8a7791: Reserve SRAM for the SMP jump stub
ARM: dts: r8a7790: Reserve SRAM for the SMP jump stub
...
Highlights:
----------
-Add DMA support on STM32F746
-Add DMA support on STM32H743
-Add DAC support on STM32H743
-Add DAC support on STM32F429
-Add ADC support on STM32H743
-Enable ADC on stm32h743i-eval board
-Add CEC support on STM32F7xx MCUs
-Enable CEC on stm32f769-disco board
-Remove rdinit from stm32f4 boards
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZez7AAAoJEH+ayWryHnCF+I8P/3/+yK4yYfRStwYo7EjP0mnj
SS6WK+i7Zsz7mfbE7eWBSYLdaLjEwrFyuNIUDqf3b2Fc7XTBQOs51x8Mo0aukuoi
vxhW5bIAFfFombrY9ISgh2cl01VYsuRxlIHaR9S1Ch/kaoAGIDwvsHduWrcOtKvb
zFqPsE+/qSlCyWU/BFjDa6qBgoWlHAqxS0mulQ5Kyz/EAuXC3/9fugnwrN0jsSRj
am78i5r6wsddAr8f51VODs1eM0dlFEwBK1RFKxUjXYIZmL9IHCj/SqUWdMkKwTZw
UYB88V9rDw4Fp8d9pWFgloQKwBJguDvz6VqcY4tKVW9r7ahA5YtY2s+NI8OE09bb
WlsIg1lWf62uspPNnR8N1lRruh6c3+1kyOzl9hGHkPccsEAga2GN92goYmuxdZnS
4dWKwOW6mVOjnnCZsCJLNvQad7yoT6Jz+CgX75DGAisrRIzPwySbLACciHHzipJr
4ySqs3OvO/6v9pjFUMxNTZRqRanMrywcgvmOsv6I2LsG2tD5ftBMsDNwRnQ8KUUc
f2fQY8AiKMUMNB7sdTU3LbczF1h4UaH9XUnwbHizI7XzZt9vbD1m2v4WVUQ8niYx
3yjowPaTELm1zCzIrp4CQUUkJWxZDaujU5QcNwJ20kyl6O2rkvhD6eSh0QrK1vzu
ZQ9aNBnnqeZynYG6PaZf
=pZdf
-----END PGP SIGNATURE-----
Merge tag 'stm32-dt-for-v4.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/dt
Pull "STM32 DT updates for v4.14, round 1" from Alexandre Torgue:
Highlights:
----------
-Add DMA support on STM32F746
-Add DMA support on STM32H743
-Add DAC support on STM32H743
-Add DAC support on STM32F429
-Add ADC support on STM32H743
-Enable ADC on stm32h743i-eval board
-Add CEC support on STM32F7xx MCUs
-Enable CEC on stm32f769-disco board
-Remove rdinit from stm32f4 boards
* tag 'stm32-dt-for-v4.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
ARM: dts: stm32: Add DMA support for STM32H743 SoC
ARM: dts: stm32: Add DMA support for STM32F746 SoC
ARM: dts: stm32: enable ADC on stm32h743i-eval board
ARM: dts: stm32: add ADC support on stm32h743
ARM: dts: stm32: Add DAC support on stm32h743
ARM: dts: stm32: Add DAC support on stm32f429
ARM: dts: stm32: enable CEC for stm32f769 discovery
ARM: dts: stm32: add CEC for stm32f7 family
ARM: dts: stm32: reorder stm32h743 nodes
ARM: dts: stm32: Remove rdinit from bootargs on stm32f429-disco
ARM: dts: stm32: Remove rdinit from bootargs on stm32f429i-eval
ARM: dts: stm32: Remove rdinit from bootargs on stm32f469-disco
Remove deprecated and unneeded properties from Exynos boards.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJZdj2IAAoJEME3ZuaGi4PX2dYQAJct7EGtMQy4HItOscbiF2uM
ydiNNfEuqnDC40Z+NknkHS85lgO0nMzQXswff45eotED4K+1nVPLxu2zHPsApGxa
f+oztzGzSS4/nqv4iE/mXddQgZWvpT/VqT4scSvVxeYjBO+X9Yy3Qd8PSMd+tFt7
5YhDuaommRbsyZcgjxIF+Jl6871q0wm66QmzN70US6llsnwiDL6dQ4PyDtBpejv9
r9CYPRFvjb3rzgUt9VF1tPQcRow53walOn6F5w/laKwbS3emPGzWPhkSbU3zwMC3
sB88O9ae1SZCQAzxTX1Pl62uV13mut9E5o6okkwS+hizjatSWkjagvICwBmvdZ6S
qwm2gClJzibsEi19y1Ig8Lz7gJQeYpVkvjHzoJAGxmzp3OXjyy4w1TyGw0rFH5yb
/lEt+13kAF/SrnEFrakgMtuZ13aBlmwaOA5sVxYHKQ7moJ6mR2gQZaMmacKLJN/C
fdzsLU3Y00WW+Fs7N21hn96/Q8EamwE037ElGrc6MrTfRtMJ9M2QS7qoAuQ07Oor
qoQZze2eqMK52u/HBRauCBINpcOa874AVY9PqkLpjOkKxR38ft8MRvl3RoEczs8q
BzMx1AxhznYkcrZo0ssGHWAfOSKdYmXUuryF7iv2gzjs8GdKAEBkzwRVVZryupUX
PEItnzsZfh38bsOviHTb
=9f+j
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Pull "Samsung DTS ARM changes for v4.13" from Krzysztof Kozłowski:
Remove deprecated and unneeded properties from Exynos boards.
* tag 'samsung-dt-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Remove num-slots from exynos platforms
ARM: dts: exynos: Remove the OF graph from DSI node
separately from the rest of the dts changes to avoid merge conflicts
as these depend on earlier fixes sent during v4.13-rc cycle.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlmTI94RHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXMvGA//a4qKA8IDXTjPVpEILumjcoxlpiCiYtUX
FGduGiI/ceWWfmVT1nBtd1BGXPJRzNIwOasfMQIhOt2R+umopioTtjUClom2oXVm
KSTh2ikalObjXChyLvgi7BQhoeJMJVZPumRQ/7GMc93UlM2WAdn1ACCsLqhSu2wF
U7SzpWKI987Ze4i6SKUo1ygYvZ2ue86qRt+827pCf6aIOUB+58N8Z2OII/Atdvn+
5Uy7ML3BMqcAtTEbLYz6LpiNls5TKdRBmPXNFvLJKxhtA6fTYTrgklW05ezaoKX5
iHRsMQ509M+j0b71YwEl3Ta/qiaew+L3+jaYKHjEaFXJaBF2UH17jKf4U9mi9LdN
+rtESdIWE/yNuulZV/FKRA+kUQL9MMdvS7txFaEnsyYuelnI4U3l+bCF9gQoTftk
YFc09/yRLOq60G8V8H9pYT6MKPeyD7jGTjFlSV0VHmK6wVWncIHSqPmnzfCsmVkB
URIsS8XRNLypqIOIz7r1OHaSX829DFMRgkATnWLmcuM5AOsRjGtDJtITFNZBx662
KFMhHVduVQtVJfvKprCNeUhjnDnRN3g3UMtLBiPnjxj1gmGlttxxvvhcB/OJPqPi
mPBdtl0OIM6JbVX44cl+MyjInTAGRgcRfII83TV0ptk3qYITbLE2kIYB8QC2gE9B
VFfKfjfEJr0=
=Njlb
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.14/fixes-not-urgent-dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
Pull "non-urgent dts fixes for omaps for v4.14" from Tony Lindgren:
Two non-urgent dts fixes for dra7 Ethernet quirk. These are sent
separately from the rest of the dts changes to avoid merge conflicts
as these depend on earlier fixes sent during v4.13-rc cycle.
* tag 'omap-for-v4.14/fixes-not-urgent-dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: dra72-evm-revc: workaround incorrect DP83867 RX_CTRL pin strap
ARM: dts: dra71-evm: workaround incorrect DP83867 RX_CTRL pin strap
Include dra72x-mmc-iodelay.dtsi which has pinmux and IODelay
configuration values for the various MMC modes for dra72 SoC
and use it in the pinctrl properties of MMC devicetree
nodes present in dra71-evm.dts.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Include dra72x-mmc-iodelay.dtsi which has pinmux and IODelay
configuration values for the various MMC modes for dra72 SoC
and use it in the pinctrl properties of MMC devicetree
nodes present in dra72-evm-revc.dts.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Include dra72x-mmc-iodelay.dtsi which has pinmux and IODelay
configuration values for the various MMC modes for dra72 SoC
and use it in the pinctrl properties of MMC devicetree
nodes present in dra72-evm.dts.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Include dra74x-mmc-iodelay.dtsi which has pinmux and IODelay
configuration values for the various MMC modes for dra74x SoC
and use it in the pinctrl properties of MMC devicetree
nodes present in am572x-idk.dts.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Include dra72x-mmc-iodelay.dtsi which has pinmux and IODelay
configuration values for the various MMC modes for dra72 SoC
and use it in the pinctrl properties of MMC devicetree
nodes present in am571x-idk.dts.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
AM572x IDK and AM571x IDK boards have equivalent
design of how SD card and eMMC are connected.
The two EVMs mainly differ in IOdelay configuration
needed (because of difference in SoC used).
Move the common properties to am57xx-idk-common.dtsi
file which is common for both EVMs.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Include dra74x-mmc-iodelay.dtsi which has pinmux and IODelay
configuration values for the various MMC modes for dra74 SoC
and use it in the pinctrl properties of MMC devicetree
nodes present in am57xx-beagle-x15/am57xx-beagle-x15-revb1.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Include dra74x-mmc-iodelay.dtsi which has pinmux and IODelay
configuration values for the various MMC modes for dra74 SoC
and use it in the pinctrl properties of MMC devicetree
nodes present in dra7-evm.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add pinmux configuration for MMC module including IODELAY
values suggested in the data manual for the various supported
modes.
IOdelay data for both silicon revision 1.1 and 2.0 is
added here.
The datamanual revisions used are:
* AM572x Silicon Revision 2.0: SPRS953B, Revised November 2016
* AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add pinmux configuration for MMC module including IODELAY
values suggested in the data manual for the various supported
modes.
IOdelay data for both silicon revision 1.0 and 2.0 is
added here.
The datamanual revisions used are:
* AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017
* AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017
* DRA71x : SPRS960B, Revised February 2017
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add NAND controller node to LD4, Pro4, sLD8, Pro5, and PXs2.
Set up pinctrl to enable 2 chip select lines except Pro4. The CS1
for Pro4 is multiplexed with other peripherals such as UART2, so
I did not enable it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add the (previously omitted) Ether/PHY pin data to the SK-RZG1E board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the (previously omitted) SCIF2 pin data to the SK-RZG1E board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Define the generic R8A7745 part of the PFC device node.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
- Add missing 'ranges' property for i.MX25 device tree TSCADC node, so
that it's child nodes ADC and TSC device can be probed by kernel.
- Fix i.MX GPCv2 power domain driver to request regulator after power
domain initialization, since regulator could defer probing and
therefore cause power domain initialized twice.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJZhcIQAAoJEFBXWFqHsHzO6N8H/1Uyq0u3a6T29U3BeI6CBKuD
ACYVHKv+eZCk4uMjmVknWTsMKaoGtho52TThd7GYwLxCSB4lmjurXnOpnSbMmgVX
Tl1XfCrmZECf4M0e5eTPbHbfMAI+EJXzNc8echgiLpJwA8rqQ/u9tJ0hxJjviDaI
KtUL01MT5ZfkLD6gXZnBvWA2BvU5ibatgLq1gX2WYONkGwp1aombzcYgM7ADw9NY
xEvJHLb5uVoQRUECW25evQ54leBj0YeoOWFgvjMvFrR9kr/H/LSCG0cKQidCcv1C
v85d6GcYZq/GWtlZn8ThbeQJS044S8KnLS9/z3cqXXjllN5tBB6wEM1s1XcwxKY=
=u055
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-4.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
Pull "i.MX fixes for 4.13, round 2" from Shawn Guo:
- Add missing 'ranges' property for i.MX25 device tree TSCADC node, so
that it's child nodes ADC and TSC device can be probed by kernel.
- Fix i.MX GPCv2 power domain driver to request regulator after power
domain initialization, since regulator could defer probing and
therefore cause power domain initialized twice.
* tag 'imx-fixes-4.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: i.MX25: add ranges to tscadc
soc: imx: gpcv2: fix regulator deferred probe
- A fix for imx7d-sdb board to move pinctrl_spi4 pins from low power
iomux controller to normal iomuxc node, as the pins belong to normal
iomuxc rather than low power one.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJZbEHeAAoJEFBXWFqHsHzOAPAIALiP2zuIKCWjBV5P49uxgRv8
RM6APzx6HX17lmERFt/b3j6/CmKJ758VSqhXGtvM+q7yTKdLyNr0/FNVZxc2VYwo
6fpUwQqQBEmTERE55JfToOd9nVljwPcd+5Cj3Cr0q/rkTyXbkxzZ3pE1Q2i2IWFX
rKbDxt0wjqy3V2trhR9ZOVrgJgh6zNlTOnD+49PBQPJZ87Xukg3lJDXoTe7dRXfq
+Uz4Kl9g8LNCxUGWdfw/ecgeVGx+eCir81Hq1LadXHVGOQfY5QEGs9E9bfT8gTME
4MIHdWGBgJ8yt/R5YOdsQZyv2O6t2LAJKO9BAot41I7SJbnXlWpP0ssmb8IUV50=
=e4WF
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
Pull "i.MX fixes for 4.13" from Shawn Guo:
- A fix for imx7d-sdb board to move pinctrl_spi4 pins from low power
iomux controller to normal iomuxc node, as the pins belong to normal
iomuxc rather than low power one.
* tag 'imx-fixes-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx7d-sdb: Put pinctrl_spi4 in the correct location
Add camera support to N900 dts. Also add a note about MMC & debugging.
Signed-off-by: Pavel Machek <pavel@ucw.cz>
Acked-by: Pali Rohár <pali.rohar@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
dra76-evm is a board based on TI's dra76 processor targeting
for infotainment systems. Adding support for this platform.
dra76-evm and dra7-evm has a similar layout except with few differences.
So create a dra7-evm-common.dtsi with similarities on dra76-evm and
dra7-evm. Include this common dtsi in both dra7-evm.dts and dra76-evm.dts
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
dra76 family is a high-performance, infotainment application
device, based on OMAP architecture on a 28-nm technology.
This contains most of the subsystems, peripherals that are
available on dra74, dra72 family. This SoC mainly features
Subsystems:
- 2 x Cortex-A15 with max speed of 1.8GHz
- 2 X DSP
- 2 X Cortex-M4 IPU
- ISS
- CAL
- DSS
- VPE
- VIP
Connectivity peripherals:
- 1 USB3.0 and 3 USB2.0 subsystems
- 2 x SATA
- 2 x PCI Express Gen2
- 3-port Gigabit ethernet switch
- 2 x CAN
- MCAN
Adding basic dts support for DRA76 family while reusing the
data available in dra7.dtsi, dra74x.dtsi.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add pcie1 dt node in order for the controller to operate in
endpoint mode. However since none of the dra7 based boards have
slots configured to operate in endpoint mode, keep EP mode
disabled.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for Moxa UC-8100-ME-T open platform
The UC-8100-ME-T computing platform is designed
for embedded data acquisition industrial applications
The features of UC-8100-ME-T series are:
* eMMC
* SPI flash
* SD slot
* 2x LAN
* 2 RS-232/422/485 ports, software-selectable
* Mini PCIe form factor with USB signal
* USB host
* EEPROM
* TPM
* Watchdog
* RTC
* User gpio-keys
* User LEDs
* User button
Signed-off-by: SZ Lin <sz.lin@moxa.com>
Acked-by: Rob Herring <robh@kernel.org>
[tony@atomide.com: fix unit adress as suggested by Rob]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently the default method of prefetch polled shows the highest
possible read and write speed when minimal non NAND background
activity is being done. But it is also very CPU intensive to reach
these high speeds (CPU load of 99% via mtd performance tests). While
DMA prefetch only uses 50% of the CPU to achieve around 23% less in
top read and write performance.
However, as the non NAND CPU load increases the read and write
performance takes a large hit when using polled prefetch. Therefore,
prefetch dma mode ends up outperforming prefetch polled in general
"system level" test. So switch to using dma prefetch by default since
it is likely what most users would prefer.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently the default method of prefetch polled shows the highest
possible read and write speed when minimal non NAND background
activity is being done. But it is also very CPU intensive to reach
these high speeds (CPU load of 99% via mtd performance tests). While
DMA prefetch only uses 50% of the CPU to achieve around 23% less in
top read and write performance.
However, as the non NAND CPU load increases the read and write
performance takes a large hit when using polled prefetch. Therefore,
prefetch dma mode ends up outperforming prefetch polled in general
"system level" test. So switch to using dma prefetch by default since
it is likely what most users would prefer.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently the default method of prefetch polled shows the highest
possible read and write speed when minimal non NAND background
activity is being done. But it is also very CPU intensive to reach
these high speeds (CPU load of 99% via mtd performance tests). While
DMA prefetch only uses 50% of the CPU to achieve around 23% less in
top read and write performance.
However, as the non NAND CPU load increases the read and write
performance takes a large hit when using polled prefetch. Therefore,
prefetch dma mode ends up outperforming prefetch polled in general
"system level" test. So switch to using dma prefetch by default since
it is likely what most users would prefer.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add vibrator to Droid4's device tree.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Set default mode for vaudio, which may be left in standby mode
if the system is booted via kexec from Android.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Tony Lindgren <tony@atomide.com>
All nodes inhert "interrupt-parent" property from root
node. Removed the aforementioned property from usbhsohci,
usbhsehci, ssi_port1, ssi_port2 nodes to avoid duplication.
Signed-off-by: Karthik Tummala <karthik@techveda.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Devices using an external encoder, ESD protection and level shifter
such as tpd12s015 or ip4791cz12 have the CEC pull in the encoder
chip. And on var-som-om44, there is external pull up resistor R30.
So the internal CEC pull-up resistor needs to be disabled as otherwise
the external and internal pull are parallel making the pull value
much smaller than intended. This leads into the CEC not working as
reported by Hans Verkuil <hverkuil@xs4all.nl>.
Reported-by: Hans Verkuil <hverkuil@xs4all.nl>
Cc: Dmitry Lifshitz <lifshitz@compulab.co.il>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for onboard gpio buzzer. It works using
the gpio-beeper driver. Pinmux entries for GPIO
controlling the buzzer are also added.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds the missing 32-bit enable method for SMP on BCM2836 and
BCM2837. The BCM2837 already has an enabled method, but this one only
works for 64-bit.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Tested-by: Eric Anholt <eric@anholt.net>
Dummy patch to sort nodes alphabetically and add some blank lines
for consistency.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
The bananapi-r2 board has an SD-card controller and built-in
EMMC storage so enables those devices in the devicetree.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports,
IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.
This patch adds the IOMUXC1 support for A7.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the I2C[0-5] devices to the r8a7743 device tree.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit enables i2c recovery, supported by the i2c core subsystem.
It defines the required GPIOs for SDA and SCL lines.
Signed-off-by: Jose Alarcon <jose.alarcon@ge.com>
Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Migrate to using functionally-reduced I2C master contained in the DWC
HDMI. Therefore drop the GPIO bitbanging based i2cddc definition and
modify resp. pinctrl.
While at it re-order the I2C aliases to start with the generic, followed
by the camera and concluded by the power I2C one.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Split the pinctrl property for usdhc1 into a 4-bit SD interface
and an extension to 8-bit. This is required to support both 8-bit
and 4-bit interface on usdhc1 as per the carrier board.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The SD1 pinctrl-0 property is overridden but only the card detect pin
is muxed, the control and data signals are not referenced at all.
It worked because the bootloader muxed them to a sensible state though.
Fix this.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
There are four i2c controllers on rv1108, add
device tree node for them.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
A CMA memory pool reserved memory node is added, and is attached
to the DSP node through the 'memory-region' property on the K2G
ICE board. This area will be used for allocating virtio rings and
buffers. This node allows the DSP Memory Protection and Address
Extension (MPAX) module to be configured properly for the DSP
processor, and matches the values used on the other Keystone 2
boards for software compatibility.
The reserved memory node and the user DSP node are also marked
okay to enable the DSP on the K2G ICE board.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
A CMA memory pool reserved memory node is added, and is attached
to the DSP node through the 'memory-region' property on the K2G
EVM board. This area will be used for allocating virtio rings and
buffers. This node allows the DSP Memory Protection and Address
Extension (MPAX) module to be configured properly for the DSP
processor, and matches the values used on the other Keystone 2
boards for software compatibility.
The reserved memory node and the user DSP node are also marked
okay to enable the DSP on the 66AK2G EVM board.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
The Keystone 2 66AK2G SoC has a single TMS320C66x DSP Core
Subsystem (C66x CorePac), containing a C66x Fixed/Floating-Point
DSP Core, and 32 KB of L1P & L1D SRAMs and a 1 MB L2 SRAM. Add
the DT node for this DSP processor sub-system.
The DT node has a new property 'power-domains' and no 'clocks'
properties, and uses slightly different property values for
'resets' compared to other Keystone 2 SoCs. The processor does
not have an MMU, and uses various IPC Generation registers and
shared memory for inter-processor communication. The alias with
a stem 'rproc' has also been added for the DSP, it provides a
fixed remoteproc id for the DSP processor.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
This patch enables the integrated PHY for rk3228 evb board
by default.
To use the external 1000M PHY on evb board, need to make
some switch of evb board to be on.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The DRA72 EVM Rev C straps the DP83867 GigaBit Ethernet phy's RX_DV/RX_CTRL
pin in mode 1. Unfortunately, the phy data manual disallows this.
Add "ti,dp83867-rxctrl-strap-quirk" property to the phy's device-tree node
to allow kernel to enable software workaround for this incorrect strap
setting. This is as suggested by the phy's datamanual and ensures proper
operation of this PHY.
This needs to be done for both instances of this PHY present on the board.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The DRA71 EVM straps the DP83867 GigaBit Ethernet phy's RX_DV/RX_CTRL pin
in mode 1. Unfortunately, the phy data manual disallows this.
Add "ti,dp83867-rxctrl-strap-quirk" property to the phy's device-tree node
to allow kernel to enable software workaround for this incorrect strap
setting. This is as suggested by the phy's datamanual and ensures proper
operation of this PHY.
This needs to be done for both instances of this PHY present on the board.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add nodes for the two DCAN instances included in 66AK2G
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[d-gerlach@ti.com: add power-domains and clock information]
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[fcooper@ti.com: update subject and commit message. Misc minor updates]
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
The interrupt for power button is static data that comes from the
datasheet, there is no reason to need to define this value on every
board so seams reasonable put this information into the common tps65217
file.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The interrupt specifiers for USB and AC charger input are static data that
comes from the datasheet, there is no reason to need to define these values
on every board so seem reasonable put this information into the common
tps65217 file.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Replace deprecated "vmmc_aux" with the generic "vqmmc" binding for
MMC IO supply.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The GPIO polarity for MMC1 card detect is set to '0' which means
active-high. However the polarity should be active-low. Fix it
here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The GPIO polarity for MMC1 card detect is set to '0' which means
active-high. However the polarity should be active-low. Fix it
here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The UniPhier AIO2013 audio system needs I2S and clock signal pins
to connect external codec chip.
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The UART bindings needs specifying a SoC family, use the meson6 family
for the UART nodes like the other nodes.
Switch to the stable UART bindings for meson6 by adding a XTAL node and
using the proper compatible strings.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This patch adds and enables the device-tree definitions for
both qcom,ipq4019-wifi blocks for the IPQ4019.
Support for these have been added into the ath10k driver since:
commit 280e762e9c ("ath10k: enable ipq4019 device probe in ahb module")
The binding documentation was added in:
commit a47aaa69de ("dt: bindings: add new dt entry for pre calibration in qcom, ath10k.txt")
This has been tested on an ASUS RT-AC58U (IPQ4019),
an AVM Fritz!Box 4040 (IPQ4018), a Compex WPJ428 (IPQ4028)
and a Cisco Meraki MR33 (IPQ4029).
| a000000.wifi: qca4019 hw1.0 target 0x01000000 chip_id 0x003b00ff [...]
| a000000.wifi: kconfig debug 0 debugfs 1 tracing 0 dfs 1 testmode 1
| a000000.wifi: firmware ver 10.4-3.4-00082 api 5 features no-p2p,mfp,[...]
| a000000.wifi: board_file api 2 bmi_id 0:16 crc32 5773b188
| a000000.wifi: htt-ver 2.2 wmi-op 6 htt-op 4 cal pre-cal-file [...]
...
| a800000.wifi: qca4019 hw1.0 target 0x01000000 chip_id 0x003b00ff sub 0000:0000
| a800000.wifi: kconfig debug 0 debugfs 1 tracing 0 dfs 1 testmode 1
| a800000.wifi: firmware ver 10.4-3.4-00082 api 5 features no-p2p, [...]
| a800000.wifi: board_file api 2 bmi_id 0:17 crc32 5773b188
| a800000.wifi: htt-ver 2.2 wmi-op 6 htt-op 4 cal pre-cal-file [...]
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Replace the obsolete compatible string for Coresight programmable
replicator with the new one.
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This architecture has a pseudo random number generator
supported by the existing "qcom,prng" binding.
rngtest: bits received from input: 5795960032
rngtest: FIPS 140-2 successes: 289591
rngtest: FIPS 140-2 failures: 207
rngtest: FIPS 140-2(2001-10-10) Monobit: 25
rngtest: FIPS 140-2(2001-10-10) Poker: 28
rngtest: FIPS 140-2(2001-10-10) Runs: 91
rngtest: FIPS 140-2(2001-10-10) Long run: 67
rngtest: FIPS 140-2(2001-10-10) Continuous run: 0
rngtest: input channel speed: (min=244; avg=46122; max=3906250)Kibits/s
rngtest: FIPS tests speed: (min=1.327; avg=20.966; max=26.345)Mibits/s
rngtest: Program run time: 386965827 microseconds
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The node for xo and timer belong to the SoC DTS file.
Else, new board DT files may not inherit these nodes.
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch fixes the pinctrl node addresses to be the correct format.
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds the basic pin control muliplexing settings for the
Gemini SoC: parallel (NOR) flash, SATA, optional IDE, PCI and
UART.
We also select the right GPIO groups on all applicable systems
so that GPIO keys/LEDs work smoothly.
We can then build upon this for more complex systems.
Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds a device tree file for the Gemini-based D-Link DIR-685
router, supporting all devices that are currently supported in
the main DTSI SoC file.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The macros for reset and clock lines were merged during the merge
window, this switches the Gemini to use these macros rather than
numerical defines.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies
in one package sharing the serial bus (I2C/RSB) pins. One die is the
actual PMIC. The other is an AC100 codec / RTC combo chip.
This patch adds the device nodes for the AC100 chip to the h8homlet-v2
device tree.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies
in one package sharing the serial bus (I2C/RSB) pins. One die is the
actual PMIC. The other is an AC100 codec / RTC combo chip.
This patch enables the RSB controller and adds a device node for the
PMIC die to the h8homlet-v2 device tree. Since the AXP813 and AXP818
are virtually identical, this patch uses the compatible string for
the former as a fallback.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies
in one package sharing the serial bus (I2C/RSB) pins. One die is the
actual PMIC. The other is an AC100 codec / RTC combo chip.
This patch adds the device nodes for the AC100 chip to the Cubietruck
Plus device tree.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies
in one package sharing the serial bus (I2C/RSB) pins. One die is the
actual PMIC. The other is an AC100 codec / RTC combo chip.
This patch enables the RSB controller and adds a device node for the
PMIC die to the Cubietruck Plus device tree. Since the AXP813 and
AXP818 are virtually identical, this patch uses the compatible string
for the former as a fallback.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A83T has an RSB controller for talking to the PMIC and audio codec.
Add a device node for it. Since there is only one usable pinmux setting,
for it, add that as well.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Adds support for the Broadcom reference board BCM947189ACDMBR which
features the following:
* 128MB of DRAM
* External MoCA support through a Broadcom BCM6802 chip
* 1x external Gigabit PHY through the external BCM6802
* 1x USB 2.0 port
* 1x PCIE slot
* Few configurable buttons and LEDs
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This uses trigger-sources documented in commit 80dc6e1cd8 ("dt-bindings:
leds: document new trigger-sources property") to specify USB ports. Such an
information can be used by operating system to setup LEDs behavior.
I updated dts files for 7 devices I own and I was able to test.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This uses the existing Northstar USB3 PHY driver to enable the USB3
ports on NSP.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The rest of the DTSI file is in incrementing addresses, but the USB
OHCI/ECHI entries are out of sequence. Move them to put them in the
proper place.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cache related issues with DMA rings and performance issues related to
caching are being caused by not properly setting the "dma-coherent" flag
in the device tree entries. Adding it here to correct the issue.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Fixes: 3107fa5bcf ("ARM: dts: NSP: Add SD/MMC support")
Fixes: 13d04f2093 ("ARM: dts: NSP: Add AMAC entries")
Fixes: 5aeda7bf8a ("ARM: dts: NSP: Add and enable amac2")
Fixes: 17d5171723 ("ARM: dts: NSP: Add mailbox (PDC) to NSP")
Fixes: 1d8ece6639 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
Fixes: 0f9f27a36d ("ARM: dts: NSP: Add I2C support to the DT")
Fixes: 8dbcad020f ("ARM: dts: nsp: Add sata device tree entry")
Fixes: 522199029f ("ARM: dts: NSP: Fix PCIE DT issue")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Enable MMC0 which is used for micro SD and MMC1 which is used for the on
board EMMC.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[fcooper@ti.com: add mmc1, bufferclass and pullup/pulldown settings]
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
[nsekhar@ti.com: add card detect GPIO support]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
Add device tree nodes for MMC0 and MMC1 pesent
on 66AK2G device.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[nsekhar@ti.com: fix clock-names for mmc1 node]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
66AK2G has 2 instances of gpio. The first one has all the 144 GPIOs
functional. 9 banks with 16 gpios making a total of 144. The second
instance has only the GPIO0:GPIO67 functional and rest are marked
reserved.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
In order to be able to use more than 4GB of RAM when the LPAE is
activated, the dts must be converted in 64 bits.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The H8 homlet has a micro-SD card slot connected to mmc0,
and onboard eMMC from FORESEE, connected to mmc2.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that we support the MMC controllers on the A83T SoC, we can enable
them on some boards.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
mmc2 can support 8-bit eMMC chips, with a dedicated reset line.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A83T has 3 MMC controllers. The third one is a bit special, as it
supports a wider 8-bit bus, and a "new timing mode".
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The dwmac-sun8i hardware is present on the Beelink X2.
It uses the internal PHY.
This patch create the needed emac node.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[wens@csie.org: Fixed typo in commit subject]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
This STB has a type A socket which acts as OTG.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The Bananapi M2-Magic is a board with an A33, a USB host and USB OTG
connectors, and 8GB eMMC, an AP6212 WiFi/Bluetooth chip and connectors for
DSI, CSI and GPIOs.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[wens@csie.org: Correct subject prefix case]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The Cubietruck has an AXP209 PMIC with battery connector.
This enables the battery power supply subnode.
Signed-off-by: Alexander Syring <alex@asyring.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[wens@csie.org: Correct subject prefix order]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The R_INTC interrupt controller handles the NMI interrupt pin for the
SoC. While there is no documentation or code from the vendor for this
device on the A83T, existing mainline kernel drivers and bindings show
this to be similar to the old Allwinner interrupt controller found on
the A10 SoC, but with only the NMI interrupt wired. Register poking
experiments confirm this.
The device seems to be the same across all recent Allwinner SoCs, apart
from the A20 and A80, which have a separate set of registers to handle
the NMI interrupt. We already have a set of bindings supporting this
on the A31.
Add a device node for it, with an SoC specific compatible.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
We introduced a new compatible for the NMI or R_INTC interrupt
controller. This new compatible has the register region aligned
to the boundary listed in the SoC's memory map.
This patch converts the NMI/R_INTC node to using the new compatible,
and fixes up the register region and device node name.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
We introduced a new compatible for the NMI or R_INTC interrupt
controller. This new compatible has the register region aligned
to the boundary listed in the SoC's memory map.
This patch converts the NMI/R_INTC node to using the new compatible,
and fixes up the register region and device node name.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Support proper system power-off, which disables main regulator. This
results in much lower power consumption and support of power-on issued
by button press.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add a ranges; line to the tscadc node. This creates a 1:1 mapping between
the addresses used by tscadc and those in its child nodes (adc, tsc).
Without such a mapping, the reg = ... lines in the tsc and adc nodes do
not create a resource. Probing the fsl-imx25-tcq and fsl-imx25-tsadc
drivers will then fail since there's no IORESOURCE_MEM.
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Fixes: 92f651f39b ("ARM: dts: imx25: Add TSC and ADC support")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The CX9020 differs from i.MX53 Quick Start Board by:
- use uart2 instead of uart1
- DVI-D connector instead of VGA
- no audio
- no SATA connector
- CCAT FPGA connected to emi
- enable rtc
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
UART2 on EIM_D26 - EIM_D29 pins supports interchanging RXD/TXD pins
and RTS/CTS pins.
One board using these alternate settings is Beckhoff CX9020. Add the
alternative configuration here, to make it available to others, too.
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The i.MX53 has an integrated secure real time clock. Add it to the dtsi.
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add a devicetree entry for the Random Number Generator Version B (RNGB).
The driver for RNGC supports version B as well.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The mmc1 interrupt should be connected to GIC_SPI 40,
this patch fixes this.
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Sean Wang <sean.wang@mediatek.com>
They should be used only when an actual
remote-endpoint is connected.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZectgAAoJEGFBu2jqvgRNZdkP/27ovOMGuzleyl18PiLotyXn
98qxZvnFYyEw258vkUJj0N7Rmf3gMnrfbrRIOGXyOIBpZNBkgEqjGlagXn9Z+o8F
QOERxzDT5JiM6BbR+tRPOmKc07uuccVskOCoYOZ1mk4c336b/m9dNppdWGGY83LC
WJ0OeoFP8k8gUMYqSyKscXyfryP82KbryZH5s5tmSVAnEHf6psUzAUUdQf7An5v2
Up5nD4ljF+leGX6PG8rAFRbMGy/jTHOQi7QafVx3rC+p8SydoUnEWhPTrtkDzRTb
bXtpjSUId7n80qKtyI/vD3ABDBajr4RUzYjuXGfSf32A5uvk7xjzUk8QfwWogxv5
fdOga6ogEOUjgB1L+u2uegHQl3CGSZK5sXufoQivcndBgXqA5S9VkQk/FNjAM9vJ
twyC+s3pgC7cBrHGmM4QFToubYQthmXOevKmKlbRvXyNFHW6BcIPcbq+6t4IDakd
DU7iYRzR+AxVK5fezWOhBxxL2aRK533r/gc1ZOBklRN1gD+5AWLfaQJMNDDdVePJ
8AH+PAZZz2ETXLvMH+D4XSPF6t7gDyZ6Jroh+YJ3i0Y0vOO16Jr2LvJlAClFfQNM
+TRjhaGd4WFrUVnpiyPU9l2MrTOmSu4VgEnWvf28KqyHq8fEA3ew9u+vRZhcV/2X
SwJX0rE5626UDsieIVGP
=rgNN
-----END PGP SIGNATURE-----
Merge tag 'davinci-fixes-for-v4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into fixes
Pull "DaVinci fixes for v4.13" from Sekhar Nori:
Drop unused VPIF endpoints from device-tree.
They should be used only when an actual
remote-endpoint is connected.
* tag 'davinci-fixes-for-v4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: dts: da850-lcdk: drop unused VPIF endpoints
ARM: dts: da850-evm: drop unused VPIF endpoints
Two fixes to correct the EMAC blocks memory region size to match the
datasheet. One that converts raw A83T clock indices to macros from the
clk dt-binding header, completing the A83T sunxi-ng clk driver.
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAll566wOHHdlbnNAY3Np
ZS5vcmcACgkQOJpUIZwPJDBBhw//RK8UpKhviq1kdn6yDNKe3dVYxRTGtISvpjJL
oPXpstt1b28DdbVjeIzh6jqF2HjjNmfFlLphOoOj1H7qKqhobr9+Cll05BNWbCmH
CIL6qL8FT7QyK8yw5sPLcdlNLkNil+KfgnrBf76Crdw0R1HXGENsw+gVE2lVX+tJ
yRqhguaQjWNLA5v+nfK4la+Ip1ddgKgiBmkpkq9tuR8hUDe33LHFZxur28EChHb/
P1HXL1DHUn2uO/tyk1TDhpYkNbOGiER4neOeQt21uaKLDaRMmkRlaNHgGg4CQ/fR
OYs24Sm0XB9oFVKzz2GttkIkdWTOqRI99VlXHEd3bU3Rc2PdClrdky615qkDn/90
CCjz7ibhnkri5+1/MWVC1iF/sotYnlCKjptXMZNRmqoyC2ol+tkNy84MoHvuWBCU
/IzCNuU8sGqC5/PjGNo2LwQNmzkFsk78s0MQAUyxG0isJwMrGQaSXGtOpSLJzUPv
MRBqYyK2CQk7gZtDyeZPepUUeQta/bAFIUROeozgTstvib86ywYrflrjkBTEyPar
Q+ptcoEgw1FVZZ4cQCGQWkg16dtFPSBMbGAbjlh/9DJXbZU/DVF5XRpTj8FthWm7
Vw/QQx4A18O+oS5/CkBjdltAb4RZIcF2ijAupRbwPIG+pzNVJVJ7JN7BzdVAFAyF
cf/Btkw=
=aFvT
-----END PGP SIGNATURE-----
Merge tag 'sunxi-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into fixes
Pull "Allwinner fixes for 4.13" from Chen-Yu Tsai:
Two fixes to correct the EMAC blocks memory region size to match the
datasheet. One that converts raw A83T clock indices to macros from the
clk dt-binding header, completing the A83T sunxi-ng clk driver.
* tag 'sunxi-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sun8i: a83t: Switch to CCU device tree binding macros
arm64: allwinner: sun50i-a64: Correct emac register size
ARM: dts: sunxi: h3/h5: Correct emac register size
showed a wrong value, so fix it before it gets copy-pasted
to much.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlmEM5wQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgVn+B/9Xy9km3t8cFVQ//SjNm1MEfiyVrgCnH6TH
trLit6AKq19LTIfeyI2RQucEXB0Csw2+YNh4q9Td6utnc0S3OpzueFsfKfAD9xif
WpRR6MJjCSlIQfhd09XuKyWoDwwNmnidv+Xd/H3M83dTOzoPmy0aDkn/shc1I+Tw
gL0CbLPz1HuHuG55S5EkxcBNi/Mj34qI5e3O8hrqzpfzmc1CdQ38zblfkiyu94v7
f/sVUv8p2YHyfvIJ1n1DxQx7lvAxGzo3Q7fXqS9D1jJx4iDWWFaraLMPu3NztLcv
1XrawJTdGZ9vTJSmzcEwH7JeAUHX41wIWjf/jEx9iE2R9EY0lyLo
=B0nU
-----END PGP SIGNATURE-----
Merge tag 'v4.13-rockchip-dts32fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixes
Pull "Rockchip dts32 fixes for 4.13" from Heiko Stübner:
Fix for the recently added mali dt support. The example
showed a wrong value, so fix it before it gets copy-pasted
to much.
* tag 'v4.13-rockchip-dts32fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: fix mali gpu node on rk3288
dt-bindings: gpu: drop wrong compatible from midgard binding example
Since generic Cortex-A9 global timer is available after adding
it to compilation, enable its node in armada-38x.dtsi.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 is connected to the INT1 pin of
the FXLS8471Q accelerometer, so remove it from the unrelated ENET
group.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Colibri iMX7 modules come with 512MB on-module SLC NAND flash
populated. Make use of it by enabling the GPMI controller.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Raspberry Pi Zero W has the same components like the Zero plus
a Cypress CYW43438 wireless chip (wifi + bl).
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Until RPI 3 and Zero W the pl011 (uart0) was always on pin 14/15. So in
order to take care of them and other boards in the future,
we need to define UART pinmuxing on board level.
This work based on Eric Anholt's patch "ARM: bcm2385: Don't force pl011
onto pins 14/15." and Fabian Vogt's patch "ARM64: dts: bcm2837: assign
uart0 to BT and uart1 to pin headers".
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Eric Anholt <eric@anholt.net>
Northstar has 3 controllers: OHCI and EHCI (each with 2 ports) and XHCI
(with just 1 port). Describe them in the DT. In future this will allow
to reference them as trigger sources.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The clock controller provides a few reset lines as well. Add the
corresponding CPU cores.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add ethernet device node for MT2701
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add pin configuration for LED0 which is connected to a GPIO.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add pin configuration for SCIF2 serial console interface.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
