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ARM: dts: marvell: fix PCI bus dtc warnings

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dtc recently added PCI bus checks. Fix these warnings.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit is contained in:
Rob Herring 2017-07-26 16:09:37 -05:00 committed by Gregory CLEMENT
parent 5771a8c088
commit 28fbb9c539
28 changed files with 79 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/pci/mvebu-pci.txt
View File

@ -286,7 +286,7 @@ pcie-controller {
status = "disabled";
};
pcie@10,0 {
pcie@a,0 {
device_type = "pci";
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;

4
arch/arm/boot/dts/armada-370.dtsi
View File

@ -72,7 +72,7 @@ bootrom {
reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
};
pciec: pcie-controller@82000000 {
pciec: pcie@82000000 {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@ -100,6 +100,7 @@ pcie0: pcie@1,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
@ -117,6 +118,7 @@ pcie2: pcie@2,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;

4
arch/arm/boot/dts/armada-375.dtsi
View File

@ -582,7 +582,7 @@ coredivclk: corediv-clock@e8250 {
};
};
pciec: pcie-controller@82000000 {
pciec: pcie@82000000 {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@ -610,6 +610,7 @@ pcie0: pcie@1,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
@ -627,6 +628,7 @@ pcie1: pcie@2,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;

5
arch/arm/boot/dts/armada-380.dtsi
View File

@ -71,7 +71,7 @@ pinctrl@18000 {
};
};
pcie-controller {
pcie {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@ -104,6 +104,7 @@ pcie@1,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
@ -122,6 +123,7 @@ pcie@2,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
@ -140,6 +142,7 @@ pcie@3,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;

2
arch/arm/boot/dts/armada-385-db-ap.dts
View File

@ -209,7 +209,7 @@ bm-bppi {
status = "okay";
};
pcie-controller {
pcie {
status = "okay";
/*

2
arch/arm/boot/dts/armada-385-turris-omnia.dts
View File

@ -96,7 +96,7 @@ usb3@f8000 {
};
};
pcie-controller {
pcie {
status = "okay";
pcie@1,0 {

6
arch/arm/boot/dts/armada-385.dtsi
View File

@ -70,7 +70,7 @@ cpu@1 {
};
soc {
pciec: pcie-controller {
pciec: pcie {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@ -109,6 +109,7 @@ pcie1: pcie@1,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
@ -127,6 +128,7 @@ pcie2: pcie@2,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
@ -145,6 +147,7 @@ pcie3: pcie@3,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;
@ -166,6 +169,7 @@ pcie4: pcie@4,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <3>;

2
arch/arm/boot/dts/armada-388-clearfog.dts
View File

@ -62,7 +62,7 @@ usb3@f0000 {
};
};
pcie-controller {
pcie {
pcie@3,0 {
/* Port 2, Lane 0. CON2, nearest CPU. */
reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;

2
arch/arm/boot/dts/armada-388-clearfog.dtsi
View File

@ -104,7 +104,7 @@ usb3@f8000 {
};
};
pcie-controller {
pcie {
status = "okay";
/*
* The two PCIe units are accessible through

2
arch/arm/boot/dts/armada-388-db.dts
View File

@ -172,7 +172,7 @@ bm-bppi {
status = "okay";
};
pcie-controller {
pcie {
status = "okay";
/*
* The two PCIe units are accessible through

2
arch/arm/boot/dts/armada-388-gp.dts
View File

@ -240,7 +240,7 @@ bm-bppi {
status = "okay";
};
pcie-controller {
pcie {
status = "okay";
/*
* One PCIe units is accessible through

2
arch/arm/boot/dts/armada-388-rd.dts
View File

@ -117,7 +117,7 @@ usb3@f0000 {
};
};
pcie-controller {
pcie {
status = "okay";
/*
* One PCIe units is accessible through

2
arch/arm/boot/dts/armada-390-db.dts
View File

@ -123,7 +123,7 @@ usb3@f8000 {
};
};
pcie-controller {
pcie {
status = "okay";
/* CON30 */

2
arch/arm/boot/dts/armada-395-gp.dts
View File

@ -139,7 +139,7 @@ usb3@f0000 {
};
};
pcie-controller {
pcie {
status = "okay";
/*

2
arch/arm/boot/dts/armada-398-db.dts
View File

@ -118,7 +118,7 @@ usb3@f8000 {
};
};
pcie-controller {
pcie {
status = "okay";
pcie@1,0 {

6
arch/arm/boot/dts/armada-39x.dtsi
View File

@ -442,7 +442,7 @@ thermal@e8078 {
};
};
pcie-controller {
pcie {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@ -481,6 +481,7 @@ pcie@1,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
@ -499,6 +500,7 @@ pcie@2,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
@ -517,6 +519,7 @@ pcie@3,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;
@ -538,6 +541,7 @@ pcie@4,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <3>;

3
arch/arm/boot/dts/armada-xp-98dx3236.dtsi
View File

@ -91,7 +91,7 @@ bootrom {
/*
* 98DX3236 has 1 x1 PCIe unit Gen2.0
*/
pciec: pcie-controller@82000000 {
pciec: pcie@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@ -116,6 +116,7 @@ pcie1: pcie@1,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;

2
arch/arm/boot/dts/armada-xp-db.dts
View File

@ -242,7 +242,7 @@ pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
pcie@a,0 {
/* Port 3, Lane 0 */
status = "okay";
};

2
arch/arm/boot/dts/armada-xp-gp.dts
View File

@ -227,7 +227,7 @@ pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
pcie@a,0 {
/* Port 3, Lane 0 */
status = "okay";
};

7
arch/arm/boot/dts/armada-xp-mv78230.dtsi
View File

@ -86,7 +86,7 @@ soc {
* configured as x4 or quad x1 lanes. One unit is
* x1 only.
*/
pciec: pcie-controller@82000000 {
pciec: pcie@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@ -123,6 +123,7 @@ pcie1: pcie@1,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
@ -140,6 +141,7 @@ pcie2: pcie@2,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
@ -157,6 +159,7 @@ pcie3: pcie@3,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
@ -174,6 +177,7 @@ pcie4: pcie@4,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
@ -191,6 +195,7 @@ pcie5: pcie@5,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;

11
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View File

@ -87,7 +87,7 @@ soc {
* configured as x4 or quad x1 lanes. One unit is
* x4 only.
*/
pciec: pcie-controller@82000000 {
pciec: pcie@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@ -138,6 +138,7 @@ pcie1: pcie@1,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
@ -155,6 +156,7 @@ pcie2: pcie@2,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
@ -172,6 +174,7 @@ pcie3: pcie@3,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
@ -189,6 +192,7 @@ pcie4: pcie@4,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
@ -206,6 +210,7 @@ pcie5: pcie@5,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
@ -223,6 +228,7 @@ pcie6: pcie@6,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 63>;
marvell,pcie-port = <1>;
@ -240,6 +246,7 @@ pcie7: pcie@7,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>;
marvell,pcie-port = <1>;
@ -257,6 +264,7 @@ pcie8: pcie@8,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>;
marvell,pcie-port = <1>;
@ -274,6 +282,7 @@ pcie9: pcie@9,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;

14
arch/arm/boot/dts/armada-xp-mv78460.dtsi
View File

@ -104,7 +104,7 @@ soc {
* configured as x4 or quad x1 lanes. Two units are
* x4/x1.
*/
pciec: pcie-controller@82000000 {
pciec: pcie@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
@ -159,6 +159,7 @@ pcie1: pcie@1,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
@ -176,6 +177,7 @@ pcie2: pcie@2,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
@ -193,6 +195,7 @@ pcie3: pcie@3,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
@ -210,6 +213,7 @@ pcie4: pcie@4,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
@ -227,6 +231,7 @@ pcie5: pcie@5,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
@ -244,6 +249,7 @@ pcie6: pcie@6,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 63>;
marvell,pcie-port = <1>;
@ -261,6 +267,7 @@ pcie7: pcie@7,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>;
marvell,pcie-port = <1>;
@ -278,6 +285,7 @@ pcie8: pcie@8,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>;
marvell,pcie-port = <1>;
@ -295,6 +303,7 @@ pcie9: pcie@9,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
@ -303,7 +312,7 @@ pcie9: pcie@9,0 {
status = "disabled";
};
pcie10: pcie@10,0 {
pcie10: pcie@a,0 {
device_type = "pci";
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
@ -312,6 +321,7 @@ pcie10: pcie@10,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
0x81000000 0 0 0x81000000 0xa 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;

4
arch/arm/boot/dts/dove-d3plug.dts
View File

@ -88,7 +88,7 @@ spi-flash@0 {
&pcie {
status = "okay";
/* Fresco Logic USB3.0 xHCI controller */
pcie-port@0 {
pcie@1 {
status = "okay";
reset-gpios = <&gpio0 26 1>;
reset-delay-us = <20000>;
@ -96,7 +96,7 @@ pcie-port@0 {
pinctrl-names = "default";
};
/* Mini-PCIe slot */
pcie-port@1 {
pcie@2 {
status = "okay";
reset-gpios = <&gpio0 25 1>;
};

8
arch/arm/boot/dts/dove.dtsi
View File

@ -89,7 +89,7 @@ MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
pcie: pcie-controller {
pcie: pcie {
compatible = "marvell,dove-pcie";
status = "disabled";
device_type = "pci";
@ -106,7 +106,7 @@ pcie: pcie-controller {
0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
pcie0: pcie-port@0 {
pcie0: pcie@1 {
device_type = "pci";
status = "disabled";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
@ -118,13 +118,14 @@ pcie0: pcie-port@0 {
#size-cells = <2>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 16>;
};
pcie1: pcie-port@1 {
pcie1: pcie@2 {
device_type = "pci";
status = "disabled";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
@ -136,6 +137,7 @@ pcie1: pcie-port@1 {
#size-cells = <2>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;

3
arch/arm/boot/dts/kirkwood-6192.dtsi
View File

@ -1,6 +1,6 @@
/ {
mbus@f1000000 {
pciec: pcie-controller@82000000 {
pciec: pcie@82000000 {
compatible = "marvell,kirkwood-pcie";
status = "disabled";
device_type = "pci";
@ -24,6 +24,7 @@ pcie0: pcie@1,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 9>;
marvell,pcie-port = <0>;

3
arch/arm/boot/dts/kirkwood-6281.dtsi
View File

@ -1,6 +1,6 @@
/ {
mbus@f1000000 {
pciec: pcie-controller@82000000 {
pciec: pcie@82000000 {
compatible = "marvell,kirkwood-pcie";
status = "disabled";
device_type = "pci";
@ -24,6 +24,7 @@ pcie0: pcie@1,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 9>;
marvell,pcie-port = <0>;

4
arch/arm/boot/dts/kirkwood-6282.dtsi
View File

@ -1,6 +1,6 @@
/ {
mbus@f1000000 {
pciec: pcie-controller@82000000 {
pciec: pcie@82000000 {
compatible = "marvell,kirkwood-pcie";
status = "disabled";
device_type = "pci";
@ -28,6 +28,7 @@ pcie0: pcie@1,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 9>;
marvell,pcie-port = <0>;
@ -45,6 +46,7 @@ pcie1: pcie@2,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 10>;
marvell,pcie-port = <1>;

3
arch/arm/boot/dts/kirkwood-98dx4122.dtsi
View File

@ -1,6 +1,6 @@
/ {
mbus@f1000000 {
pciec: pcie-controller@82000000 {
pciec: pcie@82000000 {
compatible = "marvell,kirkwood-pcie";
status = "disabled";
device_type = "pci";
@ -24,6 +24,7 @@ pcie0: pcie@1,0 {
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 9>;
marvell,pcie-port = <0>;