There is actually no alternate xtal on any of the axg board I have
seen so far. The 32k is actually generated internally, deriving from
the 24MHz main xtal.
Amlogic SoC also have the option to provide the 32k reference externally,
through one of the AO pads, but no platform is using this ATM.
Fixes: 5e395e1466 ("ARM64: dts: meson-axg: add an 32K alt aoclk")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the watchdog node also on the AXG platforms.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add a node for the Camera Subsystem present on the Qualcomm
MSM8996 SoC.
Signed-off-by: Todor Tomov <todor.tomov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add pinctrls required for camera sensors:
- power down signal;
- reset signal;
- camera external clock.
Signed-off-by: Todor Tomov <todor.tomov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add pinctrls required for Camera Control Interface.
Signed-off-by: Todor Tomov <todor.tomov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add a node for the Camera Subsystem present on the Qualcomm
MSM8916 SoC.
Signed-off-by: Todor Tomov <todor.tomov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
- kernelci awaits a working stdout-path.
Fix the path for reference board and bananapi-r64
- general propouse timer has issues with clocks that didn't
get probed early. Delete the DT node as the timer isn't
need, a ARM arch timer exists on the system.
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Merge tag 'v4.19-next-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into fixes
DT mt7622:
- Kernelci awaits a working stdout-path.
Fix the path for reference board and bananapi-r64
- General propouse timer has issues with clocks that didn't
get probed early. Delete the DT node as the timer isn't
need, a ARM arch timer exists on the system.
* tag 'v4.19-next-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
arm64: dts: mt7622: Drop the general purpose timer node
arm64: dts: mt7622: fix no more console output on BPI-R64 board
arm64: dts: mt7622: fix no more console output on rfb1
Signed-off-by: Olof Johansson <olof@lixom.net>
The P2888 processor module contains a TI TMP451 temperature sensor with
two channels. These are used to measure the temperatures at different
locations on the module.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The power and force recovery buttons found on Jetson Xavier are hooked
up to two Tegra GPIOs. The power button can also function as a wake-up
source.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The AON GPIO controller is in an always-on power partition and typically
provides pins for functions that need to always work, such as the power
key for example.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The on-die RTC isn't hooked up to a backup battery, so it isn't useful
to track time across reboots, but as long as power remains enabled, it
keeps track of time accurately and can be used to wake the system from
sleep, for example.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The RTC on Tegra194 is very similar to the RTC on earlier generations.
One notable exception is that the source clock is now the 32 kHz clock
instead of a dedicated RTC clock and the RTC alarm is a wake event and
can be used to wake the system from sleep.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Wake events are a feature that allows the interrupt and GPIO controllers
to be powered off as part of system sleep. The PMC which is always on is
monitoring these wake events and can power up subsequent controllers as
necessary to process them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The on-die RTC isn't hooked up to a backup battery, so it isn't useful
to track time across reboots, but as long as power remains enabled, it
keeps track of time accurately and can be used to wake the system from
sleep, for example.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The RTC on Tegra186 is very similar to the RTC on earlier generations.
One notable exception is that the source clock is now the 32 kHz clock
instead of a dedicated RTC clock and the RTC alarm is a wake event and
can be used to wake the system from sleep.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Wake events are a feature that allows the interrupt and GPIO controllers
to be powered off as part of system sleep. The PMC which is always on is
monitoring these wake events and can power up subsequent controllers as
necessary to process them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
In order for the correct interrupt type to be configured, the event
action for the power key needs to be "asserted".
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable these thermal zones to be able to monitor their temperatures and
control the fan to cool down the system if necessary.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the 5V HDMI regulator and hook up the VDD_1V0 and VDD_1V8HS supplies
from the PMIC to the display block. Also enable the display hub which is
responsible for instantiating the display controllers. Finally, enable
the third SOR that drives the TMDS signals to the HDMI connector.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra194 has a version of VIC that is very similar to that on Tegra186.
Add the device tree node for it that is enabled by default.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra194 contains a display architecture very similar to that found on
the Tegra186. One notable exception is that DSI is no longer a supported
output. Instead there are four display controllers and four SORs (with a
DPAUX associated to each of them) that can drive HDMI or DP.
Signed-off-by: Thierry Reding <treding@nvidia.com>
* Hi3660 SoC and related boards:
- Standardize LED labels and triggers for the hikey960 board
- Add the missing cooling-cells property for the cpu nodes
- Add all cpus into the cooling maps
* Hi3670 SoC and related boards:
- Add clock nodes and update the uart clock
- Add Pinctrl, GPIO and uart nodes
- Enable uart and add GPIO line names for the hikey970 board
* Hi3798 SoC and related boards:
- Standardize LED labels and triggers for the poplar board
* Hi6220 SoC and related boards:
- Standardize LED labels and triggers for the hikey board
- Add all cpus into the cooling maps
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Merge tag 'hisi-arm64-dt-for-4.21' of git://github.com/hisilicon/linux-hisi into next/dt
ARM64: DT: Hisilicon SoCs DT updates for 4.21
* Hi3660 SoC and related boards:
- Standardize LED labels and triggers for the hikey960 board
- Add the missing cooling-cells property for the cpu nodes
- Add all cpus into the cooling maps
* Hi3670 SoC and related boards:
- Add clock nodes and update the uart clock
- Add Pinctrl, GPIO and uart nodes
- Enable uart and add GPIO line names for the hikey970 board
* Hi3798 SoC and related boards:
- Standardize LED labels and triggers for the poplar board
* Hi6220 SoC and related boards:
- Standardize LED labels and triggers for the hikey board
- Add all cpus into the cooling maps
* tag 'hisi-arm64-dt-for-4.21' of git://github.com/hisilicon/linux-hisi:
ARM64: dts: hisilicon: Add all CPUs in cooling maps
arm64: dts: hi3660: Add missing cooling device properties for CPUs
arm64: dts: hisilicon: poplar: Standardize LED labels and triggers
arm64: dts: hisilicon: hikey960: Standardize LED labels and triggers
arm64: dts: hisilicon: hikey: Standardize LED labels and triggers
arm64: dts: hisilicon: hikey970: Add GPIO line names
arm64: dts: hisilicon: hikey970: Enable on-board UARTs
arm64: dts: hisilicon: hi3670: Add UART nodes
arm64: dts: hisilicon: hi3670: Add GPIO controller support
arm64: dts: hisilicon: Add Pinctrl support for HiKey970 board
arm64: dts: hisilicon: Source SoC clock for UART6
arm64: dts: hisilicon: Add clock nodes for Hi3670 SoC
Signed-off-by: Olof Johansson <olof@lixom.net>
This updates the Versatile Express family DTS files to
contain the correct and detailed information required
for the PL11x DRM driver to work properly.
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Merge tag 'vexpress-drm-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/dt
Versatile Express DTS update for DRM:
This updates the Versatile Express family DTS files to
contain the correct and detailed information required
for the PL11x DRM driver to work properly.
* tag 'vexpress-drm-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: dts: Modernize the Vexpress PL111 integration
Signed-off-by: Olof Johansson <olof@lixom.net>
- Use SPDX license identifier for all SoCFPGA DTS files.
- Remove dma-mask property as it has been deprecated.
- Use tabs in DTS files.
- Use the specific "altr,stratix10-rst-mgr" property for the Stratix10
reset manager.
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Merge tag 'socfpga_dts_updates_for_v5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
SoCFPGA DTS updates for v5.0
- Use SPDX license identifier for all SoCFPGA DTS files.
- Remove dma-mask property as it has been deprecated.
- Use tabs in DTS files.
- Use the specific "altr,stratix10-rst-mgr" property for the Stratix10
reset manager.
* tag 'socfpga_dts_updates_for_v5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: stratix10: use "altr,stratix10-rst-mgr" binding
ARM: dts: socfpga: use tabs for indentation
arm: dts: socfpga: remove dma-mask property
arm: dts: socfpga*.dts*: use SPDX-License-Identifier
Signed-off-by: Olof Johansson <olof@lixom.net>
for all Gru devices, rk3399 spi dma properties, some improvements for
the rk3399-sapphire board (fan, chosen, backlight), hs200 mode for the
emmc on the rock64 and declaring all cpu cores in the cooling maps
instead of just cpu0.
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Merge tag 'v4.21-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
New dts for Gru-Scarlet (tablet device), default backlight brightness
for all Gru devices, rk3399 spi dma properties, some improvements for
the rk3399-sapphire board (fan, chosen, backlight), hs200 mode for the
emmc on the rock64 and declaring all cpu cores in the cooling maps
instead of just cpu0.
* tag 'v4.21-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Add all CPUs in cooling maps
arm64: dts: rockchip: add Gru Scarlet devicetrees
arm64: dts: rockchip: move backlight from rk3399 sapphire to excavator
arm64: dts: rockchip: Use default brightness table for rk3399-gru
arm64: dts: rockchip: add chosen node on rk3399-sapphire
arm64: dts: rockchip: enable HS200 for eMMC on rock64
arm64: dts: rockchip: add fan on rk3399-sapphire board
arm64: dts: rockchip: add rk3399 SPI DMAs
Signed-off-by: Olof Johansson <olof@lixom.net>
and fixup of the pcie reset polarity on puma-haikou.
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Merge tag 'v4.20-rockchip-dts64fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixes
Removal of vdd_log regulator on rk960 to fix a stability issue
and fixup of the pcie reset polarity on puma-haikou.
* tag 'v4.20-rockchip-dts64fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Fix PCIe reset polarity for rk3399-puma-haikou.
arm64: dts: rockchip: remove vdd_log from rock960 to fix a stability issues
Signed-off-by: Olof Johansson <olof@lixom.net>
Deassert the reset and wireless disable signals on the CON2 mini-PCIe
socket. That allows the host to detect USB devices on the mini-PCIe
socket.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This reset signal controls the Marvell 1512 1G PHY.
Note that current implementation queries the PHY over the MDIO bus
(get_phy_device() call from of_mdiobus_register_phy()) before reset
signal deassert. If the PHY reset signal is asserted at boot time, PHY
registration fails. So current code relies on the bootloader to deassert
the reset signal.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The fixed regulator driver ignores the gpio flags, so this change has
no practical effect in the current implementation. Fix it anyway to
correct the hardware description.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The scm binding and driver was updated to rely on the fallback to the
default qcom,scm for any modern SoC and as such both are required. Add
the default compatible to make the scm instance probe.
Fixes: d850156a22 ("arm64: dts: qcom: msm8998: Add firmware node")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
While commit 3b7e7848f0 ("arm64: dts: renesas: r8a7795: Add IPMMU
device nodes") for R-Car H3 ES2.0 did include power-domains properties,
they were forgotten in the counterpart for older R-Car H3 ES1.x SoCs.
Fixes: e4b9a493df ("arm64: dts: renesas: r8a7795-es1: Add IPMMU device nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Aug 24, 2018)
removed the IPMMU-IR IOMMU instance on R-Car M3-N, as this SoC does not
have an Image Processing Unit (IMP-X5) nor the A3IR power domain.
Fixes: 55697cbb44 ("arm64: dts: renesas: r8a779{65,80,90}: Add IPMMU devices nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
AXP803 ACIN pins are routed from SOM to the DC jack on the baseboard.
AXP803 charger pins BATSENSE, LOADSENSE, N_BATDRV, LX_CHG, VIN_CHG
and IPSOUT are connected via PMOS driver to SOM VBAT pins. VBAT and
AXP803 TS pins are routed to the baseboard 3-pin battery connector.
Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
Reviewed-by: Quentin Schulz <quentin.schulz@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Parts of the AXP803 are compatible with their counterparts on the AXP813.
Add DT nodes ADC, GPIO, AC and battery power supplies.
Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
Reviewed-by: Quentin Schulz <quentin.schulz@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The SDC2 control pins are typically used to manage sleep.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The externally accessible SD card slot on the MTP is driven by SDCC2.
Wire it up for use.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
SDCC2 is typically used as the controller for an external SD card slot.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The root parent clock of most msm8998 clock is the "xo" clock. The DT node
is incorrectly named "xo_board", which prevents Linux from correctly
parsing the clock tree, resulting in most clocks being unparented and
unable to be manipulated. The end result is that we can't turn on clocks
for peripherals like SD, so init usually fails.
Fixes: 4807c71cc6 (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The Amlogic Meson GX SoCs embeds a clock measurer IP to measure the internal
clock paths frequencies.
This patch adds the node in the top-level meson-gx dtsi.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This patch adds support for the Phicomm N1. This device based on P230 reference design.
And this box doesn't have cvbs, so disable related section in device tree.
Signed-off-by: He Yangxuan <yangxuan8282@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
On Amlogic chipsets, the bias set through pinconf applies to the pad
itself, not only the GPIO function. This means that even when we change
the function of the pad from GPIO to anything else, the bias previously
set still applies.
As we have seen with the eMMC, depending on the bias type and the function,
it may trigger problems.
The underlying issue is that we inherit whatever was left by previous user
of the pad (pinconf, u-boot or the ROM code). As a consequence, the actual
setup we will get is undefined.
There is nothing mentioned in the documentation about pad bias and pinmux
function, however leaving it undefined is not an option.
This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
In some cases (such as a boot from SPI) the bootloader or the ROM code may
leave a bias pull-down on the mmc pins. If so the MMC will fail during the
initialisation.
Explicitly disabling the pinmux solves the problem.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
In the pinmux of the mmc clk_gate nodes, we define 2 subnodes. One for
the function definition, the other for the bias. This is not necessary
since we can define the function and the bias in the same subnode.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This patch disable EEE advertisement for P230 board (DWMAC + RTL8211F).
If not disable it, the network connection is not stable, will got issues
like throughput drop or broken link.
Signed-off-by: He Yangxuan <yangxuan8282@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Enable SCPI on the axg platform, with cpu clock and hwmon
(core temperature) support
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Correct the unit-address in the node name of the SRAM shared memory
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
MHU mailbox address is wrong. Fixing it enables the mailboxes on the A113.
These mailboxes are needed for SCPI
Fixes: 9d59b70850 ("arm64: dts: meson-axg: add initial A113D SoC DT support")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The hdmi_5v regulator must be enabled to provide power to the physical HDMI
PHY and enables the HDMI 5V presence loopback for the monitor.
Fixes: b409f625a6 ("ARM64: dts: meson-gx: Add HDMI_5V regulator on selected boards")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the secure monitor device to the axg platform.
With this, we can read the SoC serial number.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The uart used with bluetooth chipset on the s400 has flow control
available. Let's enable it.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The gpio line names were set in the pinctrl node instead of the gpio node,
at the time it was merged, it worked, but was obviously wrong.
This patch moves the properties to the gpio nodes.
Fixes: 60795933b7 ("ARM64: dts: meson-gxl-khadas-vim: Add GPIO lines names")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The gpio line names were set in the pinctrl node instead of the gpio node,
at the time it was merged, it worked, but was obviously wrong.
This patch moves the properties to the gpio nodes.
Fixes: b03c7d6438 ("ARM64: dts: meson-gxbb-odroidc2: Add GPIO lines names")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The gpio line names were set in the pinctrl node instead of the gpio node,
at the time it was merged, it worked, but was obviously wrong.
This patch moves the properties to the gpio nodes.
Fixes: 12ada0513d ("ARM64: dts: meson-gxbb-nanopi-k2: Add GPIO lines names")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The gpio line names were set in the pinctrl node instead of the gpio node,
at the time it was merged, it worked, but was obviously wrong.
This patch moves the properties to the gpio nodes.
Fixes: 47884c5c74 ("ARM64: dts: meson-gxl-libretech-cc: Add GPIO lines names")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
section 2.2.1 of the DT specs says: " If the node has no reg property,
the @unit-address must be omitted and the node-name alone differentiates
the node from other nodes at the same level in the tree"
Simply replace the '@' with a '-' to fix this warning.
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This enables Bluetooth support for the following models:
- Khadas VIM basic (AP6212) using firmware BCM43438A1.hcd
- Khadas VIM pro (AP6255) using firmware BCM4345C0.hcd
The AP6212 module used on the VIM basic has an ID clash with another
device. To get Bluetooth working you either need to apply a kernel
patch to drivers/bluetooth/btbcm.c so 0x2209 loads BCM43438A1 or the
BCM43438A1.hcd firmware must be renamed to BCM43430A1.hcd.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add such missing properties.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
For all 96Boards, the following standard is used for onboard LEDs.
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-indicator
yellow:wlan default-trigger: phy0tx
blue:bt default-trigger: hci0-power
So lets adopt the same for Poplar, which is one of the 96Boards
Enterprise edition platform.
Due to absence of WLAN and BT support, corresponding LED nodes are not
considered.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
For all 96Boards, the following standard is used for onboard LEDs.
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-indicator
yellow:wlan default-trigger: phy0tx
blue:bt default-trigger: hci0-power
So lets adopt the same for HiKey960 which is one of the 96Boards
CE platform.
Since there is no trigger available for onboard-storage UFS now, user2
trigger is set to none.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
For all 96Boards, the following standard is used for onboard LEDs.
green:user1 default-trigger: heartbeat
green:user2 default-trigger: mmc0/disk-activity(onboard-storage)
green:user3 default-trigger: mmc1 (SD-card)
green:user4 default-trigger: none, panic-indicator
yellow:wlan default-trigger: phy0tx
blue:bt default-trigger: hci0-power
So lets adopt the same for HiKey, which is one of the 96Boards
CE platform.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add GPIO line names for HiSilicon HiKey970 board based on HI3670 SoC.
The Line names are derived from "hikey970-schematics.pdf" document and
named in conjunction with 96Boards CE Specification v1.0.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
The Versatile Express was submitted with the actual display
bridges unconnected (but defined in the device tree) and
mock "panels" encoded in the device tree node of the PL111
controller.
This doesn't even remotely describe the actual Versatile
Express hardware. Exploit the SiI9022 bridge by connecting
the PL111 pads to it, making it use EDID or fallback values
to drive the monitor.
The also has to use the reserved memory through the
CMA pool rather than by open coding a memory region and
remapping it explicitly in the driver. To achieve this,
a reserved-memory node must exist in the root of the
device tree, so we need to pull that out of the
motherboard .dtsi include files, and push it into each
top-level device tree instead.
We do the same manouver for all the Versatile Express
boards, taking into account the different location of the
video RAM depending on which chip select is used on
each platform.
This plays nicely with the new PL111 DRM driver and
follows the standard ways of assigning bridges and
memory pools for graphics.
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Mali DP Maintainers <malidp@foss.arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Tested-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The official name for the P2972-0000 board is Jetson AGX Xavier
Development Kit. Set that as the model string in the device tree for
clarity.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Populate the power-domain properties for the xHCI device for Tegra210.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The standard reset-simple driver the uses the "altr,rst-mgr" binding is
not getting initialized early enough in the boot process, so timers
that the kernel needs are still left in reset. Thus an early
reset driver was created. This early reset driver is only for the
SoCFPGA 32-bit platform.
The Stratix10 platform does not need any of the timers that in reset to
boot, thus we don't need to early reset driver. Therefore, use the
"altr,stratix10-rst-mgr" binding for the reset-simple platform driver on
the Stratix10 platform.
Also remove the "altr,modrst-offset" property because the driver no
longer needs it.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Add pinctrl support based on "pinctrl-single" driver for HiKey970
development board from HiSilicon.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This adds the 32k clock to the RK3399 Gru board file, which is provided
by a Silego oscillator on Gru boards.
Even though it's not directly used, muxes will end up traversing the
entire clk tree on calls to determine_rate if it doesn't exist. This
is because the 32k clk is listed as a possible parent on some clks.
Since the clk doesn't know about the 32k clk (it was never registered),
it triggers a global search for it. This can happen about 40 times per
second, which isn't great for power.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
[moved clock position and adapted commit message a bit]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
As of v4.20-rc1 probing the GCC driver on a SDM845 device with the
standard security implementation causes an access violation and an
immediate system restart. Use the protected-clocks property to mark the
offending clocks protected for the MTP, in order to allow it to boot.
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This patch enables audio via the SoC's internal audio codec. All
relevant device nodes are enabled, and the routing is set to match
the board design. MIC1 is routed to an onboard microphone, with MBIAS
providing power. MIC2 and HP are routed to the 3.5mm headset TRRS jack.
No phantom power is provided to the headset microphone.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add the Stratix10 FPGA manager and a FPGA region to the
device tree.
Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Richard Gong <richard.gong@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add Intel Stratix10 service layer to the device tree
Signed-off-by: Richard Gong <richard.gong@intel.com>
Signed-off-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
MediaTeks general purpose timer register into system in early phase
during kernel boot, but the clock sources aren't probed at this point.
The system has the ARM architecture timer, so we don't need the GPT
timer from mediatek. Drop the DT node for it.
Fixes: 9cc7f0de9e ("arm64: dts: mt7622: add timer, CCI-400 and PMU nodes")
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
[mb: fix commit message]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds the thermal device node and the thermal-zone for
the R8A77990 SoC.
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Pinebook has a headphone jack tied to the HP headphone output of
the SoC, and internal speakers connected to the LINEOUT of the SoC,
through a standalone amplifier.
This commit enables I2S, digital and analog parts of audio codec on
Pinebook, along with a device node for the external amplifier.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[wens@csie.org: dropped headphone_amp; added headphone amp regulator supply;
fixed speaker_amp node name and sound-name-prefix name]
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
This commit enables I2S, digital and analog parts of audiocodec on
Pine64 and SoPine boards.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[wens@csie.org: Dropped headphone_amp; added headphone amp regulator supply]
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Add nodes for i2s, digital and analog parts of audiocodec on A64.
The routing paths listed are entries connecting the digital and analog
side of the audio codec together. Due to how device tree works, these
must be copied over to each board device tree, in addition to any board
level routes.
The oversampling rate is set to 128, so that when playing back 192 kHz
audio samples, the MCLK runs at the same rate as the module clock, at
24.576 MHz.
The user manual suggests using different oversampling rates for different
sample rates, but that's not possible without a platform-specific machine
driver.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[wens@csie.org: Lowered oversampling rate to 128; expanded commit message]
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
rsnd driver supports SSIU now, let's use it.
Then, BUSIF DMA settings on rcar_sound,ssi (= rxu, txu) are
no longer needed.
To avoid git merge timing issue / git bisect issue,
this patch doesn't remove it so far, but will be removed in
the future.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds I2C-DVFS device node for the R8A77990 SoC.
v2
* Drop aliases update as in upstream it is not required to configure the
BD9571 PMIC for DDR backup, nor is the use of i2c are aliases desired.
* Do not describe the device as compatible with "renesas,rcar-gen3-iic" or
"renesas,rmobile-iic" fallback compat strings. The absence of automatic
transmission registers leads us to declare the r8a77990 IIC controller as
incompatible.
v2.1
* Reduced register range to reflect documentation
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds CAN0,1 and CANFD device nodes for the r8a77990 SoC
and enables CANFD connected to CN10 on the E3 Ebisu board using the
R8A77990 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fix this by using a 'stdout-path' property that points to the device.
Fixes: 0b6286dd96 ("arm64: dts: mt7622: add bananapi BPI-R64 board")
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
No default serial console on boot.
Fix this by using a 'stdout-path' property that points to the device.
Fixes: c0d9f9ad4f ("arm64: dts: mt7622: add earlycon to mt7622-rfb1 board")
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
[mb: Fix commit message]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This patch adds CAN{0,1} and CANFD controller nodes for the R8A77965 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Orange Pi Lite 2 and Orange Pi One Plus both have two LEDs, one red
and one green. These are driven directly by GPIO lines in an active high
arrangement. The red LED is labeled "power", so it is set to be on by
default.
Note that the default drive current for the GPIO lines makes the LEDs
very bright.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The Orange Pi Lite 2 and Orange Pi One Plus share the same design for
their USB 2.0 ports. VBUS is directly tied to the board wide 5V rail,
which is also directly tied to the DC jack. There is no current limiting
in this design.
This patch enables all the USB 2.0 related device nodes, and sets the
VBUS regulator supplies and OTG ID detection GPIO.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The Orange Pi Lite 2 and Orange Pi One Plus share the same design for
their USB 2.0 ports. VBUS is directly tied to the board wide 5V rail,
which is also directly tied to the DC jack. There is no current limiting
in this design. This 5V rail also supplies the various inputs to the
PMIC.
This patch adds a board wide 5V regulator and sets it as the input to
the PMIC inputs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The SoC-specific compatible should come before the fallback compatible
string when multiple compatible strings are present, but the sequence is
wrong currently on H6 EMAC node (A64 fallback before H6 compatible).
Fix the sequence.
Fixes: c8ced5516d ("arm64: allwinner: h6: add EMAC device nodes")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add support for Allwinner A64 has Mali-400MP2.
All interrupt lines are mentioned in the manual so used the same.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch adds PCI express channel 0 device node to the R8A77990 SoC
and enables PCIEC0 PCI express controller on the Ebisu board.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
PMS405 also features PON block, so add PON and PWRKEY nodes
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
We can use BAM DAM for serial UART data transfers, so add it
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the BAM DMA instance found in BLSP1 node of the QCS404
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
RNG hardware in QCS404 features (Execution Environment) EE for
HLOS to use, add the node for prng-ee for QCS404.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the TrustZone based remoteproc nodes and their glink edges for
adsp, cdsp and wcss. Enable them for EVB common DTS.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
RTC is found on PMIC PMS405 and is same as other PMIC used, so add the
rtc node with compatible as qcom,pm8941-rtc
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
PMS405 is used in QCS405-EVB so include that with SPMI nodes
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the sdcc1 node and enable it for the QCS404-EVB.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the QCS404 TLMM pinctrl node with its three tiles.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the smp2p-adsp, smp2p-cdsp and smp2p-wcss nodes found in QCS404.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the RPM regulators found in PMS405 which is used in qcs404-evb
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add RPM GLINK node and the RPM message ram, hwspinlock, APCS apps global
and smem nodes it depends on.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the reserved memory regions in QCS404
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
QCS404 has two EVBs, EVB-1000 and EVB-4000. These boards are mostly
similar with few differences in the peripherals used.
So use a common qcs404-evb.dtsi which contains the common parts and use
qcs404-evb-1000.dts and qcs404-evb-4000.dts for diffs
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add base dts files for QCS404 chipset along with cpu, timer,
gcc and uart2 nodes.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
s/_/-/ for node names.
It fixes warnings like this:
... Warning (node_name_chars_strict): /cpu_opp_table:
Character '_' not recommended in node name ...
Issues reported by make dtbs W=12
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add the required peripheral clock for the efuse device.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
RNG hardware in SDM845 features (Execution Environment) EE for
HLOS to use, add the node for prng-ee for sdm845.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
RNG hardware in 8996 features (Execution Environment) EE for
HLOS to use, add the node for prng-ee for msm8996.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Set the capacity-dmips-mhz for R-Car Gen3 SoCs, that is based on
dhrystone. The average in 10 times of dhrystone result as follows:
r8a7795 SoC (A57x4 + A53x4)
CPU max-freq dhrystone
---------------------------------
A57 1500 MHz 11470943 lps/s
A53 1200 MHz 4798583 lps/s
r8a7796 SoC (A57x2 + A53x4)
CPU max-freq dhrystone
---------------------------------
A57 1500 MHz 11463526 lps/s
A53 1200 MHz 4793276 lps/s
Based on above, capacity-dmips-mhz values are calculated as follows:
r8a7795 SoC
A57 : 1024 / (11470943 / 1500) * (11470943 / 1500) = 1024
A53 : 1024 / (11470943 / 1500) * ( 4798583 / 1200) = 535
r8a7796 SoC
A57 : 1024 / (11463526 / 1500) * (11463526 / 1500) = 1024
A53 : 1024 / (11463526 / 1500) * ( 4793276 / 1200) = 535
However, since each CPUs have different max frequencies, the final
CPU capacities of A53 are scaled by this difference, the values are
as follows.
[r8a7795 SoC]
$ cat /sys/devices/system/cpu/cpu*/cpu_capacity
1024 <---- CPU capacity of A57
1024
1024
1024
428 <---- CPU capacity of A53
428
428
428
[r8a7796 SoC]
$ cat /sys/devices/system/cpu/cpu*/cpu_capacity
1024 <---- CPU capacity of A57
1024
428 <---- CPU capacity of A53
428
428
428
Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds the "cpu-map" into r8a7795/r8a7796 composed of
multi-cluster. This definition is used to parse the cpu topology.
Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Pine H64 board has both the USB2 OTG pins and the USB2 host pins on H6
SoC wired out to USB Type-A ports.
Enable them.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The 5V output of the USB ports on Pine H64 is controlled via a GPIO.
Add the USB Vbus regulator device tree node.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Allwinner H6 has two USB2 ports, one OTG and one host-only.
Add device tree nodes related to them.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Add a channel node for the die temperature to the ADC.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
One thermal zone per cpu is defined
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Tested-by: Matthias Kaehlcke <mka@chromium.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Initialise the camera thermal zone to export temperature to userspace.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Initialise the gpu thermal zone to export temperature to userspace.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This new property allows the number of sensors to be configured from DT
instead of being hardcoded in platform data. Use it.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
We've earlier added support to split the register address space into TM
and SROT regions. Split up the regmap address space into two for msm8916
that has a similar register layout.
Since tsens-common.c/init_common() currently only registers one address
space, the order is important (TM before SROT). This is OK since the
code doesn't really use the SROT functionality yet.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Update DWC3 hardware modules to Exynos5433 specific variant: change
compatible name and add all required clocks (both to the glue node and
DWC3 core node).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
