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ARM64: DT: Hisilicon SoCs DT updates for 4.21

Browse Source 
* Hi3660 SoC and related boards:
   - Standardize LED labels and triggers for the hikey960 board
   - Add the missing cooling-cells property for the cpu nodes
   - Add all cpus into the cooling maps
 
 * Hi3670 SoC and related boards:
   - Add clock nodes and update the uart clock
   - Add Pinctrl, GPIO and uart nodes
   - Enable uart and add GPIO line names for the hikey970 board
 
 * Hi3798 SoC and related boards:
   - Standardize LED labels and triggers for the poplar board
 
 * Hi6220 SoC and related boards:
   - Standardize LED labels and triggers for the hikey board
   - Add all cpus into the cooling maps
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Merge tag 'hisi-arm64-dt-for-4.21' of git://github.com/hisilicon/linux-hisi into next/dt

ARM64: DT: Hisilicon SoCs DT updates for 4.21

* Hi3660 SoC and related boards:
  - Standardize LED labels and triggers for the hikey960 board
  - Add the missing cooling-cells property for the cpu nodes
  - Add all cpus into the cooling maps

* Hi3670 SoC and related boards:
  - Add clock nodes and update the uart clock
  - Add Pinctrl, GPIO and uart nodes
  - Enable uart and add GPIO line names for the hikey970 board

* Hi3798 SoC and related boards:
  - Standardize LED labels and triggers for the poplar board

* Hi6220 SoC and related boards:
  - Standardize LED labels and triggers for the hikey board
  - Add all cpus into the cooling maps

* tag 'hisi-arm64-dt-for-4.21' of git://github.com/hisilicon/linux-hisi:
  ARM64: dts: hisilicon: Add all CPUs in cooling maps
  arm64: dts: hi3660: Add missing cooling device properties for CPUs
  arm64: dts: hisilicon: poplar: Standardize LED labels and triggers
  arm64: dts: hisilicon: hikey960: Standardize LED labels and triggers
  arm64: dts: hisilicon: hikey: Standardize LED labels and triggers
  arm64: dts: hisilicon: hikey970: Add GPIO line names
  arm64: dts: hisilicon: hikey970: Enable on-board UARTs
  arm64: dts: hisilicon: hi3670: Add UART nodes
  arm64: dts: hisilicon: hi3670: Add GPIO controller support
  arm64: dts: hisilicon: Add Pinctrl support for HiKey970 board
  arm64: dts: hisilicon: Source SoC clock for UART6
  arm64: dts: hisilicon: Add clock nodes for Hi3670 SoC

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-11-30 15:46:17 -08:00
commit b71a29d57d
8 changed files with 1128 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
View File

@ -85,36 +85,36 @@ leds {
compatible = "gpio-leds";
user_led1 {
label = "user_led1";
label = "green:user1";
/* gpio_150_user_led1 */
gpios = <&gpio18 6 0>;
linux,default-trigger = "heartbeat";
};
user_led2 {
label = "user_led2";
label = "green:user2";
/* gpio_151_user_led2 */
gpios = <&gpio18 7 0>;
linux,default-trigger = "mmc0";
linux,default-trigger = "none";
};
user_led3 {
label = "user_led3";
label = "green:user3";
/* gpio_189_user_led3 */
gpios = <&gpio23 5 0>;
default-state = "off";
linux,default-trigger = "mmc0";
};
user_led4 {
label = "user_led4";
label = "green:user4";
/* gpio_190_user_led4 */
gpios = <&gpio23 6 0>;
panic-indicator;
linux,default-trigger = "cpu0";
linux,default-trigger = "none";
};
wlan_active_led {
label = "wifi_active";
label = "yellow:wlan";
/* gpio_205_wifi_active */
gpios = <&gpio25 5 0>;
linux,default-trigger = "phy0tx";
@ -122,7 +122,7 @@ wlan_active_led {
};
bt_active_led {
label = "bt_active";
label = "blue:bt";
gpios = <&gpio25 7 0>;
/* gpio_207_user_led1 */
linux,default-trigger = "hci0-power";

16
arch/arm64/boot/dts/hisilicon/hi3660.dtsi
View File

@ -79,6 +79,7 @@ cpu1: cpu@1 {
capacity-dmips-mhz = <592>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
cpu2: cpu@2 {
@ -91,6 +92,7 @@ cpu2: cpu@2 {
capacity-dmips-mhz = <592>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
cpu3: cpu@3 {
@ -103,6 +105,7 @@ cpu3: cpu@3 {
capacity-dmips-mhz = <592>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
cpu4: cpu@100 {
@ -129,6 +132,7 @@ cpu5: cpu@101 {
capacity-dmips-mhz = <1024>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
};
cpu6: cpu@102 {
@ -141,6 +145,7 @@ cpu6: cpu@102 {
capacity-dmips-mhz = <1024>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
};
cpu7: cpu@103 {
@ -153,6 +158,7 @@ cpu7: cpu@103 {
capacity-dmips-mhz = <1024>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
};
idle-states {
@ -1112,12 +1118,18 @@ cooling-maps {
map0 {
trip = <&target>;
contribution = <1024>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&target>;
contribution = <512>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

340
arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
View File

@ -10,12 +10,19 @@
/dts-v1/;
#include "hi3670.dtsi"
#include "hikey970-pinctrl.dtsi"
/ {
model = "HiKey970";
compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
serial6 = &uart6; /* console UART */
};
@ -30,6 +37,337 @@ memory@0 {
};
};
&uart6 {
/*
* Legend: proper name = the GPIO line is used as GPIO
* NC = not connected (pin out but not routed from the chip to
* anything the board)
* "[PER]" = pin is muxed for [peripheral] (not GPIO)
* "" = no idea, schematic doesn't say, could be
* unrouted (not connected to any external pin)
* LSEC = Low Speed External Connector
* HSEC = High Speed External Connector
*
* Line names are taken from "hikey970-schematics.pdf" from HiSilicon.
*
* For the lines routed to the external connectors the
* lines are named after the 96Boards CE Specification 1.0,
* Appendix "Expansion Connector Signal Description".
*
* When the 96Board naming of a line and the schematic name of
* the same line are in conflict, the 96Board specification
* takes precedence, which means that the external UART on the
* LSEC is named UART0 while the schematic and SoC names this
* UART2. This is only for the informational lines i.e. "[FOO]",
* the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
* ones actually used for GPIO.
*/
&gpio0 {
/* GPIO_000-GPIO_007 */
gpio-line-names =
"",
"TP901", /* TEST_MODE connected to TP901 */
"",
"GPIO_003_USB_HUB_RESET_N",
"NC",
"[AP_GPS_REF_CLK]",
"[I2C3_SCL]",
"[I2C3_SDA]";
};
&gpio1 {
/* GPIO_008-GPIO_015 */
gpio-line-names =
"[UART0_CTS]", /* LSEC pin 3: GPIO_008_UART2_CTS_N */
"[UART0_RTS]", /* LSEC pin 9: GPIO_009_UART2_RTS_N */
"[UART0_TXD]", /* LSEC pin 5: GPIO_010_UART2_TXD */
"[UART0_RXD]", /* LSEC pin 7: GPIO_011_UART2_RXD */
"[USER_LED5]",
"GPIO-I", /* LSEC pin 31: GPIO_013_CAM0_RST_N */
"[USER_LED3]",
"[USER_LED4]";
};
&gpio2 {
/* GPIO_016-GPIO_023 */
gpio-line-names =
"GPIO-G", /* LSEC pin 29: GPIO_016_LCD_TE0 */
"[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */
"[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */
"GPIO_019_BT_ACTIVE",
"[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */
"[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */
"[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */
"[I2C3_SDA]"; /* HSEC pin 38: ISP_SDA1 */
};
&gpio3 {
/* GPIO_024-GPIO_031 */
gpio-line-names =
"GPIO_024_WIFI_ACTIVE",
"GPIO_025_PERST_M.2",
"[I2C4_SCL]",
"[I2C4_SDA]",
"NC",
"GPIO-H", /* LSEC pin 30: GPIO_029_LCD_RST_N */
"[USER_LED1]",
"GPIO-L"; /* LSEC pin 34: GPIO_031 */
};
&gpio4 {
/* GPIO_032-GPIO_039 */
gpio-line-names =
"GPIO-K", /* LSEC pin 33: GPIO_032_CAM1_RST_N */
"GPIO_033_PMU1_EN",
"GPIO_034_USBSW_SEL",
/*
* These two pins should be used for SD(IO) data according
* to the 96boards specification but seems to be repurposed
* for UART 0. They are however named according to the spec.
*/
"[SD_DAT1]", /* HSEC pin 3: GPIO_035_UART0_RXD */
"[SD_DAT2]", /* HSEC pin 5: GPIO_036_UART0_TXD */
"[UART1_RXD]", /* LSEC pin 13: DEBUG_UART6_RXD */
"[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */
"[SOC_GPS_UART3_CTS_N]"; /* TP2304 */
};
&gpio5 {
/* GPIO_040-GPIO_047 */
gpio-line-names =
"[SOC_GPS_UART3_RTS_N]", /* TP2302 */
"[SOC_GPS_UART3_RXD]", /* TP2303 */
"[SOC_GPS_UART3_TXD]", /* TP2305 */
"[SOC_BT_UART4_CTS_N]",
"[SOC_BT_UART4_RTS_N]",
"[SOC_BT_UART4_RXD]",
"[SOC_BT_UART4_TXD]",
"NC";
};
&gpio6 {
/* GPIO_048-GPIO_055 */
gpio-line-names =
"NC",
"GPIO_049_USER_LED6",
"GPIO_050_CAN_RST",
"GPIO_051_WIFI_EN",
"GPIO-D", /* LSEC pin 26 */
"GPIO-J", /* LSEC pin 32 */
"GPIO_054_BT_EN",
"[GPIO_055_SEL]";
};
&gpio7 {
/* GPIO_056-GPIO_063 */
gpio-line-names =
"[PCIE_PERST_L]", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};
&gpio8 {
/* GPIO_064-GPIO_071 */
gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};
&gpio9 {
/* GPIO_072-GPIO_079 */
gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};
&gpio10 {
/* GPIO_080-GPIO_087 */
gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};
&gpio11 {
/* GPIO_088-GPIO_095 */
gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};
&gpio12 {
/* GPIO_096-GPIO_103 */
gpio-line-names = "NC", "", "", "", "", "", "", "";
};
&gpio13 {
/* GPIO_104-GPIO_111 */
gpio-line-names = "", "", "", "", "", "", "", "";
};
&gpio14 {
/* GPIO_112-GPIO_119 */
gpio-line-names = "", "", "", "", "", "", "", "";
};
&gpio15 {
/* GPIO_120-GPIO_127 */
gpio-line-names = "", "", "", "", "", "", "", "";
};
&gpio16 {
/* GPIO_128-GPIO_135 */
gpio-line-names =
"[WL_SDIO_CLK]",
"[WL_SDIO_CMD]",
"[WL_SDIO_DATA0]",
"[WL_SDIO_DATA1]",
"[WL_SDIO_DATA2]",
"[WL_SDIO_DATA3]",
"[ETH_ISOLATE]",
"NC";
};
&gpio17 {
/* GPIO_136-GPIO_143 */
gpio-line-names =
"[MINI1CLK_EN]", "NC", "", "", "", "", "", "";
};
&gpio18 {
/* GPIO_144-GPIO_151 */
gpio-line-names =
"[SPI1_SCLK]", /* HSEC pin 9: GPIO_144_SPI3_CLK */
"[SPI1_DIN]", /* HSEC pin 11: GPIO_145_SPI3_DI */
"[SPI1_DOUT]", /* HSEC pin 1: GPIO_146_SPI3_DO */
"[SPI1_CS]", /* HSEC pin 7: GPIO_147_SPI3_CS0_N */
"[POWER_INT_N]",
"[CDMA_GPS_SYNC]",
"GPIO_150_PEX_INTA",
"GPIO_151_CAN_INT";
};
&gpio19 {
/* GPIO_152-GPIO_159 */
gpio-line-names = "", "", "", "", "", "", "", "";
};
&gpio20 {
/* GPIO_160-GPIO_167 */
gpio-line-names =
"[SD_CLK]",
"[SD_CMD]",
"[SD_DATA0]",
"[SD_DATA1]",
"[SD_DATA2]",
"[SD_DATA3]",
"GPIO_166_ETHCLK_EN",
"GPIO_167_USER_LED2";
};
&gpio21 {
/* GPIO_168-GPIO_175 */
gpio-line-names =
"GPIO_168_GPS_EN",
"GPIO-C", /* LSEC pin 25: GPIO_169_USIM1_CLK */
"GPIO-E", /* LSEC pin 27: GPIO_170_USIM1_RST */
"GPIO-B", /* LSEC pin 24: GPIO_171_USIM1_DATA */
"", "", "", "", "";
};
&gpio22 {
/* GPIO_176-GPIO_183 */
gpio-line-names =
"[PMU_PWR_HOLD]",
"GPIO_177_WL_WAKEUP_AP",
"[JTAG_TCK]",
"[JTAG_TMS]",
"[JTAG_TDI]",
"[JTAG_TMS]",
"GPIO_182_FATAL_ERR",
"NC";
};
&gpio23 {
/* GPIO_184-GPIO_191 */
gpio-line-names =
"GPIO_184_JTAG_SEL",
"GPIO-F", /* LSEC pin 28: GPIO_185_LCD_BL_PWM */
"[I2C0_SCL]", /* LSEC pin 15: GPIO_186_I2C0_SCL */
"[I2C0_SDA]", /* LSEC pin 17: GPIO_187_I2C0_SDA */
"[GPIO_188_I2C1_SCL]", /* Actual SoC I2C1_SCL */
"[GPIO_189_I2C1_SDA]", /* Actual SoC I2C1_SDA */
"[I2C1_SCL]", /* LSEC pin 19: GPIO_190_I2C2_SCL */
"[I2C2_SDA]"; /* LSEC pin 21: GPIO_191_I2C2_SDA */
};
&gpio24 {
/* GPIO_192-GPIO_199 */
gpio-line-names =
"[SD_LED]",
"NC",
"[PCM_DI]", /* LSEC pin 22: GPIO_194_I2S0_DI */
"[PCM_DO]", /* LSEC pin 20: GPIO_195_I2S0_DO */
"[PCM_CLK]", /* LSEC pin 18: GPIO_196_I2S0_XCLK */
"[PCM_FS]", /* LSEC pin 16: GPIO_197_I2S0_XFS */
"",
"[I2S2_DO]";
};
&gpio25 {
/* GPIO_200-GPIO_207 */
gpio-line-names =
"[I2S2_XCLK]",
"[I2S2_XFS]",
"GPIO_202_PERST_ETH",
"GPIO_203_PWRON_DET",
"GPIO_204_PMU1_IRQ_N",
"GPIO_205_SD_DET",
"GPIO_206_GPS_MOTION_INT",
"GPIO_207_HDMI_SEL";
};
&gpio26 {
/* GPIO_208-GPIO_215 */
gpio-line-names =
"GPIO-A", /* LSEC pin 23: GPIO_208_WAKEUP_SOC */
"GPIO_209_VBUS_TYPEC",
"NC",
"NC",
"NC",
"[SPI0_SCLK]", /* LSEC pin 8: GPIO_213_SPI2_CLK */
"[SPI0_DIN]", /* LSEC pin 10: GPIO_214_SPI2_DI */
"[SPI0_DOUT]"; /* LSEC pin 14: GPIO_215_SPI2_DO */
};
&gpio27 {
/* GPIO_216-GPIO_223 */
gpio-line-names =
"[SPI0_CS]", /* LSEC pin 12: GPIO_216_SPI2_CS0_N */
"GPIO_217_HDMI_PD",
"GPIO_218_GPS_WAKEUP_AP",
"GPIO_219_M.2CLK_EN",
"GPIO_220_PERST_MINI",
"GPIO_221_CC_INT",
"[PCIE_CLKREQ_L]",
"NC";
};
&gpio28 {
/* GPIO_224-GPIO_231 */
gpio-line-names =
"[PMU0_INT]",
"[SPMI_DATA]",
"[SPMI_CLK]",
"[CAN_SPI_CLK]",
"[CAN_SPI_DI]",
"[CAN_SPI_DO]",
"[CAN_SPI_CS]",
"GPIO_231_HDMI_INT";
};
&uart0 {
/* On High speed expansion header */
label = "HS-UART0";
status = "okay";
};
&uart2 {
/* On Low speed expansion header */
label = "LS-UART0";
status = "okay";
};
&uart6 {
/* On Low speed expansion header */
label = "LS-UART1";
status = "okay";
};

499
arch/arm64/boot/dts/hisilicon/hi3670.dtsi
View File

@ -7,6 +7,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi3670-clock.h>
/ {
compatible = "hisilicon,hi3670";
@ -144,19 +145,507 @@ soc {
#size-cells = <2>;
ranges;
uart6_clk: clk_19_2M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
crg_ctrl: crg_ctrl@fff35000 {
compatible = "hisilicon,hi3670-crgctrl", "syscon";
reg = <0x0 0xfff35000 0x0 0x1000>;
#clock-cells = <1>;
};
pctrl: pctrl@e8a09000 {
compatible = "hisilicon,hi3670-pctrl", "syscon";
reg = <0x0 0xe8a09000 0x0 0x1000>;
#clock-cells = <1>;
};
pmuctrl: crg_ctrl@fff34000 {
compatible = "hisilicon,hi3670-pmuctrl", "syscon";
reg = <0x0 0xfff34000 0x0 0x1000>;
#clock-cells = <1>;
};
sctrl: sctrl@fff0a000 {
compatible = "hisilicon,hi3670-sctrl", "syscon";
reg = <0x0 0xfff0a000 0x0 0x1000>;
#clock-cells = <1>;
};
iomcu: iomcu@ffd7e000 {
compatible = "hisilicon,hi3670-iomcu", "syscon";
reg = <0x0 0xffd7e000 0x0 0x1000>;
#clock-cells = <1>;
};
media1_crg: media1_crgctrl@e87ff000 {
compatible = "hisilicon,hi3670-media1-crg", "syscon";
reg = <0x0 0xe87ff000 0x0 0x1000>;
#clock-cells = <1>;
};
media2_crg: media2_crgctrl@e8900000 {
compatible = "hisilicon,hi3670-media2-crg","syscon";
reg = <0x0 0xe8900000 0x0 0x1000>;
#clock-cells = <1>;
};
uart0: serial@fdf02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf02000 0x0 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
<&crg_ctrl HI3670_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
status = "disabled";
};
uart1: serial@fdf00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf00000 0x0 0x1000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>,
<&crg_ctrl HI3670_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
status = "disabled";
};
uart2: serial@fdf03000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf03000 0x0 0x1000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>,
<&crg_ctrl HI3670_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
status = "disabled";
};
uart3: serial@ffd74000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xffd74000 0x0 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>,
<&crg_ctrl HI3670_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
status = "disabled";
};
uart4: serial@fdf01000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf01000 0x0 0x1000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>,
<&crg_ctrl HI3670_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
status = "disabled";
};
uart5: serial@fdf05000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf05000 0x0 0x1000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>,
<&crg_ctrl HI3670_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
status = "disabled";
};
uart6: serial@fff32000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfff32000 0x0 0x1000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart6_clk &uart6_clk>;
clocks = <&crg_ctrl HI3670_CLK_UART6>,
<&crg_ctrl HI3670_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
status = "disabled";
};
gpio0: gpio@e8a0b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a0b000 0x0 0x1000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO0>;
clock-names = "apb_pclk";
};
gpio1: gpio@e8a0c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a0c000 0x0 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO1>;
clock-names = "apb_pclk";
};
gpio2: gpio@e8a0d000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a0d000 0x0 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 1 6 7>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO2>;
clock-names = "apb_pclk";
};
gpio3: gpio@e8a0e000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a0e000 0x0 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO3>;
clock-names = "apb_pclk";
};
gpio4: gpio@e8a0f000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a0f000 0x0 0x1000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 18 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO4>;
clock-names = "apb_pclk";
};
gpio5: gpio@e8a10000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a10000 0x0 0x1000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 26 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO5>;
clock-names = "apb_pclk";
};
gpio6: gpio@e8a11000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a11000 0x0 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 1 34 7>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO6>;
clock-names = "apb_pclk";
};
gpio7: gpio@e8a12000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a12000 0x0 0x1000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 41 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO7>;
clock-names = "apb_pclk";
};
gpio8: gpio@e8a13000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a13000 0x0 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 49 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO8>;
clock-names = "apb_pclk";
};
gpio9: gpio@e8a14000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a14000 0x0 0x1000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 57 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO9>;
clock-names = "apb_pclk";
};
gpio10: gpio@e8a15000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a15000 0x0 0x1000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 65 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO10>;
clock-names = "apb_pclk";
};
gpio11: gpio@e8a16000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a16000 0x0 0x1000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 73 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO11>;
clock-names = "apb_pclk";
};
gpio12: gpio@e8a17000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a17000 0x0 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 81 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO12>;
clock-names = "apb_pclk";
};
gpio13: gpio@e8a18000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a18000 0x0 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO13>;
clock-names = "apb_pclk";
};
gpio14: gpio@e8a19000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a19000 0x0 0x1000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO14>;
clock-names = "apb_pclk";
};
gpio15: gpio@e8a1a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a1a000 0x0 0x1000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO15>;
clock-names = "apb_pclk";
};
gpio16: gpio@e8a1b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a1b000 0x0 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx5 0 0 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO16>;
clock-names = "apb_pclk";
};
gpio17: gpio@e8a1c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a1c000 0x0 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx5 0 8 2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO17>;
clock-names = "apb_pclk";
};
gpio18: gpio@fff28000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xfff28000 0x0 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx1 4 42 4>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3670_PCLK_GPIO18>;
clock-names = "apb_pclk";
};
gpio19: gpio@fff29000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xfff29000 0x0 0x1000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx1 0 61 2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3670_PCLK_GPIO19>;
clock-names = "apb_pclk";
};
gpio20: gpio@e8a1f000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a1f000 0x0 0x1000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx7 0 0 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO20>;
clock-names = "apb_pclk";
};
gpio21: gpio@e8a20000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xe8a20000 0x0 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx7 0 8 4>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO21>;
clock-names = "apb_pclk";
};
gpio22: gpio@fff0b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xfff0b000 0x0 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO176 */
gpio-ranges = <&pmx1 2 0 6>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3670_PCLK_AO_GPIO0>;
clock-names = "apb_pclk";
};
gpio23: gpio@fff0c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xfff0c000 0x0 0x1000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO184 */
gpio-ranges = <&pmx1 0 6 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3670_PCLK_AO_GPIO1>;
clock-names = "apb_pclk";
};
gpio24: gpio@fff0d000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xfff0d000 0x0 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO192 */
gpio-ranges = <&pmx1 0 14 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3670_PCLK_AO_GPIO2>;
clock-names = "apb_pclk";
};
gpio25: gpio@fff0e000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xfff0e000 0x0 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO200 */
gpio-ranges = <&pmx1 0 22 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3670_PCLK_AO_GPIO3>;
clock-names = "apb_pclk";
};
gpio26: gpio@fff0f000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xfff0f000 0x0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO208 */
gpio-ranges = <&pmx1 0 30 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3670_PCLK_AO_GPIO4>;
clock-names = "apb_pclk";
};
gpio27: gpio@fff10000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xfff10000 0x0 0x1000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
/* GPIO216 */
gpio-ranges = <&pmx1 4 31 4>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3670_PCLK_AO_GPIO5>;
clock-names = "apb_pclk";
};
gpio28: gpio@fff1d000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xfff1d000 0x0 0x1000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx1 1 35 7>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&sctrl HI3670_PCLK_AO_GPIO6>;
clock-names = "apb_pclk";
};
};
};

13
arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
View File

@ -35,30 +35,31 @@ leds {
compatible = "gpio-leds";
user-led0 {
label = "USER-LED0";
label = "green:user1";
gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
user-led1 {
label = "USER-LED1";
label = "green:user2";
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
linux,default-trigger = "mmc0";
default-state = "off";
};
user-led2 {
label = "USER-LED2";
label = "green:user3";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
linux,default-trigger = "mmc1";
default-state = "off";
};
user-led3 {
label = "USER-LED3";
label = "green:user4";
gpios = <&gpio10 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "cpu0";
linux,default-trigger = "none";
panic-indicator;
default-state = "off";
};
};

25
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
View File

@ -340,42 +340,43 @@ wlcore: wlcore@2 {
leds {
compatible = "gpio-leds";
user_led4 {
label = "user_led4";
user_led1 {
label = "green:user1";
gpios = <&gpio4 0 0>; /* <&gpio_user_led_1>; */
linux,default-trigger = "heartbeat";
};
user_led3 {
label = "user_led3";
user_led2 {
label = "green:user2";
gpios = <&gpio4 1 0>; /* <&gpio_user_led_2>; */
linux,default-trigger = "mmc0";
};
user_led2 {
label = "user_led2";
user_led3 {
label = "green:user3";
gpios = <&gpio4 2 0>; /* <&gpio_user_led_3>; */
linux,default-trigger = "mmc1";
};
user_led1 {
label = "user_led1";
user_led4 {
label = "green:user4";
gpios = <&gpio4 3 0>; /* <&gpio_user_led_4>; */
panic-indicator;
linux,default-trigger = "cpu0";
linux,default-trigger = "none";
};
wlan_active_led {
label = "wifi_active";
label = "yellow:wlan";
gpios = <&gpio3 5 0>; /* <&gpio_wlan_active_led>; */
linux,default-trigger = "phy0tx";
default-state = "off";
};
bt_active_led {
label = "bt_active";
label = "blue:bt";
gpios = <&gpio4 7 0>; /* <&gpio_bt_active_led>; */
linux,default-trigger = "hci0rx";
linux,default-trigger = "hci0-power";
default-state = "off";
};
};

9
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View File

@ -893,7 +893,14 @@ target: trip-point@1 {
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

244
arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi Normal file
View File

@ -0,0 +1,244 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Pinctrl dts file for HiSilicon HiKey970 development board
*/
#include <dt-bindings/pinctrl/hisi.h>
/ {
soc {
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
pmx0: pinmux@e896c000 {
compatible = "pinctrl-single";
reg = <0x0 0xe896c000 0x0 0x72c>;
#pinctrl-cells = <1>;
#gpio-range-cells = <0x3>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 82 0>;
uart0_pmx_func: uart0_pmx_func {
pinctrl-single,pins = <
0x054 MUX_M2 /* UART0_RXD */
0x058 MUX_M2 /* UART0_TXD */
>;
};
uart2_pmx_func: uart2_pmx_func {
pinctrl-single,pins = <
0x700 MUX_M2 /* UART2_CTS_N */
0x704 MUX_M2 /* UART2_RTS_N */
0x708 MUX_M2 /* UART2_RXD */
0x70c MUX_M2 /* UART2_TXD */
>;
};
uart3_pmx_func: uart3_pmx_func {
pinctrl-single,pins = <
0x064 MUX_M1 /* UART3_CTS_N */
0x068 MUX_M1 /* UART3_RTS_N */
0x06c MUX_M1 /* UART3_RXD */
0x070 MUX_M1 /* UART3_TXD */
>;
};
uart4_pmx_func: uart4_pmx_func {
pinctrl-single,pins = <
0x074 MUX_M1 /* UART4_CTS_N */
0x078 MUX_M1 /* UART4_RTS_N */
0x07c MUX_M1 /* UART4_RXD */
0x080 MUX_M1 /* UART4_TXD */
>;
};
uart6_pmx_func: uart6_pmx_func {
pinctrl-single,pins = <
0x05c MUX_M1 /* UART6_RXD */
0x060 MUX_M1 /* UART6_TXD */
>;
};
};
pmx2: pinmux@e896c800 {
compatible = "pinconf-single";
reg = <0x0 0xe896c800 0x0 0x72c>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
uart0_cfg_func: uart0_cfg_func {
pinctrl-single,pins = <
0x058 0x0 /* UART0_RXD */
0x05c 0x0 /* UART0_TXD */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
uart2_cfg_func: uart2_cfg_func {
pinctrl-single,pins = <
0x700 0x0 /* UART2_CTS_N */
0x704 0x0 /* UART2_RTS_N */
0x708 0x0 /* UART2_RXD */
0x70c 0x0 /* UART2_TXD */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
uart3_cfg_func: uart3_cfg_func {
pinctrl-single,pins = <
0x068 0x0 /* UART3_CTS_N */
0x06c 0x0 /* UART3_RTS_N */
0x070 0x0 /* UART3_RXD */
0x074 0x0 /* UART3_TXD */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
uart4_cfg_func: uart4_cfg_func {
pinctrl-single,pins = <
0x078 0x0 /* UART4_CTS_N */
0x07c 0x0 /* UART4_RTS_N */
0x080 0x0 /* UART4_RXD */
0x084 0x0 /* UART4_TXD */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
uart6_cfg_func: uart6_cfg_func {
pinctrl-single,pins = <
0x060 0x0 /* UART6_RXD */
0x064 0x0 /* UART6_TXD */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
};
pmx5: pinmux@fc182000 {
compatible = "pinctrl-single";
reg = <0x0 0xfc182000 0x0 0x028>;
#gpio-range-cells = <3>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 10 0>;
};
pmx6: pinmux@fc182800 {
compatible = "pinconf-single";
reg = <0x0 0xfc182800 0x0 0x028>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
};
pmx7: pinmux@ff37e000 {
compatible = "pinctrl-single";
reg = <0x0 0xff37e000 0x0 0x030>;
#gpio-range-cells = <3>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 12 0>;
};
pmx8: pinmux@ff37e800 {
compatible = "pinconf-single";
reg = <0x0 0xff37e800 0x0 0x030>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
};
pmx1: pinmux@fff11000 {
compatible = "pinctrl-single";
reg = <0x0 0xfff11000 0x0 0x73c>;
#gpio-range-cells = <0x3>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 46 0>;
};
pmx16: pinmux@fff11800 {
compatible = "pinconf-single";
reg = <0x0 0xfff11800 0x0 0x73c>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
};
};
};