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Versatile Express DTS update for DRM:

Browse Source 
This updates the Versatile Express family DTS files to
 contain the correct and detailed information required
 for the PL11x DRM driver to work properly.
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Merge tag 'vexpress-drm-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/dt

Versatile Express DTS update for DRM:
This updates the Versatile Express family DTS files to
contain the correct and detailed information required
for the PL11x DRM driver to work properly.

* tag 'vexpress-drm-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
  ARM: dts: Modernize the Vexpress PL111 integration

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-11-30 15:16:42 -08:00
commit 9cf0418ee0
9 changed files with 150 additions and 121 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
View File

@ -43,11 +43,6 @@ psram@1,00000000 {
bank-width = <4>;
};
v2m_video_ram: vram@2,00000000 {
compatible = "arm,vexpress-vram";
reg = <2 0x00000000 0x00800000>;
};
ethernet@2,02000000 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <2 0x02000000 0x10000>;
@ -223,13 +218,24 @@ v2m_timer23: timer@120000 {
v2m_i2c_dvi: i2c@160000 {
compatible = "arm,versatile-i2c";
reg = <0x160000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
dvi-transmitter@39 {
compatible = "sil,sii9022-tpi", "sil,sii9022";
reg = <0x39>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dvi_bridge_in: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
};
};
dvi-transmitter@60 {
@ -260,37 +266,16 @@ clcd@1f0000 {
interrupts = <14>;
clocks = <&v2m_oscclk1>, <&smbclk>;
clock-names = "clcdclk", "apb_pclk";
memory-region = <&v2m_video_ram>;
max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
/* 800x600 16bpp @36MHz works fine */
max-memory-bandwidth = <54000000>;
memory-region = <&vram>;
port {
v2m_clcd_pads: endpoint {
remote-endpoint = <&v2m_clcd_panel>;
clcd_pads: endpoint {
remote-endpoint = <&dvi_bridge_in>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
panel {
compatible = "panel-dpi";
port {
v2m_clcd_panel: endpoint {
remote-endpoint = <&v2m_clcd_pads>;
};
};
panel-timing {
clock-frequency = <25175000>;
hactive = <640>;
hback-porch = <40>;
hfront-porch = <24>;
hsync-len = <96>;
vactive = <480>;
vback-porch = <32>;
vfront-porch = <11>;
vsync-len = <2>;
};
};
};
};

63
arch/arm/boot/dts/vexpress-v2m.dtsi
View File

@ -43,11 +43,6 @@ psram@2,00000000 {
bank-width = <4>;
};
v2m_video_ram: vram@3,00000000 {
compatible = "arm,vexpress-vram";
reg = <3 0x00000000 0x00800000>;
};
ethernet@3,02000000 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <3 0x02000000 0x10000>;
@ -223,13 +218,37 @@ v2m_timer23: timer@12000 {
v2m_i2c_dvi: i2c@16000 {
compatible = "arm,versatile-i2c";
reg = <0x16000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
dvi-transmitter@39 {
compatible = "sil,sii9022-tpi", "sil,sii9022";
reg = <0x39>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/*
* Both the core tile and the motherboard routes their output
* pads to this transmitter. The motherboard system controller
* can select one of them as input using a mux register in
* "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
* the only platform with this specific set-up.
*/
port@0 {
reg = <0>;
dvi_bridge_in_ct: endpoint {
remote-endpoint = <&clcd_pads_ct>;
};
};
port@1 {
reg = <1>;
dvi_bridge_in_mb: endpoint {
remote-endpoint = <&clcd_pads_mb>;
};
};
};
};
dvi-transmitter@60 {
@ -253,6 +272,7 @@ compact-flash@1a000 {
reg-shift = <2>;
};
clcd@1f000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x1f000 0x1000>;
@ -260,37 +280,16 @@ clcd@1f000 {
interrupts = <14>;
clocks = <&v2m_oscclk1>, <&smbclk>;
clock-names = "clcdclk", "apb_pclk";
memory-region = <&v2m_video_ram>;
max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
/* 800x600 16bpp @36MHz works fine */
max-memory-bandwidth = <54000000>;
memory-region = <&vram>;
port {
v2m_clcd_pads: endpoint {
remote-endpoint = <&v2m_clcd_panel>;
clcd_pads_mb: endpoint {
remote-endpoint = <&dvi_bridge_in_mb>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
panel {
compatible = "panel-dpi";
port {
v2m_clcd_panel: endpoint {
remote-endpoint = <&v2m_clcd_pads>;
};
};
panel-timing {
clock-frequency = <25175000>;
hactive = <640>;
hback-porch = <40>;
hfront-porch = <24>;
hsync-len = <96>;
vactive = <480>;
vback-porch = <32>;
vfront-porch = <11>;
vsync-len = <2>;
};
};
};
};

14
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
View File

@ -53,6 +53,20 @@ memory@80000000 {
reg = <0 0x80000000 0 0x40000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* Chipselect 2 is physically at 0x18000000 */
vram: vram@18000000 {
/* 8 MB of designated video RAM */
compatible = "shared-dma-pool";
reg = <0 0x18000000 0 0x00800000>;
no-map;
};
};
hdlcd@2b000000 {
compatible = "arm,hdlcd";
reg = <0 0x2b000000 0 0x1000>;

14
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
View File

@ -104,6 +104,20 @@ memory@80000000 {
reg = <0 0x80000000 0 0x40000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* Chipselect 2 is physically at 0x18000000 */
vram: vram@18000000 {
/* 8 MB of designated video RAM */
compatible = "shared-dma-pool";
reg = <0 0x18000000 0 0x00800000>;
no-map;
};
};
wdt@2a490000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0 0x2a490000 0 0x1000>;

14
arch/arm/boot/dts/vexpress-v2p-ca5s.dts
View File

@ -55,6 +55,20 @@ memory@80000000 {
reg = <0x80000000 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* Chipselect 2 is physically at 0x18000000 */
vram: vram@18000000 {
/* 8 MB of designated video RAM */
compatible = "shared-dma-pool";
reg = <0x18000000 0x00800000>;
no-map;
};
};
hdlcd@2a110000 {
compatible = "arm,hdlcd";
reg = <0x2a110000 0x1000>;

43
arch/arm/boot/dts/vexpress-v2p-ca9.dts
View File

@ -69,6 +69,20 @@ memory@60000000 {
reg = <0x60000000 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* Chipselect 3 is physically at 0x4c000000 */
vram: vram@4c000000 {
/* 8 MB of designated video RAM */
compatible = "shared-dma-pool";
reg = <0x4c000000 0x00800000>;
no-map;
};
};
clcd@10020000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x10020000 0x1000>;
@ -76,36 +90,15 @@ clcd@10020000 {
interrupts = <0 44 4>;
clocks = <&oscclk1>, <&oscclk2>;
clock-names = "clcdclk", "apb_pclk";
max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
/* 1024x768 16bpp @65MHz */
max-memory-bandwidth = <95000000>;
port {
clcd_pads: endpoint {
remote-endpoint = <&clcd_panel>;
clcd_pads_ct: endpoint {
remote-endpoint = <&dvi_bridge_in_ct>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
panel {
compatible = "panel-dpi";
port {
clcd_panel: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
panel-timing {
clock-frequency = <63500127>;
hactive = <1024>;
hback-porch = <152>;
hfront-porch = <48>;
hsync-len = <104>;
vactive = <768>;
vback-porch = <23>;
vfront-porch = <3>;
vsync-len = <4>;
};
};
};
memory-controller@100e0000 {

23
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
View File

@ -78,6 +78,20 @@ memory@80000000 {
<0x00000008 0x80000000 0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* Chipselect 2,00000000 is physically at 0x18000000 */
vram: vram@18000000 {
/* 8 MB of designated video RAM */
compatible = "shared-dma-pool";
reg = <0x00000000 0x18000000 0 0x00800000>;
no-map;
};
};
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
@ -107,6 +121,15 @@ pmu {
<0 63 4>;
};
panel {
compatible = "arm,rtsm-display";
port {
panel_in: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
};
smb@8000000 {
compatible = "simple-bus";

37
arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
View File

@ -24,11 +24,6 @@ flash@0,00000000 {
bank-width = <4>;
};
v2m_video_ram: vram@2,00000000 {
compatible = "arm,vexpress-vram";
reg = <2 0x00000000 0x00800000>;
};
ethernet@2,02000000 {
compatible = "smsc,lan91c111";
reg = <2 0x02000000 0x10000>;
@ -187,38 +182,16 @@ clcd@1f0000 {
interrupts = <14>;
clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
clock-names = "clcdclk", "apb_pclk";
arm,pl11x,framebuffer = <0x18000000 0x00180000>;
memory-region = <&v2m_video_ram>;
max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
/* 800x600 16bpp @36MHz works fine */
max-memory-bandwidth = <54000000>;
memory-region = <&vram>;
port {
v2m_clcd_pads: endpoint {
remote-endpoint = <&v2m_clcd_panel>;
clcd_pads: endpoint {
remote-endpoint = <&panel_in>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
panel {
compatible = "panel-dpi";
port {
v2m_clcd_panel: endpoint {
remote-endpoint = <&v2m_clcd_pads>;
};
};
panel-timing {
clock-frequency = <63500127>;
hactive = <1024>;
hback-porch = <152>;
hfront-porch = <48>;
hsync-len = <104>;
vactive = <768>;
vback-porch = <23>;
vfront-porch = <3>;
vsync-len = <4>;
};
};
};
virtio-block@130000 {

14
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
View File

@ -65,6 +65,20 @@ memory@80000000 {
reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* Chipselect 2 is physically at 0x18000000 */
vram: vram@18000000 {
/* 8 MB of designated video RAM */
compatible = "shared-dma-pool";
reg = <0 0x18000000 0 0x00800000>;
no-map;
};
};
gic: interrupt-controller@2c001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;