Commit Graph

840610 Commits

Author SHA1 Message Date
Alex Deucher
72a14e9b23 Revert "drm/amdgpu: add DRIVER_SYNCOBJ_TIMELINE to amdgpu"
This reverts commit 8d8a5a64a8.

Wait until KHR exposes the VLK support.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-05 22:18:09 -05:00
Christian König
ae96e8d7b6 drm/ttm: fix ttm_bo_unreserve
Since we now keep BOs on the LRU we need to explicitely remove
them from the LRU now after they are pinned.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-05 22:18:09 -05:00
Alex Deucher
621b325aa8 drm/amdgpu/display: Drop some new CONFIG_DRM_AMD_DC_DCN1_01 guards
These got added back by subsequent merges accidently.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-05 22:18:09 -05:00
Alex Deucher
beff74bc6e drm/amdgpu: fix a race in GPU reset with IB test (v2)
Split late_init into two functions, one (do_late_init) which
just does the hw init, and late_init which calls do_late_init
and schedules the IB test work.  Call do_late_init in
the GPU reset code to run the init code, but not schedule
the IB test code.  The IB test code is called directly
in the gpu reset code so no need to run the IB tests
in a separate work thread.  If we do, we end up racing.

v2: Rework late_init.  Pull out the mgpu fan boost and xgmi
pstate code into late_init so they get called in all cases.
rename the late_init worker thread to delayed work since it's
just the IB tests now which can happen later.  Schedule the
work at init and resume time.  It's not needed at reset time
because the IB tests are called directly.

Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: Xinhui Pan <xinhui.pan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-05 22:18:09 -05:00
xinhui pan
c53e4db712 drm/amdgpu: cancel late_init_work before gpu reset
gpu reset will run late_init and schedule the late_init_work.  if we
keep triggering gpu reset in a short time, there are potenial races.

Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-05 22:18:09 -05:00
Mauro Carvalho Chehab
fbebaa7299 gpu: amdgpu: fix broken amdgpu_dma_buf.c references
This file was renamed, but docs weren't updated accordingly.

	WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function PRIME Buffer Sharing ./drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c' failed with return code 1
	WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal ./drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c' failed with return code 2

Fixes: 2fbd6f94ac ("drm/amdgpu: rename amdgpu_prime.[ch] into amdgpu_dma_buf.[ch]")
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-05 22:17:32 -05:00
Chunming Zhou
0f257b0953 drm/amd/display: use ttm_eu_reserve_buffers instead of amdgpu_bo_reserve v2
add ticket for display bo, so that it can preempt busy bo.

v2: fix stupid rebase error

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:35 -05:00
Christian König
d367bd2a5e drm/ttm: fix busy memory to fail other user v10
BOs on the LRU might be blocked during command submission
and cause OOM situations.

Avoid this by blocking for the first busy BO not locked by
the same ticket as the BO we are searching space for.

v10: completely start over with the patch since we didn't
     handled a whole bunch of corner cases.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:34 -05:00
Christian König
224ee02a9d drm/ttm: immediately move BOs to the new LRU v3
Move BOs which are currently in a lower domain to the new
LRU before allocating backing space while validating.

This makes sure that we always have enough entries on the
LRU to allow for other processes to wait for an operation
to complete.

v2: generalize the test
v3: fix rebase error

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:34 -05:00
Christian König
4c5ac9487c drm/ttm: cleanup ttm_bo_mem_space
We tried this once before, but that turned out to be more
complicated than thought. With all the right prerequisites
it looks like we can do this now.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:34 -05:00
Christian König
af1dac01a7 drm/ttm: remove manual placement preference
If drivers don't prefer a system memory placement
they should not but it into the placement list first.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:34 -05:00
Christian König
b2f7a61619 drm/ttm: return immediately in case of a signal
When a signal arrives we should return immediately for
handling it and not try other placements first.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:34 -05:00
Christian König
6e58ab7ac7 drm/ttm: Make LRU removal optional v2
We are already doing this for DMA-buf imports and also for
amdgpu VM BOs for quite a while now.

If this doesn't run into any problems we are probably going
to stop removing BOs from the LRU altogether.

v2: drop BUG_ON from ttm_bo_add_to_lru

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:34 -05:00
Emily Deng
526c654a8a drm/amdgpu/display: Fix reload driver error
Issue:
Will have follow error when reload driver:
[ 3986.567739] sysfs: cannot create duplicate filename '/devices/pci0000:00/0000:00:07.0/drm_dp_aux_dev'
[ 3986.567743] CPU: 6 PID: 1767 Comm: modprobe Tainted: G           OE     5.0.0-rc1-custom #1
[ 3986.567745] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014
[ 3986.567746] Call Trace:
......
[ 3986.567808]  drm_dp_aux_register_devnode+0xdc/0x140 [drm_kms_helper]
......
[ 3986.569081] kobject_add_internal failed for drm_dp_aux_dev with -EEXIST, don't try to register things with the same name in the same directory.

Reproduce sequences:
1.modprobe amdgpu
2.modprobe -r amdgpu
3.modprobe amdgpu

Root cause:
When unload driver, it doesn't unregister aux.

v2: Don't use has_aux

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:33 -05:00
Emily Deng
bdb50274d0 drm/amdgpu/sriov: Correct some register program method
For the VF, some registers only could be programmed with RLC.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Trigger Huang <Trigger.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:33 -05:00
Oak Zeng
443e902eee drm/amdkfd: Return proper error code for gws alloc API
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:33 -05:00
Aric Cyr
4fd3341223 drm/amd/display: program manual trigger only for bottom most pipe
[Why]
We only want to manual trigger end-of-frame when the bottom-most
pipe is flipped to prevent overlays from ending the frame too early.

[How]
Check that the manual trigger is only firing on bottom plane.

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:33 -05:00
Krunoslav Kovac
6ad34adeae drm/amd/display: CS_TFM_1D only applied post EOTF
[Why]
There's some unnecessary mem allocation for CS_TFM_ID. What's worse, it
depends on LUT size and since it's 4K for CS_TFM_1D, it is 16x bigger
than in regular case when it's actually needed. This leads to some
crashes in stress conditions.

[How]
Skip ramp combining designed for RGB256 and DXGI gamma with CS_TFM_1D.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:33 -05:00
Nicholas Kazlauskas
7316c4ad29 drm/amd/display: Reset planes for color management changes
[Why]
For commits with allow_modeset=false and CRTC degamma changes the planes
aren't reset. This results in incorrect rendering.

[How]
Reset the planes when color management has changed on the CRTC.
Technically this will include regamma changes as well, but it doesn't
really after legacy userspace since those commit with
allow_modeset=true.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:33 -05:00
Eryk Brol
e25228b02e drm/amd/display: Increase Backlight Gain Step Size
[Why]
Some backlight tests fail due to backlight settling
taking too long. This happens because the step
size used to change backlight levels is too small.

[How]
1. Change the size of the backlight gain step size
2. Change how DMCU firmware gets the step size value
   so that it is passed in by driver during DMCU initn

Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:33 -05:00
Anthony Koo
8633d96d3c drm/amd/display: fix issues with bad AUX reply on some displays
[Why]
Some displays take some time to power up AUX CH once they are
put into D3 state via write to DPCD 600h=2.

Interestingly enough, some display may simply NACK, but some might
also ACK with a bunch of 0s, which can cause issues with receiver
cap retrieval. Note that not all DPCD address return 0s, but in
particular it has been observed on some higher DPCD address such
as DPCD 2200h, etc.

[How]
Based on spec, receiver will monitor differential signal while in D3 and
AUX CH is in low power mode. When detected, it may allow up to
1 ms to power up AUX CH and reply.

If we read Sink power state D3, we should add 1 ms delay to satisfy
this spec requirement.

Signed-off-by: Anthony Koo <anthony.koo@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:32 -05:00
Eric Bernstein
c5c07cb543 drm/amd/display: Refactor DIO stream encoder
* Pull duplicate audio_clock_info struct to stream_encoder.h
* Generalize sec_gsp7* to sec_gsp_pps*
* Expose enc1 and enc2 stream encoder audio funcs

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:32 -05:00
Daniel He
ff1232a905 drm/amd/display: Modified AUX_DPHY_RX_CONTROL0
[Description] This is cause by failing to read link caps from driver.

Signed-off-by: Daniel He <daniel.he@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:32 -05:00
Ilya Bakoulin
d764409130 drm/amd/display: Add writeback_config to VBA vars
Adding writeback_config enum to vba_vars_st, replacing old flag.
Initialize to dm_normal.

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:32 -05:00
Eric Yang
baa1fd7f32 drm/amd/display: Refactor clk_mgr functions
[Why]
Some HW specific implementations can be pulled out into clk_mgr.c.

[How]
* Pull get_active_display_cnt out to clk_mgr.
* Pull out shared logic in set_dispclk and set_dprefclk

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:32 -05:00
Eric Yang
961ea20155 drm/amd/display: Fix type of pp_smu_wm_set_range struct
[why]
Value read from SMU is 16 bits, not 32.

[How]
Fix type, and add wm_type enum in preparation for future interfaces.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:32 -05:00
Anthony Koo
44ab1aa84a drm/amd/display: do not power on eDP power rail early
[Why]
Modern Standby may toggle display adapter state between D0
and D3 state unpredictably.
But events that cause transition to D0 are not always resulting
in a display light up scenario.

Modern eDP panels should be able to power on panel logic
quickly upon VDD going high. Based on spec, the T3 time
between VDD on and HPD high can be between 0 and 80 ms.

Doing any tricky sorts of optimization by powering on panel
VDD early during D0 transition on can negatively impact other
features due to unnecessary power drain and toggling when
final system state does not intend for the panel to be lit up.

We need OEMs to source higher end panels that have T3 time
close to 0 if they want quick S3/Modern Standby resume times.

[How]
Remove panel VDD power on in init_hw

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:31 -05:00
Su Sung Chung
4b0ab7dd37 drm/amd/display: fix crash on setmode when mode is close to bw limit
[why]
during It's possible to call dcn_validate_bandwidth with no plane.
In that case, as we are only intersted in if output timing is supported or not,
even if we cannot support native resolution, we still want to support lower
resolution if it is valid

[how]
if there exist no surface, make viewport/rec_out size at max 1080p. It is
already known that 1080p x 6(max # of pipes) is supported, so if we fail
validation, it is because of the stream

Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:31 -05:00
Su Sung Chung
88147df030 drm/amd/display: fix calculation of total_data_read_bandwidth
[why]
by adding fast_validate flag, we are skipping some portion of
dcn_validate_bandwidth code that is not necessary for mode validation.
However we have a bug where it does not calculate
v->total_data_read_bandwidth, which is one of the factors determines the
result of the validation, and therefore report false positive during
mode validation.

[how]
add calculation of v->total_data_read_bandwidth outside of the region
that is guarded by fast_validate flag

Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:31 -05:00
Aric Cyr
b8b205ab2b drm/amd/display: 3.2.32
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:31 -05:00
Chris Park
fe798de53a drm/amd/display: Move link functions from dc to dc_link
[Why]
link-specific functions should reside in dc_link.c

[How]
Move them there.

Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:31 -05:00
Jun Lei
8e0546d6c4 drm/amd/display: Add min_dcfclk_mhz field to bb overrides
Add min_dcfclk_mhz to bounding box overrides.

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:31 -05:00
Eric Yang
9b93eb475a drm/amd/display: move clk_mgr files to right place
[Why]
Better organization

[How]
Move clk_mgr files under dc/clk_mgr

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:31 -05:00
Paul Hsieh
70d9e8cb8b drm/amd/display: disable PSR/ABM before destroy DMCU struct
[Why]
1. DMCU is not running on some platform but driver still send ABM
   command. It may cause assert due to DMCU is not alive.
2. To make sure PSR disable when driver disable

[How]
1. Add dmcu_is_running in ABM struct, driver can check this flag to
   determine driver should send ABM command or not.
2. Send PSR disable command when destroy PSR

Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:30 -05:00
Eryk Brol
e63e2491ad drm/amd/display: Ensure DRR triggers in BP
[Why]
In the previous implementation DRR event sometimes came
in during FP2 region which is a keep-out zone. This
would cause the frame not to latch until the next frame
which resulted in heavy flicker. To fix this we need
to make sure that it triggers in the BP.

[How]
1. Remove DRR programming during flip
2. Setup manual trigger for DRR event and trigger it
after surface programming is complete

Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:30 -05:00
Krunoslav Kovac
313a9a21ff drm/amd/display: Add GSL source select registers
GSL is a form of locking that can be used to synchronize pipes in a
pipe-split configurations when async flip is used. Add the registers
here.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:30 -05:00
Eryk Brol
0a32df9cfd drm/amd/display: Disable audio stream only if it's currently enabled
[Why]
Previously there were 2 consecutive calls being made to disable
audio stream. The first one disabled the audio stream, and the second
one went through and also tried to disable the audio stream causing
BACO entry issues due to the ASIC appearing busy.

[How]
1. Add a status field to the audio struct which stores enabled/disabled
info
2. In the calls to enable/disable audio stream check if we're already
in the desired state before executing the function

Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:30 -05:00
Wenjing Liu
b1432fcbdb drm/amd/display: assign new stream id in dc_copy_stream
[why]
stream id should uniquely identify an instance of stream.
the copy constructor should be treated as a new
stream instance.

[how]
assign a new stream id in this copy constructor.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:30 -05:00
Eric Yang
a7f90cbc0e drm/amd/display: Move CLK_BASE_INNER macro
This macro is specificly used by RV1. Move it to the appropriate
location.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:30 -05:00
Gary Kattan
48ea75f99a drm/amd/display: Implement CM dealpha and bias interfaces
Add vtable entries for de-alpha and bias color management interfaces.
Move piece-wise transfer function registers to a helper list for future
reuse.

Signed-off-by: Gary Kattan <gary.kattan@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:29 -05:00
Hugo Hu
821c65596b drm/amd/display: Don't use ROM for output TF if GAMMA_CS_TFM_1D
We can’t use hardcoded SRGB ROM for output TF if we have GAMMA_CS_TFM_1D
(unless we know 1D LUT is identity), so we never want to return here early.
We apply the LUT part of ColorTransform3x4 only in apply_lut_1d() which is
called near the end of that function.

Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:29 -05:00
Eric Yang
dc88b4a684 drm/amd/display: make clk mgr soc specific
[Why]
First step of refactoring clk mgr to better handle different
ways of handling clock operations. Clock operation policies are
soc specific and not just DCN vesion specific. It is not a hw resource,
should not be in the resource pool.

[How]
Change clock manager creation to be based on HW internal ID, rename
clock manager members to be more clear. Move clock manager out of
resource.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:29 -05:00
Emily Deng
789142eb8b drm/amdgpu:Fix the unpin warning about csb buffer
As it will destroy clear_state_obj, and also will unpin it in the
gfx_v9_0_sw_fini, so don't need to
call amdgpu_bo_free_kernel in gfx_v9_0_sw_fini, or it will have unpin warning.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:29 -05:00
xinhui pan
efb426d581 drm/amdgpu: ras injection use gpu address
injection need a valid gpu address.

Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31 10:39:29 -05:00
Dave Airlie
91c1ead6ae Merge branch 'drm-next-5.3' of git://people.freedesktop.org/~agd5f/linux into drm-next
New stuff for 5.3:
- Add new thermal sensors for vega asics
- Various RAS fixes
- Add sysfs interface for memory interface utilization
- Use HMM rather than mmu notifier for user pages
- Expose xgmi topology via kfd
- SR-IOV fixes
- Fixes for manual driver reload
- Add unique identifier for vega asics
- Clean up user fence handling with UVD/VCE/VCN blocks
- Convert DC to use core bpc attribute rather than a custom one
- Add GWS support for KFD
- Vega powerplay improvements
- Add CRC support for DCE 12
- SR-IOV support for new security policy
- Various cleanups

From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190529220944.14464-1-alexander.deucher@amd.com
2019-05-31 10:04:39 +10:00
Colin Ian King
cf401e2856 drm/amdkfd: fix null pointer dereference on dev
The pointer dev is set to null yet it is being dereferenced when
checking dev->dqm->sched_policy.  Fix this by performing the check
on dev->dqm->sched_policy after dev has been assigned and null
checked.  Also remove the redundant null assignment to dev.

Addresses-Coverity: ("Explicit null dereference")
Fixes: 1a058c3376 ("drm/amdkfd: New IOCTL to allocate queue GWS")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-29 16:50:09 -05:00
Emily Deng
394e9a14c6 drm/amdgpu: Need to set the baco cap before baco reset
For passthrough, after rebooted the VM, driver will do
a baco reset before doing other driver initialization during loading
 driver. For doing the baco reset, it will first
check the baco reset capability. So first need to set the
cap from the vbios information or baco reset won't be
enabled.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-28 14:47:42 -05:00
Alex Deucher
d55f33da54 drm/amdgpu/soc15: skip reset on init
Not necessary on soc15 and breaks driver reload on server cards.

Acked-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-28 14:47:20 -05:00
Chunming Zhou
8d8a5a64a8 drm/amdgpu: add DRIVER_SYNCOBJ_TIMELINE to amdgpu
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Flora Cui <Flora.Cui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-28 14:45:46 -05:00
Oak Zeng
0235097371 drm/amdkfd: PM4 packets change to support GWS
Add a field in map_queues packet to indicate whether
this is a gws control queue. Only one queue per process
can be gws control queue. Change num_gws field in
map_process packet to 7 bits

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-28 14:44:37 -05:00