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drm/amd/display: Add GSL source select registers
GSL is a form of locking that can be used to synchronize pipes in a pipe-split configurations when async flip is used. Add the registers here. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -84,7 +84,8 @@
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SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
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SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
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SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
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SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst)
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SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
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SR(GSL_SOURCE_SELECT)
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#define TG_COMMON_REG_LIST_DCN1_0(inst) \
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TG_COMMON_REG_LIST_DCN(inst),\
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@ -156,6 +157,7 @@ struct dcn_optc_registers {
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uint32_t OTG_CRC0_WINDOWA_Y_CONTROL;
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uint32_t OTG_CRC0_WINDOWB_X_CONTROL;
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uint32_t OTG_CRC0_WINDOWB_Y_CONTROL;
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uint32_t GSL_SOURCE_SELECT;
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};
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#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
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@ -266,7 +268,10 @@ struct dcn_optc_registers {
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SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
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SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
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SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
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SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh)
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SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
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SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
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SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
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SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh)
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#define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
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@ -413,7 +418,10 @@ struct dcn_optc_registers {
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type OTG_CRC0_WINDOWB_X_START;\
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type OTG_CRC0_WINDOWB_X_END;\
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type OTG_CRC0_WINDOWB_Y_START;\
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type OTG_CRC0_WINDOWB_Y_END;
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type OTG_CRC0_WINDOWB_Y_END;\
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type GSL0_READY_SOURCE_SEL;\
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type GSL1_READY_SOURCE_SEL;\
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type GSL2_READY_SOURCE_SEL;
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#define TG_REG_FIELD_LIST(type) \
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