Commit Graph

4699 Commits

Author SHA1 Message Date
Olof Johansson
4cb0f05d37 mvebu dt64 for 5.3 (part 1)
For Armada 7K/8K:
  - enable AP806 thermal throttling with CPUfreq
  - add missing #interrupt-cells property allowing configuring
    interrupt for GPIO
 
 On Armada 8040 based board:
 - Fix PCI memory window on Mcbin board
 - Set SFP power limit on clearfog GT board
 - Disable AP I2C on Armada-8040-DB
 
 On Armada 3720 based board espressobin correct the SPI node used for
 NOR flash
 
 On Armada 7040 DB board add USB current regulators
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Merge tag 'mvebu-dt64-5.3-1' of git://git.infradead.org/linux-mvebu into arm/dt

mvebu dt64 for 5.3 (part 1)

For Armada 7K/8K:
 - enable AP806 thermal throttling with CPUfreq
 - add missing #interrupt-cells property allowing configuring
   interrupt for GPIO

On Armada 8040 based board:
- Fix PCI memory window on Mcbin board
- Set SFP power limit on clearfog GT board
- Disable AP I2C on Armada-8040-DB

On Armada 3720 based board espressobin correct the SPI node used for
NOR flash

On Armada 7040 DB board add USB current regulators

* tag 'mvebu-dt64-5.3-1' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: add missing #interrupt-cells property
  arm64: dts: marvell: armada-7040-db: Add USB current regulators
  arm64: dts: armada-3720-espressobin: correct spi node
  arm64: dts: marvell: Disable AP I2C on Armada-8040-DB
  arm64: dts: marvell: Enable AP806 thermal throttling with CPUfreq
  arm64: dts: marvell: Change core numbering in AP806 thermal-node
  arm64: dts: marvell: clearfog-gt-8k: set SFP power limit
  arm64: dts: marvell: mcbin: enlarge PCI memory window

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-25 04:47:08 -07:00
Olof Johansson
d71036005f Renesas ARM64 Based SoC DT Updates for v5.3
* Renesas SoCs
   - Revise usb2_phy nodes and phys properties according to updated bindings
   - Use ip=on for bootargs
 
 * R-Car Gen 3 and RZ/G2M (r8a774a1) SoCs
   - Add dynamic power coefficient
   - Create thermal zone to support IPA
 
 * R-Car E3 (r8a77990) and D3 (r8a77995) SoCs
   - Point LVDS0 to its companion LVDS1
 
 * R-Car E3 (r8a77990) SoC
   - Corresct register range of DU
 
 * R-Car E3 (r8a77990) based Ebisu board
   - Remove renesas, no-ether-link property
 
 * R-Car D3 (r8a77995) based Draak board:
   - Remove unnecessary index from vin4 port
 
 * RZ/G2M (r8a774a1) based HiHope main and sub-boards:
   - Initial support
   - Describe CPU capacity and topoligy
   - Enable CMT, HDMI, LEDs, PCIe RWDT, SCIF, SDHI, TMU, and USB 2.0 and 3.0
 
 * RZ/G2E (r8a774c0) SoC based EK874 board:
   - Clean up CPU compatible strings
   - Enable: Bluetooth, HDMI audio and video, TPU, USB 3.0 and WLAN
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Merge tag 'renesas-arm64-dt-for-v5.3' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/dt

Renesas ARM64 Based SoC DT Updates for v5.3

* Renesas SoCs
  - Revise usb2_phy nodes and phys properties according to updated bindings
  - Use ip=on for bootargs

* R-Car Gen 3 and RZ/G2M (r8a774a1) SoCs
  - Add dynamic power coefficient
  - Create thermal zone to support IPA

* R-Car E3 (r8a77990) and D3 (r8a77995) SoCs
  - Point LVDS0 to its companion LVDS1

* R-Car E3 (r8a77990) SoC
  - Corresct register range of DU

* R-Car E3 (r8a77990) based Ebisu board
  - Remove renesas, no-ether-link property

* R-Car D3 (r8a77995) based Draak board:
  - Remove unnecessary index from vin4 port

* RZ/G2M (r8a774a1) based HiHope main and sub-boards:
  - Initial support
  - Describe CPU capacity and topoligy
  - Enable CMT, HDMI, LEDs, PCIe RWDT, SCIF, SDHI, TMU, and USB 2.0 and 3.0

* RZ/G2E (r8a774c0) SoC based EK874 board:
  - Clean up CPU compatible strings
  - Enable: Bluetooth, HDMI audio and video, TPU, USB 3.0 and WLAN

* tag 'renesas-arm64-dt-for-v5.3' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (53 commits)
  arm64: dts: renesas: hihope-common: Remove "label" from LEDs
  arm64: dts: renesas: hihope-common: Add HDMI support
  arm64: dts: renesas: r8a774a1: Add HDMI encoder instance
  arm64: dts: renesas: r8a774a1: Add dynamic power coefficient
  arm64: dts: renesas: r8a774a1: Create thermal zone to support IPA
  arm64: dts: renesas: r8a774a1: Add CPU capacity-dmips-mhz
  arm64: dts: renesas: r8a774a1: Add CPU topology on r8a774a1 SoC
  arm64: dts: renesas: hihope-common: Add LEDs support
  arm64: dts: renesas: hihope-common: Enable USB3.0
  arm64: dts: renesas: hihope-common: Add USB 2.0 support
  arm64: dts: renesas: r8a774a1: Fix USB 2.0 clocks
  arm64: dts: renesas: r8a774a1: Add TMU device nodes
  arm64: dts: renesas: r8a774a1: Add CMT device nodes
  arm64: dts: renesas: hihope-common: Add uSD and eMMC
  arm64: dts: renesas: r8a77990: Fix register range of display node
  arm64: dts: renesas: cat874: Enable usb role switch support
  arm64: dts: renesas: cat874: Enable USB3.0 host/peripheral device node
  arm64: dts: renesas: r8a7799[05]: Point LVDS0 to its companion LVDS1
  arm64: dts: renesas: hihope-common: Add RWDT support
  arm64: dts: renesas: hihope-rzg2-ex: Enable PCIe support
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-25 04:45:45 -07:00
Olof Johansson
8fbf1bb715 This time we only have a single patch for our command branch between
arm and arm64, a fix for the array syntax raised by our DT schemas.
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Merge tag 'sunxi-h3-h5-for-5.3-201906210812' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

This time we only have a single patch for our command branch between
arm and arm64, a fix for the array syntax raised by our DT schemas.

* tag 'sunxi-h3-h5-for-5.3-201906210812' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  ARM: dts: sunxi: h3/h5: Fix GPIO regulator state array

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-25 04:42:05 -07:00
Olof Johansson
3264c72dcc Our usual bunch of arm64 DT changes, this time with:
- Some fixes for the DT schemas that were added during this release
   - Wifi support for the H6
   - LRADC suppport for the A64
   - Some background work on A64 boards, to enable various devices such
     as touchscreens, PMIC, audio, wifi, etc.
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Merge tag 'sunxi-dt64-for-5.3-201906210808' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

Our usual bunch of arm64 DT changes, this time with:
  - Some fixes for the DT schemas that were added during this release
  - Wifi support for the H6
  - LRADC suppport for the A64
  - Some background work on A64 boards, to enable various devices such
    as touchscreens, PMIC, audio, wifi, etc.

* tag 'sunxi-dt64-for-5.3-201906210808' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: dts: allwinner: h6: Add DMA node
  arm64: dts: allwinner: a64: Add lradc node
  dt-bindings: input: sun4i-lradc-keys: Add A64 compatible
  arm64: dts: allwinner: h6: add r_watchog node
  arm64: dts: allwinner: h6: add watchdog node
  dt-bindings: watchdog: add Allwinner H6 watchdog
  arm64: dts: allwinner: a64: Enable audio on Teres-I
  arm64: dts: allwinner: a64: bananapi-m64: Enable PMIC USB power supply
  arm64: dts: allwinner: axp803: add USB power supply node
  arm64: dts: allwinner: a64: Add pinmux for RGB666 LCD
  arm64: dts: allwinner: a64: orangepi-win: Add wifi and bluetooth nodes
  arm64: dts: allwinner: h6: add PIO VCC bank supplies for Pine H64
  arm64: dts: allwinner: a64-oceanic-5205-5inmfd: Enable GT911 CTP
  arm64: dts: allwinner: a64-amarula-relic: Add GT5663 CTP node
  arm64: dts: allwinner: a64: move I2C pinctrl to dtsi

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-25 04:41:39 -07:00
Olof Johansson
750ee7858f Qualcomm ARM64 Updates for v5.3
* Switch to use second gen PON on PM8998
 * Add PSCI cupidle states for MSM8996, MSM8998,and SDM845
 * Add MSM8996 UFS phy reset controller
 * Add propre cpu capacity scaling on MSM8996
 * Fixups for APR domain, legacy clocks, and PSCI entry latency on MSM8996
 * Enable SMMUs on MSM8996
 * Add Dragonboard 845C
 * Add Q6V5, GPU, GMU, and AOSS QMP node on SDM845
 * Fixup CPU topology on SDM845
 * Change USB1 to be peripheral on SDM845 MTP
 * Add PCIe Phy, RC nodes, ANOC1 SMMU, and RPMPD node on MSM8998
 * Update coresight bindings for MSM8916
 * Update idle state names and entry-method on MSM8916
 * Add PCIe, RPMPD, LPASS, Q6, TCSR, TuringCC, PSCI cpuidle states,
   and CDSP on QCS404
 * Add reset-cells property to QCS404 GCC node
 * Fixup s3 max voltage, l3 min voltage, drive strength typo, and
   s3 supply definition on QCS404-evb
 * Fixup ADC outputs and VADC calibration on PMS405
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Merge tag 'qcom-arm64-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 Updates for v5.3

* Switch to use second gen PON on PM8998
* Add PSCI cupidle states for MSM8996, MSM8998,and SDM845
* Add MSM8996 UFS phy reset controller
* Add propre cpu capacity scaling on MSM8996
* Fixups for APR domain, legacy clocks, and PSCI entry latency on MSM8996
* Enable SMMUs on MSM8996
* Add Dragonboard 845C
* Add Q6V5, GPU, GMU, and AOSS QMP node on SDM845
* Fixup CPU topology on SDM845
* Change USB1 to be peripheral on SDM845 MTP
* Add PCIe Phy, RC nodes, ANOC1 SMMU, and RPMPD node on MSM8998
* Update coresight bindings for MSM8916
* Update idle state names and entry-method on MSM8916
* Add PCIe, RPMPD, LPASS, Q6, TCSR, TuringCC, PSCI cpuidle states,
  and CDSP on QCS404
* Add reset-cells property to QCS404 GCC node
* Fixup s3 max voltage, l3 min voltage, drive strength typo, and
  s3 supply definition on QCS404-evb
* Fixup ADC outputs and VADC calibration on PMS405

* tag 'qcom-arm64-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (39 commits)
  arm64: dts: qcom: qcs404-evb: fix vdd_apc supply
  arm64: dts: qcom: pm8998: Use qcom,pm8998-pon binding for second gen pon
  arm64: dts: qcom: msm8996: Enable SMMUs
  arm64: dts: qcom: msm8996: Correct apr-domain property
  arm64: dts: qcom: Add Dragonboard 845c
  arm64: dts: qcom: qcs404-evb: Enable PCIe
  arm64: dts: qcom: qcs404: Add PCIe related nodes
  arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes
  arm64: dts: qcom: msm8998: Add ANOC1 SMMU node
  arm64: dts: qcom: msm8996: Stop using legacy clock names
  arm64: dts: msm8996: fix PSCI entry-latency-us
  arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states
  arm64: dts: qcom: sdm845: Add Q6V5 MSS node
  arm64: dts: qcom: Add AOSS QMP node
  arm64: dts: qcom-qcs404: Add reset-cells to GCC node
  arm64: dts: qcom-msm8916: Update coresight DT bindings
  arm64: dts: qcom: msm8998: Add rpmpd node
  arm64: dts: qcom: qcs404: Add rpmpd node
  arm64: dts: qcom: qcs404: Move lpass and q6 into soc
  arm64: dts: qcom: qcs404: Fully describe the CDSP
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-25 04:31:37 -07:00
Olof Johansson
80f7f92c16 ARM64: DT: Hisilicon SoCs DT updates for v5.3
* Hi3660 SoC and related boards:
   - Added CoreSight trace components
 
 * Hi6220 SoC and related boards:
   - Updated CoreSight funnel and replicator using new bindings to fix warning
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Merge tag 'hisi-arm64-dt-for-5.3' of git://github.com/hisilicon/linux-hisi into arm/dt

ARM64: DT: Hisilicon SoCs DT updates for v5.3

* Hi3660 SoC and related boards:
  - Added CoreSight trace components

* Hi6220 SoC and related boards:
  - Updated CoreSight funnel and replicator using new bindings to fix warning

* tag 'hisi-arm64-dt-for-5.3' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hi3660: Add CoreSight support
  arm64: dts: hi6220: Update coresight DT bindings

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-25 04:30:13 -07:00
Jorge Ramirez-Ortiz
2410fd450c arm64: dts: qcom: qcs404-evb: fix vdd_apc supply
The invalid definition in the supply causes the Qualcomm's EVB-1000
and EVB-4000 not to boot.

Fix the boot issue by correctly defining the supply: vdd_s3 (namely
"vdd_apc") is actually connected to vph_pwr.

Reported-by: Niklas Cassel <niklas.cassel@linaro.org>
Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
2019-06-19 23:50:52 -05:00
Olof Johansson
4ed7e4e578 Texas Instruments K3 SoC family changes for 5.3
- Add support for the new J721e SoC, includes basic peripherals needed for
   booting up the device
 - New peripheral support added for AM654x:
   * TI SCI irqchip
   * GPIO
   * MCU SRAM
   * R5Fs
   * MSMC RAM
   * SERDES and PCIe
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Merge tag 'ti-k3-soc-for-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt

Texas Instruments K3 SoC family changes for 5.3

- Add support for the new J721e SoC, includes basic peripherals needed for
  booting up the device
- New peripheral support added for AM654x:
  * TI SCI irqchip
  * GPIO
  * MCU SRAM
  * R5Fs
  * MSMC RAM
  * SERDES and PCIe

* tag 'ti-k3-soc-for-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux: (26 commits)
  arm64: dts: ti: k3-j721e: Add the MCU SRAM node
  arm64: dts: ti: k3-j721e: Add interrupt controllers in wakeup domain
  arm64: dts: ti: k3-j721e: Add interrupt controllers in main domain
  arm64: dts: ti: k3-j721e-main: Add Main NavSS Interrupt controller node
  arm64: defconfig: Enable TI's J721E SoC platform
  arm64: dts: ti: Add support for J721E Common Processor Board
  soc: ti: Add Support for J721E SoC config option
  arm64: dts: ti: Add Support for J721E SoC
  dt-bindings: serial: 8250_omap: Add compatible for J721E UART controller
  dt-bindings: arm: ti: Add bindings for J721E SoC
  arm64: dts: ti: am654-base-board: Disable SERDES and PCIe
  arm64: dts: k3-am6: Add PCIe Endpoint DT node
  arm64: dts: k3-am6: Add PCIe Root Complex DT node
  arm64: dts: k3-am6: Add SERDES DT node
  arm64: dts: k3-am6: Add mux-controller DT node required for muxing SERDES
  arm64: dts: k3-am6: Add "socionext,synquacer-pre-its" property to gic_its
  arm64: dts: ti: k3-am65: Add MSMC RAM ranges in interconnect node
  arm64: dts: ti: k3-am65: Add R5F ranges in interconnect nodes
  arm64: dts: ti: k3-am65-mcu: Add the MCU RAM node
  arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodes
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19 09:03:38 -07:00
Olof Johansson
50f5ef466d SoCFPGA DTS updates for v5.3
- Use the new "altr,socfpga-stmmac-a10-s10" for the EMAC controllers on
   Arria10/Stratix10
 - Add the ltc2497 i2c entry on the Arria10 devkit
 - Add the EMAC OCP reset property on the Arria10
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Merge tag 'socfpga_dts_updates_for_v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt

SoCFPGA DTS updates for v5.3
- Use the new "altr,socfpga-stmmac-a10-s10" for the EMAC controllers on
  Arria10/Stratix10
- Add the ltc2497 i2c entry on the Arria10 devkit
- Add the EMAC OCP reset property on the Arria10

* tag 'socfpga_dts_updates_for_v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: dts: arria10: Add EMAC OCP reset property
  ARM: dts: socfpga: add ltc2497 on arria10 devkit
  arm64: dts: stratix10: use the "altr,socfpga-stmmac-a10-s10" binding
  ARM: dts: socfpga: use the "altr,socfpga-stmmac-a10-s10" binding

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19 09:00:58 -07:00
Wanglai Shi
9500ff14c4 arm64: dts: hi3660: Add CoreSight support
This patch adds DT bindings for the CoreSight trace components
on hi3660, which is used by 96boards Hikey960.

Signed-off-by: Wanglai Shi <shiwanglai@hisilicon.com>
Reviewed-and-tested-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2019-06-19 15:43:31 +01:00
Leo Yan
b6f7cd7fae arm64: dts: hi6220: Update coresight DT bindings
CoreSight DT bindings have been updated, thus the old compatible strings
are obsolete and the drivers will report warning if DTS uses these
obsolete strings.

This patch switches to the new bindings for CoreSight dynamic funnel and
static replicator, so can dismiss warning during initialisation.

Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Guodong Xu <guodong.xu@linaro.org>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2019-06-19 15:32:25 +01:00
Fabrizio Castro
f6130381e2 arm64: dts: renesas: hihope-common: Remove "label" from LEDs
Remove "label" properties from the LEDs device tree nodes, since
we don't have nice labels on the PCB.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-19 16:32:13 +02:00
Fabrizio Castro
89d6adc63f arm64: dts: renesas: hihope-common: Add HDMI support
Add HDMI support to the HiHope RZ/G2[MN] mother board common
dtsi.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-19 16:04:03 +02:00
Fabrizio Castro
8c96564235 arm64: dts: renesas: r8a774a1: Add HDMI encoder instance
Add the HDMI encoder to the R8A774A1 DT in disabled state.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-19 15:52:02 +02:00
Olof Johansson
65004867c9 Merge tag 'juno-updates-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt
ARMv8 Juno updates for v5.3

Couple of updates switching to use new/updated bindings for CoreSight
dynamic funnel components and NOR flash partition type

* tag 'juno-updates-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: juno: set the right partition type for NOR flash
  arm64: dts: juno: update coresight DT bindings

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19 06:36:31 -07:00
Olof Johansson
3aa45174e1 Merge tag 'arm-soc/for-5.3/devicetree-arm64' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree changes
for 5.3, please pull the following:

- Pramod adds the Device Tree nodes for thermal support on Stingray

- Srinath adds the Device Tree nodes for both XHCI (host) and BDC
  (device) modes

- Rayagonda adds the Device Tree node for slave I2C operation when
  Stingray operates as a SmartNIC

* tag 'arm-soc/for-5.3/devicetree-arm64' of https://github.com/Broadcom/stblinux:
  arm64: dts: Stingray: Add NIC i2c device node
  arm64: dts: Add USB DT nodes for Stingray SoC
  arm64: dts: stingray: Add Stingray Thermal DT support.

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19 06:36:22 -07:00
Olof Johansson
3990c9918a PCIe for rockpro64, wifi+bt for Rock-PI4, spi for Rock960 family
and a fix for the yet unused isp-iommus.
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Merge tag 'v5.3-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

PCIe for rockpro64, wifi+bt for Rock-PI4, spi for Rock960 family
and a fix for the yet unused isp-iommus.

* tag 'v5.3-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: add WiFi+BT support on ROCK Pi4 board
  arm64: dts: rockchip: fix isp iommu clocks and power domain
  arm64: dts: rockchip: Enable SPI1 on Ficus
  arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960
  arm64: dts: rockchip: add PCIe nodes on rk3399-rockpro64

Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19 06:22:43 -07:00
Andy Gross
0763d0c227 arm64: qcom: qcs404: Add reset-cells to GCC node
This patch adds a reset-cells property to the gcc controller on the QCS404.
Without this in place, we get warnings like the following if nodes reference
a gcc reset:

arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property):
/soc@0/remoteproc@b00000: Missing property '#reset-cells' in node
/soc@0/clock-controller@1800000 or bad phandle (referred from resets[0])
  also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3
  DTC     arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb
arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property):
/soc@0/remoteproc@b00000: Missing property '#reset-cells' in node
/soc@0/clock-controller@1800000 or bad phandle (referred from resets[0])
  also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3

Signed-off-by: Andy Gross <agross@kernel.org>
Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19 06:17:54 -07:00
Baolin Wang
c311f4ff2b arm64: dts: sprd: Add Spreadtrum SD host controller support
Add one Spreadtrum SD host controller to support eMMC card for Spreadtrum
SC9860 platform.

Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19 06:16:40 -07:00
Suman Anna
78eccc2ac9 arm64: dts: ti: k3-j721e: Add the MCU SRAM node
Add the on-chip SRAM present within the MCU domain as a mmio-sram node.
The K3 J721E SoCs have 1 MB of such memory. Any specific memory range
within this RAM needed by a driver/software module ought to be reserved
using an appropriate child node.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19 11:59:49 +03:00
Lokesh Vutla
ae7d8505b1 arm64: dts: ti: k3-j721e: Add interrupt controllers in wakeup domain
Wakeup domain in J721E SoC has an interrupt router connected to gpio
in wakeup domain. Add DT node for this interrupt router.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19 11:59:49 +03:00
Lokesh Vutla
073086fc68 arm64: dts: ti: k3-j721e: Add interrupt controllers in main domain
Main domain in J721E has the following interrupt controller instances:
- Main Domain GPIO Interrupt router connected to gpio in main domain.
- Under the Main Domain Navigator Subsystem(NAVSS)
	- Main Navss Interrupt Router connected to main navss inta and mailboxes.
	- Main Navss Interrupt Aggregator connected to main domain UDMASS

Add DT nodes for the interrupt controllers available in main domain.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19 11:59:49 +03:00
Suman Anna
1463a70dfc arm64: dts: ti: k3-j721e-main: Add Main NavSS Interrupt controller node
Add the Interrupt controller node for the Interrupt Router present within
the Main NavSS module. This Interrupt Router can route 192 interrupts to
the GIC_SPI in 3 sets of 64 interrupts each. Note that the last set is
reserved for the host ID A72_3 for hypervisor usecases, so the node is
added only with 2 sets for the Linux kernel context (host id A72_2). This
is specified through the ti,sci-rm-range-girq property.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19 11:59:49 +03:00
Nishanth Menon
803d3a1870 arm64: dts: ti: Add support for J721E Common Processor Board
Add Support for J721E Common Processor board support.
The EVM architecture is as follows:

+------------------------------------------------------+
|   +-------------------------------------------+      |
|   |                                           |      |
|   |        Add-on Card 1 Options              |      |
|   |                                           |      |
|   +-------------------------------------------+      |
|                                                      |
|                                                      |
|                     +-------------------+            |
|                     |                   |            |
|                     |   SOM             |            |
|  +--------------+   |                   |            |
|  |              |   |                   |            |
|  |  Add-on      |   +-------------------+            |
|  |  Card 2      |                                    |    Power Supply
|  |  Options     |                                    |    |
|  |              |                                    |    |
|  +--------------+                                    | <---
+------------------------------------------------------+
                                Common Processor Board

Common Processor board is the baseboard that has most of the actual
connectors, power supply etc. A SOM (System on Module) is plugged on
to the common processor board and this contains the SoC, PMIC, DDR and
basic high speed components necessary for functionality. Add-n card
options add further functionality (such as additional Audio, Display,
networking options).

Note:
A) The minimum configuration required to boot up the board is System On
   Module(SOM) + Common Processor Board.
B) Since there is just a single SOM and Common Processor Board, we are
   maintaining common processor board as the base dts and SOM as the dtsi
   that we include. In the future as more SOM's appear, we should move
   common processor board as a dtsi and include configurations as dts.
C) All daughter cards beyond the basic boards shall be maintained as
   overlays.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19 11:59:48 +03:00
Nishanth Menon
2d87061e70 arm64: dts: ti: Add Support for J721E SoC
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.

Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
  capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
  C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
  and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
  PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
  up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
  addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
  capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
  16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
  I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
  management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
  capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
  Management (DMSC)

See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19 11:59:48 +03:00
John Stultz
6fd7c4da54 arm64: dts: qcom: pm8998: Use qcom,pm8998-pon binding for second gen pon
This changes pm8998 to use the new qcom,pm8998-pon compatible
string for the pon in order to support the gen2 pon
functionality properly.

Cc: Andy Gross <agross@kernel.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Amit Pundir <amit.pundir@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Sebastian Reichel <sre@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
2019-06-19 00:30:01 -05:00
Bjorn Andersson
72825e7f4a arm64: dts: qcom: msm8996: Enable SMMUs
Enable SMMUs on 8996 now that the WRZ workaround in the arm-smmu driver
has landed.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
2019-06-19 00:23:29 -05:00
Bjorn Andersson
64a68a7360 arm64: dts: qcom: msm8996: Correct apr-domain property
The domain specifier was changed from using "reg" to "qcom,apr-domain",
update the dts accordingly.

Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-18 17:13:23 -07:00
Bjorn Andersson
3f72e2d3e6 arm64: dts: qcom: Add Dragonboard 845c
This adds an initial dts for the Dragonboard 845. Supported
functionality includes Debug UART, UFS, USB-C (peripheral), USB-A
(host), microSD-card and Bluetooth.

Initializing the SMMU is clearing the mapping used for the splash screen
framebuffer, which causes the board to reboot. This can be worked around
using:

  fastboot oem select-display-panel none

Reviewed-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Tested-by: Vinod Koul <vkoul@kernel.org>
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-18 14:24:41 -07:00
Biju Das
9e35f49cf7 arm64: dts: renesas: r8a774a1: Add dynamic power coefficient
Describe the dynamic power coefficient of A57 and A53 CPUs.

Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> and others.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18 12:42:29 +02:00
Biju Das
06a928fb58 arm64: dts: renesas: r8a774a1: Create thermal zone to support IPA
Setup a thermal zone driven by SoC temperature sensor. Create passive trip
points and bind them to CPUFreq cooling device that supports power
extension.

Based on work by Dien Pham <dien.pham.ry@renesas.com> for r8a7796 SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18 12:42:17 +02:00
Biju Das
5f5249497b arm64: dts: renesas: r8a774a1: Add CPU capacity-dmips-mhz
Set the capacity-dmips-mhz for RZ/G2M(r8a774a1) SoC, that is based on
dhrystone.

Based on work done by Gaku Inami <gaku.inami.xw@bp.renesas.com> for
r8a7796 SoC.

The average dhrystone result for 5 iterations is as below:

r8a774a1 SoC (CA57x2 + CA53x4)
  CPU   max-freq   dhrystone
  ---------------------------------
  CA57   1500 MHz  11428571 lps/s
  CA53   1200 MHz   5000000 lps/s

From this, CPU capacity-dmips-mhz for CA57 and CA53 are calculated
as follows:

r8a774a1 SoC
  CA57 : 1024 / (11428571 / 1500) * (11428571 / 1500) = 1024
  CA53 : 1024 / (11428571 / 1500) * ( 5000000 / 1200) =  560

Since each CPUs have different max frequencies, the final CPU
capacities of A53 scaled by the above difference is as below

$ cat /sys/devices/system/cpu/cpu*/cpu_capacity
1024
1024
448
448
448
448

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18 12:42:02 +02:00
Biju Das
7b996955e5 arm64: dts: renesas: r8a774a1: Add CPU topology on r8a774a1 SoC
This patch adds the "cpu-map" into r8a774a1 composed of multi-cluster. This
definition is used to parse the cpu topology.

Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> for r8a7796 SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18 12:41:49 +02:00
Fabrizio Castro
1485b6353a arm64: dts: renesas: hihope-common: Add LEDs support
This patch adds LEDs support to the HiHope RZ/G2[MN] Main Board
common device tree.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18 12:39:58 +02:00
Biju Das
3ba27637d8 arm64: dts: renesas: hihope-common: Enable USB3.0
This patch enables USB3.0 host/peripheral device node for the HiHope
RZ/G2M board.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18 12:38:48 +02:00
Russell King
200f5c4081 arm64: dts: marvell: add missing #interrupt-cells property
The GPIO interrupt controllers are missing their required
specified in DT.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-06-18 10:17:39 +02:00
Bjorn Andersson
73786fea02 arm64: dts: qcom: qcs404-evb: Enable PCIe
Enable the PCIe PHY and controller found on the QCS404 EVB.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-17 23:23:45 -07:00
Bjorn Andersson
431f64642c arm64: dts: qcom: qcs404: Add PCIe related nodes
The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, define these
to for the platform.

Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-17 23:23:45 -07:00
Marc Gonzalez
b84dfd175c arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes
Add MSM8998 PCIe QMP PHY and PCIe root complex DT nodes.

Based on the following DTS downstream:
https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998.dtsi?h=LE.UM.1.3.r3.25#n2537

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-17 08:50:24 -07:00
Marc Gonzalez
8389b869bb arm64: dts: qcom: msm8998: Add ANOC1 SMMU node
The MSM8998 ANOC1(*) SMMU services BLSP2, PCIe, UFS, and USB.
(*) Aggregate Network-on-Chip #1

Based on the following DTS downstream:
https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi?h=LE.UM.1.3.r3.25#n18

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-17 08:48:24 -07:00
Kishon Vijay Abraham I
1b89dc93b8 arm64: dts: ti: am654-base-board: Disable SERDES and PCIe
AM654 base board does not have any PCIe slots. Disable all the
SERDES and PCIe instances.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17 17:58:44 +03:00
Kishon Vijay Abraham I
30eb8ea46c arm64: dts: k3-am6: Add PCIe Endpoint DT node
Add PCIe Endpoint DT node.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17 17:58:44 +03:00
Kishon Vijay Abraham I
cfa6437a71 arm64: dts: k3-am6: Add PCIe Root Complex DT node
Add PCIe Root Complex DT node.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17 17:58:43 +03:00
Kishon Vijay Abraham I
cedc255cc6 arm64: dts: k3-am6: Add SERDES DT node
Add DT node for SERDES0 and SERDES1.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17 17:58:43 +03:00
Kishon Vijay Abraham I
1cbe04b0b7 arm64: dts: k3-am6: Add mux-controller DT node required for muxing SERDES
Add mux-controller DT node as a child node of scm_conf. This is
required for muxing SERDES between USB, PCIe and ICSS2 SGMII.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17 17:58:43 +03:00
Kishon Vijay Abraham I
4b4ffc6e1f arm64: dts: k3-am6: Add "socionext,synquacer-pre-its" property to gic_its
GIC_ITS used in AM654 platform has the same configuration as that of
GIC_ITS used in Socionext SoCs. Add "socionext,synquacer-pre-its"
property to get PCI MSI working.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17 17:58:43 +03:00
Roger Quadros
cc2d13e750 arm64: dts: ti: k3-am65: Add MSMC RAM ranges in interconnect node
Add the MSCM RAM address space to the ranges property of the cbass_main
interconnect node so that the addresses can be translated properly.

This fixes the probe failure in the sram driver for the MSMC RAM node.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17 17:50:24 +03:00
Suman Anna
833123386c arm64: dts: ti: k3-am65: Add R5F ranges in interconnect nodes
Add the address spaces for the R5F cores in MCU domain to the ranges
property of the cbass_mcu interconnect node so that the addresses
within the R5F nodes can be translated properly by the relevant OF
address API.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17 17:32:51 +03:00
Suman Anna
f853f00531 arm64: dts: ti: k3-am65-mcu: Add the MCU RAM node
Add the on-chip SRAM present within the MCU domain as a mmio-sram node.
The K3 AM65x SoCs have 512 KB of such memory. Any specific memory range
within this RAM needed by a software module ought to be reserved using
an appropriate child node.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17 17:31:31 +03:00
Suman Anna
0ded541218 arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodes
Add the address space for the MCU SRAM memory to the ranges property
of the cbass_mcu interconnect node so that the addresses within the
mcu_sram nodes and its children can be translated properly by the
relevant OF address API.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17 17:31:30 +03:00