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arm64: dts: qcom: msm8998: Add ANOC1 SMMU node

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The MSM8998 ANOC1(*) SMMU services BLSP2, PCIe, UFS, and USB.
(*) Aggregate Network-on-Chip #1

Based on the following DTS downstream:
https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi?h=LE.UM.1.3.r3.25#n18

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Marc Gonzalez 2019-04-01 17:40:13 +02:00 committed by Bjorn Andersson
parent 693e824452
commit 8389b869bb
1 changed files with 15 additions and 0 deletions
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15
arch/arm64/boot/dts/qcom/msm8998.dtsi
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@ -859,6 +859,21 @@ tsens1: thermal@10ae000 {
#thermal-sensor-cells = <1>;
};
anoc1_smmu: iommu@1680000 {
compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
reg = <0x01680000 0x10000>;
#iommu-cells = <1>;
#global-interrupts = <0>;
interrupts =
<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
};
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x20000>;