Ethernet phys based on devicetree specification should be using
ethernet-phy@ node name instead of pure phy@.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Currently CCF clocks sre used in zynqmp dts. So there is no use of
dtsi for fixed clock. Remove dtsi for fixed clock.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Memory address/size depends on board design, so memory node should
be in board DT.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Memory address/size depends on board design, so memory node should
be in board DT.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add DT node for the eeprom data storage on SolidRun i.MX8M SOM.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
LS2088ADB has one spansion flash s25fs512s of size 64M.
Add qspi dts entry for the board using compatibles as "jedec,spi-nor" to
probe flash successfully. Also, align properties with other board dts
properties.
Use dt-bindings constants in interrupts instead of using numbers.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add devicetree support for Thor96 board from Einfochips. This board is
one of the 96Boards Consumer Edition platform powered by the NXP
i.MX8MQ SoC.
Following are the features supported currently:
1. uSD
2. WiFi/BT
3. Ethernet
4. EEPROM (M24256)
5. NOR Flash (W25Q256JW)
6. 2xUSB3.0 ports and 1xUSB2.0 port at HS expansion
More information about this board can be found in Arrow website:
https://www.arrow.com/en/products/i.imx8-thor96/arrow-development-tools
Link to 96Boards CE Specification: https://linaro.co/ce-specification
Signed-off-by: Darshak Patel <darshak.patel@einfochips.com>
[Mani: cleaned up for upstream]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The rk3399-roc-pc uses a MP8859 DC/DC converter for 12V supply.
This supplies 5V only in default state after booting.
Now we can control the output voltage via I2C interface.
Add a node for the driver to reach 12V.
Signed-off-by: Markus Reichl <m.reichl@fivetechno.de>
Link: https://lore.kernel.org/r/20200106211633.2882-6-m.reichl@fivetechno.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Explicitly set the switch cpu (upstream) port phy-mode and managed
properties. This fixes the Marvell 88E6141 switch serdes configuration
with the recently enabled phylink layer.
Fixes: a612083327 ("arm64: dts: add support for SolidRun Clearfog GT 8K")
Reported-by: Denis Odintsov <d.odintsov@traviangames.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add the property describing the depth of the audio fifo on the axg, g12a
and sm1 SoC family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The PCIe 'bus-range' setting is incorrect and causing the following
message during boot.
pci_bus 0000:01: busn_res: can not insert [bus 01-ff] under [bus 00-0f] (conflicts with (null) [bus 00-0f])
Correct it to get rid of the message.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
APQ8096 has its VDD APC (Power for quad Kryo applications
microprocessors) powered by PM8996 PMIC S9, S10, S11 tri-phase
regulators (gang). The bootloader may have configured these
regulators with non sustainable default values, leading to sporadic
hangs under CPU stress tests (cpufreq-bench). Ideally we should enable
voltage scaling along with frequency scaling, but for now just set the
regulator gang value to a sane voltage, capable of supporting highest
frequencies (turbo).
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Link: https://lore.kernel.org/r/1578401755-26211-1-git-send-email-loic.poulain@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
vdd_apc is the regulator that supplies the main CPU cluster.
At sudden CPU load changes, we have noticed invalid page faults on
addresses with all bits shifted, as well as on addresses with individual
bits flipped.
By putting the vdd_apc regulator in high power mode, the voltage drops
during sudden load changes will be less severe, and we have not been able
to reproduce the invalid page faults with the regulator in this mode.
Fixes: 8faea8edbb ("arm64: dts: qcom: qcs404-evb: add spmi regulators")
Cc: stable@vger.kernel.org
Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20191014120920.12691-1-niklas.cassel@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The msm_serial driver has a predefined set of uart ports defined, which
is allocated either by reading aliases or if no match is found a simple
counter, starting at index 0. But there's no logic in place to prevent
these two allocation mechanism from colliding. As a result either none
or all of the active msm_serial instances must be listed as aliases.
Define blsp1_uart3 as "serial1" to mitigate this problem.
Fixes: 4cffb9f2c7 ("arm64: dts: qcom: msm8998-mtp: Enable bluetooth")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lore.kernel.org/r/20191119011823.379100-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The entries "supports-sd" and "supports-emmc" are not a valid Linux option
in relation with SD card or eMMC, so remove them.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20191231175054.4929-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
A few clocks from the CCU were exported later, and references to them in
the device tree were using raw numbers.
Now that the DT binding header changes are in as well, switch to the
macros for more clarity.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The Libre Computer ALL-H5-CC board is an upgraded version of the
ALL-H3-CC. Changes include:
- Gigabit Ethernet via external RTL8211E Ethernet PHY
- 16 MiB SPI NOR flash memory
- PoE tap header
- Line out jack removed
Only H5 variant test samples were made available, and the vendor is not
certain whether other SoC variants would be made or not. Furthermore the
board is a minor upgrade compared to the ALL-H3-CC. Thus the device tree
simply includes the one for the ALL-H3-CC, and adds the changes on top.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Fix the following error/warn seen with make dtbs_check
arm,smmu-venus@d40000: $nodename:0: 'arm,smmu-venus@d40000' does not match '^iommu@[0-9a-f]*'
arm,smmu-venus@d40000: clock-names:0: 'bus' was expected
arm,smmu-venus@d40000: clock-names:1: 'iface' was expected
by rename nodename to "iommu".
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Link: https://lore.kernel.org/r/20200106102305.27059-1-stanimir.varbanov@linaro.org
[bjorn: Added padding of address to 8 digits]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
- Remove now unused ARCH_R8A7796 config symbol,
- Rename R-Car H3 and M3-W SoC, and ULCB board DTS files to increase
naming consistency,
- Miscellaneous fixes for issues detected by "make dtbs_check",
- Enhance support for R-Car M3-W+,
- Display support for the EK874 board,
- Prepare for split of R-Car H3 ES1.x and ES2.0+ config symbols,
- Minor fixes and improvements.
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Merge tag 'renesas-arm64-dt-for-v5.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM64 DT updates for v5.6
- Remove now unused ARCH_R8A7796 config symbol,
- Rename R-Car H3 and M3-W SoC, and ULCB board DTS files to increase
naming consistency,
- Miscellaneous fixes for issues detected by "make dtbs_check",
- Enhance support for R-Car M3-W+,
- Display support for the EK874 board,
- Prepare for split of R-Car H3 ES1.x and ES2.0+ config symbols,
- Minor fixes and improvements.
* tag 'renesas-arm64-dt-for-v5.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: Prepare for split of ARCH_R8A7795 into ARCH_R8A7795[01]
arm64: dts: renesas: Sort DTBs in Makefile
arm64: dts: renesas: Drop redundant SoC prefixes from ULCB DTS file names
arm64: dts: renesas: Rename r8a7795{-es1,}* to r8a7795[01]*
arm64: dts: renesas: Add EK874 board with idk-2121wr display support
arm64: dts: renesas: r8a77961: Add SDHI nodes
arm64: dts: renesas: r8a77961: Add I2C nodes
arm64: dts: renesas: r8a77961: Add SYS-DMAC nodes
arm64: dts: renesas: r8a77961: Add RAVB node
arm64: dts: renesas: r8a77961: Add GPIO nodes
arm64: dts: renesas: r8a77961: Add RWDT node
arm64: dts: renesas: r8a77990: ebisu: Remove clkout-lr-synchronous from sound
arm64: dts: renesas: r8a77970: Group tuples in thermal reg property
arm64: dts: renesas: Group tuples in pci ranges and dma-ranges properties
arm64: dts: renesas: Group tuples in interrupt properties
arm64: dts: renesas: Group tuples in regulator-gpio states properties
arm64: dts: renesas: Rename r8a7796* to r8a77960*
arm64: dts: renesas: Remove use of ARCH_R8A7796
Link: https://lore.kernel.org/r/20200106104857.8361-4-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
Add basic DT to support Unisoc's SC9863A, with this patch,
the board sp9863a-1h10 can run into console.
Link: https://lore.kernel.org/r/20191223092948.24824-4-zhang.lyra@gmail.com
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Apparently I wasn't paying enough attention... And nor is the lazy
test of `cat /dev/lirc0` sufficiently blunder-proof. Oh well, with
the correct polarity, let's also hook up a keymap now that one for
the standard Beelink remote has handily appeared.
Fixes: 79702ded8c ("arm64: dts: rockchip: Add Beelink A1")
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/44269c08e2a5d75b03ded87d2eb11621762d8249.1577636223.git.robin.murphy@arm.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
By default, gpio-keys configures the pin to trigger wakeup IRQs on
either edge. The lid switch should only trigger wakeup when opening the
lid, not when closing it.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
UFS phy register space size is 0x1c0. so update it
Reported-by: Can Guo <cang@codeaurora.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20200106070826.147064-3-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
It adds remote control map name for IR device, so that key event can be
reported.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Support dynamic voltage and frequency scaling on qcs404.
CPUFreq will soon be superseded by Core Power Reduction (CPR, a form
of Adaptive Voltage Scaling found on some Qualcomm SoCs like the
qcs404).
Due to the CPR upstreaming already being in progress - and some
commits already merged - the following commit will need to be
reverted to enable CPUFreq support
Author: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Date: Thu Jul 25 12:41:36 2019 +0200
cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist
Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191125142511.681149-5-niklas.cassel@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The high frequency pll functionality is required to enable CPU
frequency scaling operation.
Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191125142511.681149-3-niklas.cassel@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Specify the clocks that feed the APCS mux/divider instead of using
default hardcoded values in the source code.
The driver still supports the previous bindings; however with this
update it we allow the msm8916 to access the parent clock names
required by the driver operation using the device tree node.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191125142511.681149-2-niklas.cassel@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the DT node for the rpmhpd power controller on SC7180 SoCs.
Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20191220064823.6115-3-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the SPMI regulator node in the PM8004 LSID5 (as there is where
it resides basically 99% of the times) and set the nodes to be
disabled by default, as not all boards have both or one of the
lsids specified in this generic pm8004 DT.
While at it, also add nice phandles to the lsids specified in this
DT to allow configuration in specific board dts in a more human
readable fashion.
Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Link: https://lore.kernel.org/r/20191031111645.34777-3-kholk11@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
To enable the OS to better support PSCI OS initiated CPU suspend mode,
let's convert from the flattened layout to the hierarchical layout.
In the hierarchical layout, let's create a power domain provider per CPU
and describe the idle states for each CPU inside the power domain provider
node. To group the CPUs into a cluster, let's add another power domain
provider and make it act as the master domain. Note that, the CPU's idle
states remains compatible with "arm,idle-state", while the cluster's idle
state becomes compatible with "domain-idle-state".
Co-developed-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
As R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+ (R8A77951) are really
different SoCs, CONFIG_ARCH_R8A7795 will be split in
CONFIG_ARCH_R8A77950 and CONFIG_ARCH_R8A77951.
Relax dependencies by handling both the old and the new symbols.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191217183841.432-5-geert+renesas@glider.be
Sort the entries for the various DTBs in the Makefile by SoC and board
type. Keep Salvator-X(S) together, and do the same for ULCB with and
without Kingfisher extension.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191217183841.432-4-geert+renesas@glider.be
Unlike the V3MSK and V3HSK boards, the various "ULCB" boards are really
the same boards, with different SiPs fitted, just like the Salvator-X(S)
boards. Furthermore, the "H3", "M3", and "M3N" prefixes of the "ULCB"
parts in the DTS file names are redundant, as they are implied by the
SoC part numbers, which are also part of the file names.
Hence drop the redundant prefixes, to make the DTS file names consistent
with the file names for the various "Salvator-X(S)" boards.
Suggested-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191217183841.432-3-geert+renesas@glider.be
Despite using the same compatible values ("r8a7795"-based) because of
historical reasons, R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+
(R8A77951) are really different SoCs, with different part numbers.
Reflect this in the DTS files by changing their base names from
"r8a7795-es1" and "r8a7795" to "r8a77950" resp. "r8a77951".
Drop all "ES" references next to part numbers, as they are implied by
the part numbers, and thus redundant.
Note that DT binding headers, definitions, and compatible values are
not renamed, to preserve backward compatibility.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191217183841.432-2-geert+renesas@glider.be
There are two sensors, one for CPU, one for GPU.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The redistributable firmware should work on any engineering device, so
lets push this to qcom/sdm845, rather than qcom/db845c. Also specify the
path for the modem firmware.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191113203951.3704428-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Introduce a base dts for the Inforce 6640 Single Board Computer. This
initial commit boots to console on the uart and provides UFS and SD card
storage support.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Update the regulator names in db820c.dtsi to use the names from the
schematics, instead of the made up genric names.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Pad all addresses in msm8996.dtsi to 8 digits, in order to make it
easier to ensure ordering when adding new nodes.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Rather than scattering pinctrl definitions in various files, merge the
nodes into db820c.dtsi to make it easier to navigate.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Sort all nodes in db820c.dtsi based on address, then name.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Prior refactoring have left a few root nodes scattered throughout
db820c.dtsi, group these at the top of the file.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
As the definition of available PMICs and the names of their outputs are
board specifc move this to db820c.dtsi
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Supplies for the various components in the SoC depends on board layout,
so move the supply definitions to db820c.dtsi instead of carrying them
in the platform dtsi.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Instead of mimicing the structure of the platform, reference nodes by
their label in apq8096-db820c.dtsi. Add labels in msm8996.dtsi where
necessary.
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The USB id pins and wlan regulator are not platform devices, so move
them out of /soc
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The Libre Computer ALL-H3-IT board is a small single board computer that
is roughly the same size as the Raspberry Pi Zero, or around 20% smaller
than a credit card.
The board features:
- H2, H3, or H5 SoC from Allwinner
- 2 DDR3 DRAM chips
- Realtek RTL8821CU based WiFi module
- 128 Mbit SPI-NOR flash
- micro-SD card slot
- micro HDMI video output
- FPC connector for camera sensor module
- generic Raspberri-Pi style 40 pin GPIO header
- additional pin headers for extra USB host ports, ananlog audio and
IR receiver
Only H5 variant test samples were made available, but the vendor does
have plans to include at least an H3 variant. Thus the device tree is
split much like the ALL-H3-CC, with a common dtsi file for the board
design, and separate dts files including the common board file and the
SoC dtsi file. The other variants will be added as they are made
available.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Add MIPI DSI pipeline for Allwinner A64.
- dsi node, with A64 compatible since it doesn't support
DSI_SCLK gating unlike A33
- dphy node, with A64 compatible with A33 fallback since
DPHY on A64 and A33 is similar
- finally, attach the dsi_in to tcon0 for complete MIPI DSI
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Merlijn Wajer <merlijn@wizzup.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
A64 has 3 thermal sensors: 1 for CPU, 2 for GPU.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
There are two sensors, one for CPU, one for GPU.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The LSM9DS1 uses a high level interrupt.
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
Fixes: eb4ea0857c ("arm64: dts: fsl: librem5: Add a device tree for the Librem5 devkit")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Now that there is driver support, describe the accel and gyro sensor parts
of the LSM9DS1 IMU.
Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The i.MX8M Mini supports the same crypto engine as what is in
the i.MX8MQ, but it is not currently present in the device tree.
This patch places it into the device tree.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch adds the device tree to support Google Coral Edge TPU,
historicaly named as fsl-imx8mq-phanbell, a computer on module
which can be used for AI/ML propose.
It introduces a minimal enablement support for this module and
was totally based on the NXP i.MX 8MQ EVK board and i.MX 8MQ Phanbell
Google Source Code for Coral Edge TPU Mendel release:
https://coral.googlesource.com/linux-imx/
Tested components:
- PMIC;
- USB-C OTG;
- USB-C PWR;
- micro-USB;
- USB.
Signed-off-by: Marco Franchi <marco.franchi@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Using SDMA1 with UART1 is causing a "Timeout waiting for CH0" error.
This patch changes to ahb clock from SDMA1_ROOT to AHB which
fixes the timeout error.
Fixes: a05ea40eb3 ("arm64: dts: imx: Add i.mx8mm dtsi support")
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
DCFG block uses little endian. Fix it so that register access becomes
correct.
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Acked-by: Yangbo Lu <yangbo.lu@nxp.com>
Fixes: 8897f3255c ("arm64: dts: Add support for NXP LS1028A SoC")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch is to enable emmc hs400 mode for ls1028ardb.
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Acked-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The eDMA of LS1028A soc has a little bit different from others, So we
should distinguish them in driver by compatible.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
There is no binding doc for these compatible string
"fsl,imx8mq-aips-bus" and "fsl,aips-bus", "simple-bus" is enough
for aips usage, so drop the upper two.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
According to the reference manual and the "Pins Tool" from NXP, the
signals for UART1 and UART2 can be muxed to the SAI2 and SAI3 pads
respectively. Let's add the missing options.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The device tree enables the following features -
1. dpmac17 RGMII MAC connected to Atheros AR8035 phy
2. 2x MDIO busses
3. 2x USB 3.0 controllers
4. 4x SATA ports
5. MT35X 512Mb SPI flash
6. Temperature sensor on i2c0 channel 3
7. AMC6821 temperature and PWM fan controller (not fitted)
The module supports AMC6821 PWM controller which is not currently
assembled on currently available Com Express 7 hardware.
This commit adds support for the Clearfog CX and Honeycomb variants,
which are indentical in this patch, but once QSFP support is finished,
only the Clearfog CX will have a QSFP description.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
[Add Makefile patch, split into clearfog-cx and honeycomb variants,
reworded commit -- rmk]
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add a description for the emdio2 controller to the lx2160a dtsi file,
so we can use it in the SolidRun Clearfog CX platform.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The WiFi firmware used on db845c implements the 8bit host-capability
message, so enable the quirk for this.
Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191113232245.4039932-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This is just like commit ac00546a67 ("arm64: dts: qcom: sc7180:
Rename gic-its node to msi-controller") but for sdm845. This fixes
all arm64/qcom device trees that I could find.
Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191216222021.1.I684f124a05a1c3f0b113c8d06d5f9da5d69b801e@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Rock Pi N10 is a Rockchip RK3399Pro based SBC, which has
- VMARC RK3399Pro SOM (as per SMARC standard) from Vamrs.
- Compatible carrier board from Radxa.
VAMRC RK3399Pro SOM need to mount on top of radxa dalang
carrier board for making Rock Pi N10 SBC.
So, add initial support for Rock Pi N10 by including rk3399,
rk3399pro vamrc-som and raxda dalang carrier board dtsi files.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20191216174711.17856-5-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
VMARC RK3399Pro SOM is a standard SMARC SOM design with
Rockchip RK3399Pro SoC, which is designed by Vamrs.
Specification:
- Rockchip RK3399Pro
- PMIC: RK809-3
- SD slot, 16GiB eMMC
- 2xUSB-2.0, 1xUSB3.0
- USB-C for power supply
- Ethernet, PCIe
- HDMI, MIPI-DSI/CSI, eDP
Add initial support for VMARC RK3399Pro SOM, this would use
with associated carrier board.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20191216174711.17856-3-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
With enabled wifi support (required for firmware loading) for the
Ampak AP6359SA based wifi/bt combo module we now also can enable
the bluetooth part.
Suggested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Soeren Moch <smoch@web.de>
Link: https://lore.kernel.org/r/20191218223523.30154-3-smoch@web.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
RockPro64 supports an Ampak AP6359SA based wifi/bt combo module.
The BCM4359/9 wifi controller in this module is connected to sdio0,
enable this interface.
Use the in-band sdio irq instead of the out-of-band wifi_host_wake_l
signal since the latter is not working reliably on this board (probably
due to it's PCIe WAKE# connection).
Signed-off-by: Soeren Moch <smoch@web.de>
Link: https://lore.kernel.org/r/20191218223523.30154-2-smoch@web.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Update existing and add missing regions to the reserved memory map, as
described in version 7.1
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20191218132217.28141-5-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The EK874 is advertised as compatible with panel IDK-2121WR from
Advantech, however the panel isn't sold alongside the board.
A new dts, adding everything that's required to get the panel to
to work with the EK874, is the most convenient way to support the
EK874 when it's connected to the IDK-2121WR.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/1576590361-28244-7-git-send-email-fabrizio.castro@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add device nodes for the I2C and IIC Controllers on the Renesas R-Car
M3-W+ (r8a77961) SoC, including DMA properties linking them to the DMA
controllers.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Tested-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Link: https://lore.kernel.org/r/20191216124740.16647-6-geert+renesas@glider.be
To improve human readability and enable automatic validation, the tuples
in "reg" properties should be grouped.
Fix this by grouping the tuples in the thermal node's "reg" property
using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213164115.3697-9-geert+renesas@glider.be
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
To improve human readability and enable automatic validation, the tuples
in the "ranges" and "dma-ranges" properties of PCI device nodes should
be grouped.
Fix this by grouping the tuples of the "ranges" and "dma-ranges"
properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213164115.3697-8-geert+renesas@glider.be
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped. While "make dtbs_check" does not impose this yet for the
"interrupts" property, it does for the "interrupt-map" property.
Fix this by grouping the tuples of the "interrupts" and "interrupt-map"
properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213164115.3697-7-geert+renesas@glider.be
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
To improve human readability and enable automatic validation, the tuples
in the "states" properties of device nodes compatible with
"regulator-gpio" should be grouped, as reported by "make dtbs_check":
$ make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/regulator/gpio-regulator.yaml
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml: regulator-vccq-sdhi0: states:0: Additional items are not allowed (1800000, 0 were unexpected)
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml: regulator-vccq-sdhi0: states:0: [3300000, 1, 1800000, 0] is too long
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml: regulator-vccq-sdhi3: states:0: Additional items are not allowed (1800000, 0 were unexpected)
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml: regulator-vccq-sdhi3: states:0: [3300000, 1, 1800000, 0] is too long
...
Fix this by grouping the tuples using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213164115.3697-6-geert+renesas@glider.be
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Commit f4a73f5e26 ("pinctrl: qcom: sc7180: Add new qup functions")
has landed which means that we absolutely need to use the proper names
for the pinmuxing for I2C/UART numbers 2, 4, 7, and 9. Let's do it.
For reference:
- If you get only one of this commit and the pinctrl commit then none
of I2C/UART 2, 4, 7, and 9 will work.
- If you get neither of these commits then I2C 2, 4, 7, and 9 will
work but not UART.
...but despite the above it should be fine for this commit to land in
the Qualcomm tree because sc7180.dtsi only exists there (it hasn't
made it to mainline).
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org>
Fixes: ba3fc64963 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191217130352.1.Id8562de45e8441cac34699047e25e7424281e9d4@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The pm8005_s1 is VDD_GFX, and needs to be on to enable the GPU.
This should be hooked up to the GPU CPR, but we don't have support for that
yet, so until then, just turn on the regulator and keep it on so that we
can focus on basic GPU bringup.
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lore.kernel.org/r/20191217170249.5280-1-jeffrey.l.hugo@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The SC7180 device tree nodes should be ordered by address. Re-shuffle
some nodes which currently don't follow this convention.
Since we are already moving it add a missing leading zero to the
address in the 'reg' property of the 'interrupt-controller@b220000'
node.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191212170824.v2.1.I55198466344789267ed1eb5ec555fd890c9fc6e1@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
It turns out that the wcn3990 can float the gpio lines during bootup, etc
which will result in the uart core thinking there is incoming data. This
results in the bluetooth stack getting garbage. By applying a bias to
match what wcn3990 would drive, the issue is corrected.
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lore.kernel.org/r/20191021161921.31825-1-jeffrey.l.hugo@gmail.com
[bjorn: Moved board specific pinctrl states to the end]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the cr50 device to the spi controller it is attached to. This
enables /dev/tpm0 and some login things on Cheza.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20191216234204.190769-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Fix up the correct interrupt numbers for the PMU unit on Agilex
and Stratix10.
Fixes: 78cd6a9d8e ("arm64: dts: Add base stratix 10 dtsi")
Cc: linux-stable <stable@vger.kernel.org>
Reported-by: Meng Li <Meng.Li@windriver.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Add support for the the amlogic libretech-pc platform, aka tartiflette.
There is 2 variants of the platform, one with the s905d, the other with
the s912.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the DV18 and DV19 pinmux setting for the i2c C of the gxl family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Allwinner device tree files used different comment style for
copyright notice.
Update this to keep a coherency.
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Use a shorter SPDX identifier instead of pasting the
whole license.
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Some headers specify that files are under dual-licensed GPL2.0+
and X11. But in fact, it turns out that the full licenses texts
associated are GPL2.0+ and MIT.
Fix license headers to reflect real licenses associated.
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
This patch splits rk3399-rockpro64 dts file to 2 files for v2 and
v2.1 boards.
Both v2 and v2.1 boards can use almost same settings but we find a
difference in I2C address of audio CODEC ES8136.
Reported-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Link: https://lore.kernel.org/r/20191202055929.26540-1-katsuhiro@katsuster.net
[put pine64,rockpro64-v2.* into an enum]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the video decoder specific compatible for Amlogic SM1 SoC.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the video decoder node for the Amlogic G12A and compatible SoC.
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
CONFIG_ARCH_R8A7796 was renamed to CONFIG_ARCH_R8A77960 in commit
39e57e14d7 ("soc: renesas: Add ARCH_R8A77960 for existing R-Car
M3-W"), to avoid confusion between R-Car M3-W (R8A77960) and R-Car M3-W+
(R8A77961).
Rename the DTS files as well, for consistency.
Note that DT binding headers, definitions, and compatible values were
not renamed, to preserve backward compatibility.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191211131311.23661-1-geert+renesas@glider.be
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com>
The bindings for the QMP PHY are truly strange. I believe (?) that
they may have originated because with PCIe each lane is treated as a
different PHY and the same PHY driver is used for a whole bunch of
things (incluidng PCIe).
In any case, now that we have "make dtbs_check", we find that having
the outer node named "phy" triggers the
"schemas/phy/phy-provider.yaml" schema, yelling about:
phy@88e9000: '#phy-cells' is a required property
Let's call the outer node the "phy-wrapper" and the inner node the
"phy" to make dtbs_check happy.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: 0b766e7fe5 ("arm64: dts: qcom: sc7180: Add USB related nodes")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191212113540.6.Iec10b23bb000186b36b8bacfb6789d8233de04a7@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This is just like commit e77cc85ee3 ("arm64: dts: qcom: sdm845:
remove macro from unit name"). It fixes the error in 'make
dtbs_check':
arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml: adc@3100: 'adc-chan@0x06' does not match any of the regexes: ...
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: a727ec1232 ("arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191212113540.4.I5f67a5ed7665f658c95447a837cbd0021e1dc689@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Running "dtbs_check" yells:
'#clock-cells' is a dependency of 'clock-output-names'
...and sure enough the bindings say we should have "#clock-cells".
Add it.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: 0b766e7fe5 ("arm64: dts: qcom: sc7180: Add USB related nodes")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191212113540.3.Ia530e4065ca81f55ac8f89a400f6a0a084ff6712@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Running `make dtbs_check` yells:
arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml: interrupt-controller@17a00000: gic-its@17a40000: False schema
From "arm,gic-v3.yaml" we can grok that this is explained by the
comment "msi-controller is preferred". Switch to the preferred name
so that dtbs_check stops yelling.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: 90db71e480 ("arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191212113540.2.Ibad7d3b0bea02957e89047942c61cc6c0aa61715@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This patch adds dr_mode property to the usb node for
zynqmp boards.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The #clock-cells and clock-accuracy properties are all expressed in
decimal, except for the drm-clock. Fix it, as decimal is easier to read
for those properties.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add the new compatible string for ZynqMP SD Host Controller for its use
in the Arasan SDHCI driver for some of the ZynqMP specific operations.
Add required properties for the same.
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add the DT node for the rpmhpd power controller.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/0101016e7f99eab9-35efa01f-8ed3-4a77-87e1-09c381173121-000000@us-west-2.amazonses.com
[bjorn: Use constant for opp6, until include lands]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
remove the additional CS muxes that were added by default for
spi so every board using sc7180 does not have to override it.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/0101016ef3cdad4a-cbfbc482-1f74-4cb7-88fc-b4b6ed7e7543-000000@us-west-2.amazonses.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The Dragonboard-410c is able to act either as USB Host or Device.
The role can be determined at runtime via the USB_HS_ID pin which is
derived from the micro-usb port VBUS pin.
In Host role, SoC USB D+/D- are routed to the onboard USB 2.0 HUB.
In Device role, SoC USB D+/D- are routed to the USB 2.0 micro B port.
Routing is selected via USB_SW_SEL_PM gpio.
In device role USB HUB can be held in reset.
chipidea driver expects two extcon device pointers, one for the
EXTCON_USB event and one for the EXTCON_USB_HOST event. Since
the extcon-usb-gpio device is capable of generating both these
events, point two times to this extcon device.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Link: https://lore.kernel.org/r/1576083014-5842-1-git-send-email-loic.poulain@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
PM8916 has one vibration motor driver that is already supported
by the pm8xxx-vibrator driver.
Add a node describing it to pm8916.dtsi.
Keep it disabled by default since not all devices make use of it.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191211192906.56638-1-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The reboot register isn't located inside the DCFG controller, but in its
own RST controller. Fix it.
Fixes: 8897f3255c ("arm64: dts: Add support for NXP LS1028A SoC")
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This device node is for calculating dynamic power in mW.
Since mt8173 has two clusters, there are two dynamic power
coefficient as well.
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Signed-off-by: Michael.Kao <michael.kao@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
The LS1028A SoC has only unidirectional SAIs. Therefore, it doesn't make
sense to have the RX and TX part synchronous. Even worse, the RX part
wont work out of the box because by default it is configured as
synchronous to the TX part. And as said before, the pinmux of the SoC
can only be configured to route either the RX or the TX signals to the
SAI but never both at the same time. Thus configure the asynchronous
mode by default.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
With dual licensed SPDX identifier the "OR" should
be uppercase.
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Allwinner A64 SoC has separate supplies for PC, PD, PE, PG and PL. This
patch adds regulators for them to the pinctrl node.
Exception is PL which is used by the RSB bus. To avoid circular
dependencies, VCC-PL is omitted.
On boards with eMMC, VCC-PC is supplied by ELDO1, instead of DCDC1.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
[Maxime: Changed the r_pio comment a bit]
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Allwinner H6 PWM is similar to that in A20 except that it has additional
bus clock and reset line.
Note that first PWM channel is connected to output pin and second
channel is used internally, as a clock source to AC200 co-packaged chip.
This means that any combination of these two channels can be used and
thus it doesn't make sense to add pinctrl nodes at this point.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The LS1028A has six SAI cores.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
