- support for a new variant of pca953x
- documentation fix from Wolfram
- some tegra186 name changes
- two minor fixes for madera and altera-a10sr
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEFp3rbAvDxGAT0sefEacuoBRx13IFAlxleLcACgkQEacuoBRx
13I45Q//YMGUYzkMjOL+lp2DYnnVhVNqrF4hoLjinWVrnhZ6gqu88RgV2Cea4Pta
oxVxnSsE8LK7kY8VZ8tcBmIqLLkQAJdSVtqkeSoZF2vhWBAbE9ZaSOYb17SIkSXK
Ok16lZgZ+ZWOM5EjEvuRpB/qYGjX2glD5/Y2Kl7+wsX1W6U2pXasP0IjhcvDU8mJ
NXNgfkr6kluMUqHJyqKo8eT/P3Hdv0CK9GsN2vGyfJenCdTSd7EC6KuhWAivi+fG
/lf1bVuc2cCiXjxdSOXx+Yz7SjNe56viTaqnn/K6OlfLgErjKnRW+AxPkTZXNtDi
pfMMpPXiwPcbQR2wrXG/7OMmJ1kUsfWoIUCx5RDwhF1KbEQVqgaSITLylk+4Yp/3
eM0fYsQ+KvOdAnWKSgfxBhaaiO7z5XDdrnkSHBDoiBrm07BqBgK/v3Rivzf2GMEv
QvM4OBfThS9I8skV5BaOBRDfHZs4N0EU/vhsW9gt50urtlSM0vSYx6kdMq/8R0k4
NkJT43u+1vi5koMljBAsZYZiyXOQ2B+PlfpTMfMu+93QH8wlu9mOt1r3YTQyA1Xf
jiOK8M2yQKP5g7RuPM6MtMsqlZKDM5nAlSf7S280Z3+vBd+LaELbXvT2/JL5ViGU
hfH/gaNwUGUYd8EsWvfhHVdPAAecDCwxfKyKEnFGhMrtunTgwfI=
=nV64
-----END PGP SIGNATURE-----
Merge tag 'gpio-v5.1-updates-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel
gpio updates for v5.1
- support for a new variant of pca953x
- documentation fix from Wolfram
- some tegra186 name changes
- two minor fixes for madera and altera-a10sr
* Add MSM8998 RPMCC, I2C, and USB related nodes
* Add MSM8996 rpmpd node
* Fix typo in MSM8996 pin definitions
* Disable MSM8996 VFE smmu to fix security violation
* Add I2C, SPI, rpmcc, uart, and WCN3990 wlan nodes on QCS404
* Enable SDCC1 HS400 support on QCS404
* Add a multitude of nodes on SDM845:
SD, UFS, USB, LPASS, SCM, QSPI, PDC, DPU, videocc, GPU, RPMh
bus interconnect, WCN3990 WLAN
* Add gpio ranges to SDM845 TLMM
* Fix regulator load on sdcard on MSM8998-mtp board
* Add thermal trip points to cpufreq
* Add SDM845 IOMMU info for SDHC, USB, and WLAN
* Fix MSM8916 clock cell argument
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJcZxDLAAoJEFKiBbHx2RXVWGgP/080wwgcj0gJP31orLypfSJa
9UYndhjdEVpomP3YOKNCUMyGO5MtQAIPXF3yPO30UER4mUsjDYmtZhlhIGPHDy3w
1ZAjIKPBb/9ujz3+/A4VHTVnySdgAdGDhUfXsae8cu+/55GGcbspbvev0Mt81QXm
n5Wk0rI2LDJsVKoV5PVV/YuWZgf7cycvW7b3kGKDD9mckbJ4IJZqXOQ+3sd8Gal+
RSS3l82ndKTJ8fugHxCroxAbS0CqPESqd8X/nopNdM3z2c4jlDd57v3NpygyfPQ6
/zKergRb02j4YqsB7Gv9m868beqmGjrmbAov1+v1MMEztoobSPwQZK/dkerHz5yf
e1K1dYHHnpvDA5sYZwNlTge/IojMZy5Rsm1Fs8ZQxun+6RrjfHW7QJbgQkcE2l/i
ISjRPUQTOGN2d+6XfoIRu76m13A7H9LiutW2IG10p6vFrwePuE3hwCO5XH2puAak
+1k4g+nBgzRlx+u01qKHqZq7nQwYfCq+fW3yqYOsepYTmaLUcT8+78C4PGu7Dz0P
sYCooq+byJ5eOPaq4DpA5szU2FuBABlBqBRVA+Wmy9slNuHiiK1fIOPO4V97Glqz
2F4Iivr9mbw79OrXx6bcqJm6EbAgpvyonlRnw0BVYd+1DEVEHntSx2QVN5wiEjqe
d6oyVpZT1VJb0CpnGU9p
=FgSp
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/dt
Qualcomm ARM64 Updates for v5.1
* Add thermal trip points to cpufreq
* Add SDM845 IOMMU info for SDHC, USB, and WLAN
* Fix MSM8916 clock cell argument
* tag 'qcom-arm64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: dts: sdm845: Fixup dependency on RPMPD includes
arm64: dts: sdm845: Add clocks and iommus to WCN3990 WLAN node
arm64: dts: qcom: sdm845: Define iommus for USB controllers
arm64: dts: qcom: sdm845: Define IOMMU for sdhc 2
arm64: dts: sdm845: wireup the thermal trip points to cpufreq
arm64: dts: msm8916: remove bogus argument to the cpu clock
[arnd: I've pulled the earlier branch again after an update, this
adds the stuff listed above, and fixes a build error from the missing
dependency, as I requested]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Contains a few DT updates on top of part 1 of the pull:
- MSMC RAM support (on-chip SRAM)
- Main system control module support
- USB support
- ADC support
There is an extra dt-binding update included, which has been acked
by Rob.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCAAuFiEEtQ6szHmfiBT7fujkyvq9MXlQGhEFAlxme1MQHHQta3Jpc3Rv
QHRpLmNvbQAKCRDK+r0xeVAaESgdD/9aZCR4YX27oQV5YmIsT0DkleOve48MIK9A
ex2Qk5dtZM8GRPTKQPfI1i8kHMya9Hlwb3NRAjCrZnnNRjge5LvTcDWbvSeUzlc1
BjyygctF2Sb9zKKyCoqV9UklpXisqw3QTxwmtUkdHNAzeyiQe71MM8XCEeBHcjUu
7EZJUzBPX4fABo560/1phubG4PrLA7eNG8gPl0p0LFf91ug5c+QO0jv+3p7K9pvn
o4TxyKgEXwADfx4px6y6u4uEuO3OXtYWNGbRhAaGXUAgEFiOYz5gJlgti7M16kXb
D1YeE4oKl3aXbCjb2V5FzoNw08zgQZgRT3QltyQnAZ/kYs1CFX4ooXUMx9GuCaJ3
T2UZ33t2lm4zVoYhlpKlZlZlk7bO4U9ZaOeSv+daKitpxvZPyJM7NLRTawCc3yyZ
08RJmYAf9Rl6MmNbrhyX3XQ5VC9/O26L1Gx+92bRFvdNL3Uwoi6T8bWFxbWrdr76
cL2aF9rYzVq3dQetNiqozg0GB/sCgEO1luGgkfIMLS9CpNxLPNa6orysRfMfkdJh
b1R51dUq80cl5v2lagTquFKb1T+/GRgEv/hi9aIR/Yfl2ASufFFQGkCKUPyFnPoX
BhH7Izg47x8HwAPU2s20nMJmaZ7hJ0PW1MUqidXgIdto9X82QWLcUCoeGXG1PAJR
uWFlyqaNag==
=L6dq
-----END PGP SIGNATURE-----
Merge tag 'am654-for-v5.1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into HEAD
AM654x SoC updates for v5.1 (part 2)
Contains a few DT updates on top of part 1 of the pull:
- MSMC RAM support (on-chip SRAM)
- Main system control module support
- USB support
- ADC support
There is an extra dt-binding update included, which has been acked
by Rob.
* tag 'am654-for-v5.1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
arm64: dts: ti: k3-am65-mcu: Add ADC nodes
dt-bindings: input: ti-tsc-adc: Add new compatible for AM654 SoCs
arm64: dts: ti: k3-am654-base-board: enable USB1
arm64: dts: ti: k3-am6: add USB support
arm64: dts: ti: am654: Add Main System Control Module node
arm64: dts: ti: k3-am65: Add MSMC RAM node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch fixes a dependency issue with the RPMPD dt bindings. This
temporarily removes the include file and adds hardcoded values for the
OPPs until the other changes full land. This will be addressed in 5.2.
Fixes: 5b6f186f0a ("arm64: dts: sdm845: Add rpmh powercontroller node")
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
- Extend timeout for wifi to power up on Ultra96
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlxiwJUACgkQykllyylKDCGTFQCgkxFLqTdsRVpcXbwdVZbI0TBL
CukAn3kkFlyUv/OE8z3K1u32tHKTDqyK
=2Qw6
-----END PGP SIGNATURE-----
Merge tag 'zynqmp-dt-for-v5.1' of https://github.com/Xilinx/linux-xlnx into arm/dt
arm64: dts: zynqmp: DT changes for v5.1
- Extend timeout for wifi to power up on Ultra96
* tag 'zynqmp-dt-for-v5.1' of https://github.com/Xilinx/linux-xlnx:
arm64: dts: zcu100-revC: Give wifi some time after power-on
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Interrupt support to Armada 7K/8K thermal nodes
- Armada 37xx related patches allowing to enable suspend to RAM
(USB2, USB3, PCIe, SATA, DSA)
- uDPU board support (Armada-3720 based):single-port FTTdp
distribution point unit
- Fixes for EspressoBin Ethernet support when using U-Boot mainline
- cleanup for partitions under flashes nodes
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCXF3x1wAKCRALBhiOFHI7
1ZtFAJ4pn8nIeHqWgYEUmWmCpQXnUoc4eQCgninj7JcAFV8KNLKhRCkKdlkeO38=
=Wt6S
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-5.1-1' of git://git.infradead.org/linux-mvebu into arm/dt
mvebu dt64 for 5.1 (part 1)
- Interrupt support to Armada 7K/8K thermal nodes
- Armada 37xx related patches allowing to enable suspend to RAM
(USB2, USB3, PCIe, SATA, DSA)
- uDPU board support (Armada-3720 based):single-port FTTdp
distribution point unit
- Fixes for EspressoBin Ethernet support when using U-Boot mainline
- cleanup for partitions under flashes nodes
* tag 'mvebu-dt64-5.1-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: armada-37xx: link USB hosts with their PHYs
arm64: dts: marvell: armada-3720-espressobin: declare SATA PHY property
arm64: dts: marvell: armada-3720-espressobin: declare PCIe PHY
arm64: dts: marvell: armada-37xx: declare the COMPHY node
arm64: dts: marvell: Remove unnecessary #address-cells/#size-cells under flashes
arm64: dts: armada-3720-espressobin: Set mv88e6341 cpu port as RGMII-ID
arm64: dts: armada-3720-espressobin: Configure RGMII and SMI pins
arm64: dts: marvell: Add device tree for uDPU board
arm64: dts: marvell: armada-3720-espressobin: declare PCIe warm reset pin
arm64: dts: marvell: armada-37xx: declare PCIe reset pin
arm64: dts: marvell: armada-37xx: declare USB2 UTMI PHYs
arm64: dts: marvell: armada-37xx: fix USB2 memory region
arm64: dts: marvell: armada-37xx: declare SATA clock
arm64: dts: marvell: armada-37xx: fix SATA node scope
arm64: dts: marvell: add interrupt support to cp110 thermal node
arm64: dts: marvell: add interrupt support to ap806 thermal node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add device nodes for usb3, iommu, smi, i2c, spi, pwm,
mmc, NAND flash and PCIe
mt6797:
add pinctrl node
enable uart pins on x20 board
enable uart pins on EVB
mt7622:
Add all CPUs to the cooling maps
mt7623a:
Remove unused binding description
mt7629:
Add binding description for the SoC and the BananaPi
based on this chip
mt8173:
Add all CPUs to the cooling maps
mt8183:
Add binding description for the SoC
-----BEGIN PGP SIGNATURE-----
iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAlxd2gYXHG1hdHRoaWFz
LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00MXBg//VKQgMqIWshMhu7hrD0wkPXZw
B0BJVlWhywTEisv3oduSL5HOVzKU6pQrWnF+X9PYokwNxz3VkNh3RixaLGsY3JOr
mkGtx3zAi1qsKYoKH6PNBhJVNCdX8D9SFlBSNOGkK0P5s0kjuPqzk28QU3ehwzdo
pFjbNadNDL9ySoybFtWGR8UwNkqq0w9acuiZbuRrqzdqkZLdxQ6zDry9P9s+97lA
WxFQEm+yhGHkpOb1XG75Zw3JBG55L3KymZV+h60wqHvdVCszINZZ9C2c/PqsWGVd
JzWMJPx2cghfLZdGlr5HQhKD5xM2Swmy2b5co4yRwsSmXdiK2RDkHkkli5CMpiIG
bt/6v3YffIVV07p/pzWrcOhJex4tCs0w3w24T03FxfCWVNXwb2kIV0Sv8dSBhUku
aESCBSrU0XAaKmhOPv49ys1oACpvPA9v/QyR+YyQPnK/4c4YezPidhCStvzhoxFG
a64OID6B1cmhI8PBCecRG22fEmDxktTj/FJ/0nsdbUgwbMXubr2vr9RzJW3B/M+G
z2ykW6q2K736EWWfKTpzXxfghVSaE90F1leQ3hjIv7h4AuribDw4IJ6ye+uI4Hb/
jiVHy6TSk8C07jMsvjifs1dL7UF6GIisD+90psuaiYngjilQkaHeDkosybe4qA6n
+r/pe4bCWvajl37DMXs=
=xm9P
-----END PGP SIGNATURE-----
Merge tag 'v5.0-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt
mt2712:
Add device nodes for usb3, iommu, smi, i2c, spi, pwm,
mmc, NAND flash and PCIe
mt6797:
add pinctrl node
enable uart pins on x20 board
enable uart pins on EVB
mt7622:
Add all CPUs to the cooling maps
mt7623a:
Remove unused binding description
mt7629:
Add binding description for the SoC and the BananaPi
based on this chip
mt8173:
Add all CPUs to the cooling maps
mt8183:
Add binding description for the SoC
* tag 'v5.0-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
dt-bindings: arm: mediatek: add support for MT7622 BPI-R64 and MT7629 RFB
dt-bindings: arm: mediatek: remove unused "mediatek, mt7623a"
dt-bindings: arm: Add bindings for Mediatek MT8183 SoC Platform
arm64: dts: add pcie nodes for MT2712
arm64: dts: add nand nodes for MT2712
arm64: dts: add mmc nodes for MT2712
arm64: dts: add pwm nodes for MT2712
arm64: dts: add spi nodes for MT2712
arm64: dts: add i2c nodes for MT2712
arm64: dts: add iommu/smi nodes for MT2712
arm64: dts: Add USB3 related nodes for MT2712
ARM64: dts: mediatek: Add all CPUs in cooling maps
arm64: dts: Add uart for mt6797 EVB
arm64: dts: mediatek: x20: Add pinmux support for UART1
arm64: dts: mediatek: mt6797: Add pinctrl support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This contains a couple of fixes to existing device trees, enables CPU
frequency scaling on various Tegra210 boards, enables the TCU as debug
serial port on Jetson Xavier, adds various improvements for SDMMC on
Tegra210, Tegra186 and Tegra194 boards and finally adds initial support
for the NVIDIA Shield TV.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlxdmX0THHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zob8+D/4oX6rlHS70H1CVhEF/2JejVBki5iX2
YGsjtywFGVU072OjQrIXARq/7LlH/4ykF8m8rNCTCzL1SewxpAhzTuyHSAitREjX
FMICa9bfv26J8n4n9SVOvuWmHc88rK3xaXgiKXIO/2viZsVDC7jeEfl/ztbSUWC7
KHx3moU3mzM0AqIX0z+tYg93uxYpx/sUgygLsJIneaj7b1g5sMZCAdLWQnvXmZKf
q5WTwbfUmhg2OrhnO6WXr6swmo7cXKO3zJcm/+b2adf01axMgCjA1RVFgO9yonqn
s2402oVRv/y7jsM7HGptlS6NqcurMnhlKCEUsVucXugWwbbAj/oFirYiCWW6fkq/
fgpOVbudjtF4jEiwxJ1KOVXlT34/Tt/Rksxr9uAht2L3KyDCT6mVKFVHq2jIFYVx
bIXT9HB3/ZjoVQzQKwRqKR8P9923avMmGvkGrDVXvvXx10hm7CK+UYJxOuwf80dQ
7ahfqSf34Pm3ezWpzr2TJxbd1DOFl57W2K/BjM3eUolwYXwIv8jANj87CqJj+llf
gtzMZS1bEdmFiP8DVnW0oQRS7quqSw0jo6qYLPV/dUBMPLFN8kdoWC9AfpQAaOxY
jJjpKBTkRcpc48TNAqcAuq53d1f+fsRptuIX2sLuSz7i3mQ80fJo+dET836Q0nYx
YYgVNWlJ5FTYyg==
=31KA
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.1-rc1
This contains a couple of fixes to existing device trees, enables CPU
frequency scaling on various Tegra210 boards, enables the TCU as debug
serial port on Jetson Xavier, adds various improvements for SDMMC on
Tegra210, Tegra186 and Tegra194 boards and finally adds initial support
for the NVIDIA Shield TV.
* tag 'tegra-for-5.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (25 commits)
arm64: tegra: Update compatible for Tegra186 I2C
arm64: tegra: Update compatible for Tegra210 I2C
arm64: tegra: Support 200 MHz for SDMMC on Tegra194
arm64: tegra: Add CQE Support for SDMMC4
arm64: tegra: Add SDMMC auto-calibration settings
arm64: tegra: Mark TCU as primary serial port on Tegra194 P2888
arm64: tegra: Add nodes for TCU on Tegra194
arm64: tegra: Enable DFLL clock on Smaug
arm64: tegra: Add CPU power rail regulator on Smaug
arm64: tegra: Enable DFLL clock on Jetson TX1
arm64: tegra: Add pinmux for PWM-based DFLL support on P2597
arm64: tegra: Add CPU clocks on Tegra210
arm64: tegra: Add DFLL clock on Tegra210
arm64: tegra: p2771-0000: Use TEGRA186_ prefix for GPIO names
arm64: tegra: p3310: Use TEGRA186_ prefix for GPIO names
arm64: tegra: p2597: Sort nodes by unit-address
arm64: tegra: p2972: Sort nodes properly
arm64: tegra: Add regulators for Tegra210 Darcy
arm64: tegra: Add pinmux for Darcy board
arm64: tegra: Add gpio-keys nodes for Darcy
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Our usual round of DT changes for the arm64 Allwinner SoCs:
- Enabling of the various power supplies on most a64 boards
- H6 SRAM controller support
- A64 CSI support
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXF1ZiQAKCRDj7w1vZxhR
xeeaAQCuII0MyMyRYhk4XPkjRncEks7A1Fp7u1kjR4VjbNq8JQD+OhCbKMAz4DVv
T7DeI92HwEO2Dx/ggNMVYDCUDyH55gI=
=Pd5b
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt64-for-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Allwinner arm64 DT changes for 5.1, take 2
Our usual round of DT changes for the arm64 Allwinner SoCs:
- Enabling of the various power supplies on most a64 boards
- H6 SRAM controller support
- A64 CSI support
* tag 'sunxi-dt64-for-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: a64: Enable PMIC power supplies on various boards
arm64: dts: allwinner: a64: teres-i: enable power supplies
arm64: dts: allwinner: h6: Add support for the SRAM C1 section
dt-bindings: sram: sunxi: Add compatible for the H6 SRAM C1
arm64: dts: allwinner: a64: Add A64 CSI controller
arm64: dts: allwinner: h6: Move GIC device node fix base address ordering
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Our usual round of DT changes shared between arm and arm64.
We have a bunch of changes for board, improving the eMMC support on the H5
variant of the All-H3-CC, enabling HDMI and reworking the CSI driver.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXF1X8QAKCRDj7w1vZxhR
xX9ZAP9KwFKKehrS1QJjTHKeowUKEnRHuDj2MlwTZJgCw/AMMgEAzgRZwY/VH/Os
aQIhJho9hWmBE0dePIZuWzzCp1giNw8=
=7jQV
-----END PGP SIGNATURE-----
Merge tag 'sunxi-h3-h5-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Allwinner H3 and H5 changes for 5.1
Our usual round of DT changes shared between arm and arm64.
We have a bunch of changes for board, improving the eMMC support on the H5
variant of the All-H3-CC, enabling HDMI and reworking the CSI driver.
* tag 'sunxi-h3-h5-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: h5: libretech-all-h3-cc: Mark eMMC HS-DDR 3.3V capable
ARM: dts: sunxi: h3/h5: Drop A31 fallback compatible for CSI controller
ARM: dts: sun8i-h3: nanopi-m1-plus: enable HDMI
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add SMMU node for Stratix10
- Add vendor prefix fo Novtech
- Add a new 96Boards Chameleon96 board that uses a Cyclone5 SoCFPGA
- Add missing reset properties for all IP on Cyclone5 and Arria10
-----BEGIN PGP SIGNATURE-----
iQJIBAABCgAyFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAlxYYAAUHGRpbmd1eWVu
QGtlcm5lbC5vcmcACgkQGZQEC4GjKPSfPA//a013n1vCV9Wz6RsbXNRODXzhV6FN
9uPWAdbkuWrCvDFAH+9s/0nMwxAj8f1HCEK9J07CPRcjcLPO7iHfIUeJ4lbCNCXZ
1ZuLDdK0Y4GjziJ4xlUP0JvUpJXtRKo+XDXVC+jNAMQy6wQpsEYdEwpeTPo94jrv
X0Zait3PeaY6ai6ImzV4QOYYmZ9GhRHjNY/Hc8jSsZeMWk+sMWygExlUngXlpO8c
dvK1Z4dfhrRZyJ/ewjjb/D0eekq8XiIfGmI4A2Cox3A73XAmtPEL3MT57BbPnq7f
jmNmlh7yRrxZHVErSt0dJTOJ6dNx+McuuwSmDL1vR19M44JUbVOjLjDUEwA7tSmr
eQXVhGuYHfxgJT0CeEBIHJAxPZfTqy68IijZYXv4aWimFdsbeAtraY7PKeZ/TnOP
3Aa9GDSks5NsAGVR5AltiNRmZujyQktbcNU8TcNt8tc19Kub8Q9GVhsmPUIKEov8
oAeXq4xbvGe6Ike6cfR1H+P14mgpbxJSZwGQoqky1T3lWqFBhl/93/ixpzt5jMWX
96tHA7VuZ7+in3BoqzHNxZ2PWpHScd3UScLxzxFEotW2nCofXCLCVkW+Zl8xWLa9
eu5GXE0ZzA04Elaagj2MM/rTsIgWFWqROq4A3Za6k5AB7quThr1yMoL+5Q5keOlO
4xAhCKudZb74BS4=
=8OgV
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_for_v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA DTS updates for v5.1
- Add SMMU node for Stratix10
- Add vendor prefix fo Novtech
- Add a new 96Boards Chameleon96 board that uses a Cyclone5 SoCFPGA
- Add missing reset properties for all IP on Cyclone5 and Arria10
* tag 'socfpga_dts_for_v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: update more missing reset properties
ARM: dts: socfpga: update missing reset property peripherals
ARM: dts: Add support for 96Boards Chameleon96 board
dt-bindings: vendor-prefixes: Add Novtech Vendor Prefix
arm64: dts: stratix10: Add Stratix10 SMMU support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
for 5.1, please pull the following:
- Stefan adds support for the Raspberry Pi 3 A+ by using the same
mechanism of creating a symbolic reference to the ARM 32-bit DTS file
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAlxV0bUACgkQh9CWnEQH
BwQ8Bw/6Anh/U7UiwqmxYCzEOUOE0Ry+v2Ar5CLSevUL2DbzP3fDEycRw4Cj2/0B
ZupHZFvCP4lYZEv1j679/nvcDz2XrfZ8+NED3ShHm9iIcXNtOodSGV7PYaeSdH6y
Ee63Cs7NlrwgHaSG8sDIvB3O7A+2Eq4/k7VuPPcGUIDF31TqqD9QgIA0qxGlq9dp
KheE7MsIklBk60OHq6rN+zRdgyxRYs0tuU8zv2SIT+8vK83NIV7t6ESRpj5Vw4x8
dCYYqCDJrormDlMV4cSC5nGo+7TrxZ2KvMQ/GxM/eDspDM0T+S+mYL8RrmEBLi+M
eUENDsLUt5pIjvXnyDXBIUTmWt+IFNCTdsyZ9WbGm/WES5+ktjRxe5VQOmezBfWV
U0uJ/chEZDz17zf2RpdQ4DuZT/QLqF1Uc2O+CyXNv3VwJ0L95+EyWlQ7TqR9ssDQ
KlPoEU6MOzVHtCTfXzTOv3+b1ndAAErYGV1bGjWPeaNeQllogMXHTMWzZnAkYWWO
zwl2+HtXgaVZN0oaU2voEDXB3DYKbNHyLqrQL/9IbbNXWWeswP/lIEYuOJ/h8l4j
u2Cq8PP6z6vb/oGWQGUCfWMPttaB5cyFeEYxb84q8MwizG0Yh/nEo5G4E8CI+dQT
5oqHlfvcnYap/Q796qcUxySmYMAWVlQA59xQ36WNzg+mRL3SdJw=
=iDFK
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.1/devicetree-arm64' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 5.1, please pull the following:
- Stefan adds support for the Raspberry Pi 3 A+ by using the same
mechanism of creating a symbolic reference to the ARM 32-bit DTS file
* tag 'arm-soc/for-5.1/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Add reference to RPi 3 A+
ARM: dts: add Raspberry Pi 3 A+
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
two being part of a family and sharing bigger parts of the devicetree.
rk3328 got sound-related upgrades and a wider patch drops mmc display-wp
fields from nodes which shouldn't use it.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlxTAa0QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgYrMB/93qkhsRz6kGXyeGWLQFYVJZET1IsHIqRUl
HDu/NwvZRPheupjgk37lAbTvQ8TeE8zb8i5I3lbhSZr1m8GL1Bsc3XZc2l8FXA9f
jib3xCaykp/qZMjgqSsesZmwcMzpUdMuGvK4NLLIWNWW+u3jQzo8N4eyXexRzY29
4Z69GodfMbsvFfi9mJ63pb2iTJhU+h1pLm4X8Df5DE4i1QyL9+vOiVYFM7AaMhMC
bBHzkQiJZC5hlhKUcCCW22T62yPnCHQdRG7SNPVyh/zSl3GvtL1CP9CHFDsPHG/j
443k+McXCvRCSK1wjRJraffD8gluBa/QgjFZj7hvuooOX7aGlM2E
=Bc63
-----END PGP SIGNATURE-----
Merge tag 'v5.1-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
New boards are the Rock Pi 4, NanoPC-T4 and NanoPi-M4, with the last
two being part of a family and sharing bigger parts of the devicetree.
rk3328 got sound-related upgrades and a wider patch drops mmc display-wp
fields from nodes which shouldn't use it.
* tag 'v5.1-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: clean up the abuse of disable-wp
arm64: dts: rockchip: 'Fix' nanopi4 uSD card detect
arm64: dts: rockchip: Add NanoPC-T4 IR receiver
arm64: dts: rockchip: Refine nanopi4 differences
arm64: dts: rockchip: Add DT for NanoPi M4
arm64: dts: rockchip: add ROCK Pi 4 DTS support
arm64: dts: rockchip: Add devicetree for NanoPC-T4
arm64: dts: rockchip: enable analog audio node for rock64
arm64: dts: rockchip: move rk3328 #sound-dai-cells to the soc dtsi
arm64: dts: rockchip: add rk3328 ACODEC node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
It contains a fix for i.MX8MQ EVK board device tree, which makes the
broken eMMC support work as expected.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJcVkZzAAoJEFBXWFqHsHzOjfwIALX4Sy/lU2X7M/ISKHwEIYP+
aRQ8ymXjRldTmCQusQVez8wRnphVqFI0Iyk6ktt/xzktmCCrhPDoUSKJWpwOuXj7
xTj5Rn13xNmanZ0Lox1d7w4dLEhWzYM+n2IAQT0UkcwQ6zhZQ+jx8dSbFVr15cd7
grlv5/a98IU7RvpdZzzIJvfHhey4R0diZicE6Gwha94JDGZkeyovdJ+5LvCiU7QU
lx632vsnIMWSlqNWmdKK8SvtduhRz099nhp+sZFrP/7CK8E+j1c6nV0rF2onUmkO
kvRLpw/IbBheQb9lBmcTrlf6f6Om03juy0Q682bX78qcMLvIAMczNsJNpfrNl8o=
=2/kD
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-5.0-3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
i.MX fixes for 5.0, 3rd round:
It contains a fix for i.MX8MQ EVK board device tree, which makes the
broken eMMC support work as expected.
* tag 'imx-fixes-5.0-3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx8mq: Fix boot from eMMC
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlxS/OQQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgbjLB/0XJqH9MerWA/J+OalNANjsXQemt8Vum4OA
4C5/ViMxMbzRQm+Sc2wCAzsq30Q6pqV74aTJYtUk6J2RalaiMCbkf8zRVZKzokbj
MKUdMmHu96ZA5LEqEEHK/eMOP4j70xz5VOnTBHQ2R759DkrS2U7rHIwx9ZX8XO9V
dI8rlHot9lgF1l8DDYLuPaLsILwHPhT/Y/wUv2Js5dZ5PFHS962I76sjYlngarT5
rd49Gv8ZvNDx1wftL4JtVMy/xuMKFRHhcxpF8TrdSS648U9Rvf9l2vXR6PErHfZP
poSG5jy1vn0aPmOEWjw1sDSXPcK7ImUNTM7k8ffTPecCmmC5gCIO
=qf0D
-----END PGP SIGNATURE-----
Merge tag 'v5.0-rockchip-dts64fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
Fix for new dtc graph warnings and a regulator fix for rock64.
* tag 'v5.0-rockchip-dts64fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: enable usb-host regulators at boot on rk3328-rock64
arm64: dts: rockchip: fix graph_port warning on rk3399 bob kevin and excavator
This patch is a port of the fix from
commit 73e42e1866 ("arm64: dts: rockchip: fix rock64 gmac2io stability
issues")
As per that patch, enabling thresh dma mode force disables checksuming.
This is necessary as tx checksuming does not work with packets larger
than 1498.
The rk3328-roc-cc board exhibits tx stability issues with large packets
similar to rock64's issues. This patch resolves that issue.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
vcc5v0_host and vcc5v0_typec is supplied by vcc5v0_usb and not vcc5v0_sys.
add node for vcc5v0_usb fixed regulator.
Signed-off-by: Akash Gajjar <Akash_Gajjar@mentor.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
lcd panel pinmux is unused and the pin actually for something different,
so removing it.
Signed-off-by: Akash Gajjar <Akash_Gajjar@mentor.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
rename dc12, vcc_sys, vcc1v8_pmu regulators and make it more redable as per the
schematic of rk3399-rockpro64.
Signed-off-by: Akash Gajjar <Akash_Gajjar@mentor.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Describe the Bluetooth portion of the Ampak combo module - this is
either an AP6356S or an AP6212 depending on the board variant, but
there are no relevant compatibility differences between the two.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
TI AM654 SoC has two ADC instances in the MCU domain. Add DT nodes for
the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Adds support for USB0 and USB1 instances on the AM6 SoC.
USB0 is limited to high-speed for now.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Main System control module support is added to the device tree to allow
driver to access to their control module registers.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The AM65 SoC has 2MB MSMC RAM. Add this as a mmio-sram
node so drivers can use it via genpool API.
Following areas are marked reserved:
- Lower 128KB for ATF
- 64KB@0xf0000 for SYSFW
- Upper 1MB for cache
The reserved locations are subject to change at runtime by
the bootloader.
Cc: Nishanth Menon <nm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Andrew F. Davis <afd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Sort the labels in the same order as in the corresponding dtsi file,
in other words, the order of reg address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The peripheral bus on the i.MX8MQ is still limited to 32bits, so
we need to declare the usable range for device DMA operations, as
the DRAM will extend across the 32bit boundary if more than 3GB
are installed.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add RTC support for i.MX8MQ.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Tested-by: Chris Spencer <christopher.spencer@sea.co.uk>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Enable the Freescale/NXP QuadSPI controller with a proper pinctrl set on
the i.MX8MQ EVK board.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add a node for the Freescale/NXP QuadSPI controller and extend the AIPS3
memory range to accommodate the QuadSPI-memory region.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support for the three ECSPI ports present on i.MX8MQ.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add devicetree support for Sophon Edge board from Bitmain based on
BM1880 SoC. This board is one of the 96Boards Consumer and AI platform.
More information about this board can be found in 96Boards product page:
https://www.96boards.org/documentation/consumer/sophon-edge/
Only UART peripheral support is enabled for now.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Add devicetree support for Bitmain BM1880 SoC, consisting of a Dual
core ARM Cortex A53 subsystem, a Single core RISC-V subsystem and a Tensor
Processor subsystem. Only ARM Cortex A53 Application processor subsystem
support is enabled for now.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reference the PHY nodes from the USB controller nodes.
The USB3 host controller is wired to:
* the first PHY of the COMPHY IP
* the OTG-capable UTMI PHY
The USB2 host controller is wired to:
* the host-only UTMI PHY
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The SATA node is wired to the third PHY of the COMPHY IP.
Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The PCIe node is wired to the second PHY of the COMPHY IP.
Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Describe the A3700 COMPHY node. It has three PHYs that can be
configured as follow:
* PCIe or GbE
* USB3 or GbE
* SATA or USB3
Each of them has its own memory area.
Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
By using the new binding for the partitions for the flashes we don't need
anymore to use #size-cells and #address-cells at the flash node level.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The mv88e6341 ethernet switch needs the cpu port control register to be
set with TX and RX internal delay in order to work.
This fixes ethernet support on system booted via a bootloader that
has not already configured this register (e.g. mainline u-boot, or
vendor u-boot compiled without ethernet support).
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
In order to be able to communicate with the 88e6341 switch some pins
have to be repurposed as RGMII and SMI pins.
This fixes ethernet support on system booted via a bootloader that
has not already configured those pins (e.g. mainline u-boot, or vendor
u-boot compiled without ethernet support).
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add the G12a (S905X2) based X96 Max board[1].
There is no branding for the manufacturer anywhere on the product, so it
took some digging[2] to find the manufacturer. But since there's
nothing about the maker on the product I've left it out of the DT name
because 1) nobody will know that name and 2) keeps the DT filename
shorter.
[1] https://www.cnx-software.com/2018/09/25/x96-max-amlogic-s905x2-tv-box/
[2] https://fccid.io/2AI6D-X96MAX
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the peripheral clock controller to the g12a SoC DT
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This adds initial support for micro-DPU (uDPU) board which is based on
Armada-3720 SoC. micro-DPU is the single-port FTTdp distribution point
unit made by Methode Electronics which offers complete modularity with
replaceable SFP modules both for uplink and downlink (G.hn over
twisted-pair, G.hn over coax, 1G and 2.5G Ethernet over Cat-5e cable).
On-board features:
- 512 MiB DDR3
- 2 x 2.5G SFP via HSGMII SERDES interface to the A3720 SoC
- USB 2.0 Type-C connector
- 4GB eMMC
- ETSI TS 101548 reverse powering via twisted pair (RJ45) or coax (F Type)
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Luis Torres <luis.torres@methode.com>
Cc: Scott Roberts <scott.roberts@telus.com>
Cc: Paul Arola <paul.arola@telus.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This patch enables PCIEC0 PCI express controller on the sub board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Silicon Linux CAT 874 board has 2GB DDR memory. Update the dma-ranges
mapping for pciec0 node. Also declare pcie bus clock, since it is
generated on the CAT874 main board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch defines OOP tables for all CPUs, similarly to
what done by Takeshi Kihara and Yoshihiro Kaneko for the
R8A77990.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch define OOP tables for all CPUs.
This allows CPUFreq to function.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Successfully tested on H3 ES2.0 and M3-N ES1.0.
Transfer rates where >160MB/s for H3 and >200MB/s for M3-N.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
When commit 022bccb840 ("dts: arm64/sdm845: Add WCN3990 WLAN module
device node") was posted upstream no clocks were specified. However,
when the pack was picked into the Chrome OS kernel tree (allegedly
directly from the mailing list post) it had clock properties.
I presume that the clock should be there, so let's add it.
Fixes: 022bccb840 ("dts: arm64/sdm845: Add WCN3990 WLAN module device node")
Tested-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
[bjorn: Add also the required iommus property]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the clock measure device to the g12a SoC family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the clock measure device to the axg SoC family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Change the SDMMC clock source to support a maximum frequency of 200 MHz
on Tegra194.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add SDMMC initial pad offsets used by auto calibration process.
Add SDMMC fixed drive strengths for Tegra210, Tegra186 and
Tegra194 which are used when calibration timeouts.
Fixed drive strengths are based on Pre SI Analysis of the pads.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Tegra Combined UART is the proper primary serial port on P2888,
so use it.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add nodes required for communication through the Tegra Combined UART.
This includes the AON HSP instance, addition of shared interrupts
for the TOP0 HSP instance, and finally the TCU node itself. Also
mark the HSP instances as compatible to tegra194-hsp, as the hardware
is not identical but is compatible to tegra186-hsp.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable DFLL clock for Smaug board.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add CPU power rail regulator for Smaug board.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable DFLL clock for Jetson TX1 platform.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add pinmux for PWM-based DFLL support.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add CPU clocks for Tegra210.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add essential DFLL clock properties for Tegra210.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Fix apb, cbus, hiu and periph regions which are not aligned
with the documentation and the information provided by Amlogic
Fixes: 9c8c52f7cb ("arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support")
Cc: Jianxin Pan <jianxin.pan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The USB controllers need to be associated with their respective IOMMU
bank, so define this on the dwc3 nodes.
Also add dma-ranges to the qcom-dwc3 nodes to make the bus' DMA mask
propagate to the dwc3 controller instances.
Fixes: 4429e57567 ("arm64: dts: sdm845: Add node for arm,mmu-500")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
With apps_smmu initializing the SMMU we must specify iommus property for
the sdhc controller.
Fixes: 4429e57567 ("arm64: dts: sdm845: Add node for arm,mmu-500")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Since all cpus in the big and little clusters, respectively, are in the
same frequency domain, use all of them for mitigation in the
cooling-map. We end up with two cooling devices - one each for the big
and little clusters.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The apcs node has #clock-cells = <0>, which means that those who
references it should specify 0 arguments.
The apcs reference in the cpu node incorrectly specifies an argument,
remove this bogus argument.
Fixes: 65afdf4583 ("arm64: dts: qcom: msm8916: Add CPU frequency scaling support")
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The Libre Computer ALL-H3-CC H5 is one of the few boards that can have
its eMMC run at HS-DDR speed mode. Mark it as such.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
On these A64 devices, the DC input jacks are wired to the ACIN pins of
the PMIC, which is represented by the AC power supply. With the
exception of the Nanopi A64, all devices include LiPo batteries or have
connectors for them, which are represented by the battery power supply.
Enable these power supplies in the device tree.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Ensure the PCIe endpoint card reset that is toggled by the PCIe
controller itself is muxed correctly on the EspressoBin.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
One pin can be muxed as PCIe endpoint card reset.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
On Marvell Armada 3700 SoCs there are two USB2 UTMI PHYs. They are
both very similar but only one has OTG/charging capabilities.
Because there are USB host registers and PHY registers mixed in a
single area, a system controller is also created and referenced from
both the USB host node and the PHY node.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The specification splits the USB2 memory region into three sections:
1/ 0xD005E000-0xD005EFFF: USB2 Host Controller Registers
2/ 0xD005F000-0xD005F7FF: USB2 UTMI PHY Registers
3/ 0xD005F800-0xD005FFFF: USB2 Host Miscellaneous Registers
Section 1/ belongs to the USB2 node but section 2/ belongs to the UTMI
PHY node. Section 3/ can be accessed by both the USB controller and
the PHY because of the miscaellaneous nature of the registers inside
so a specific node will be created to cover the area and a handle to
it will be added in both the USB controller and the PHY node.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
The SATA IP get its clock from the north-bridge.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Fix the SATA IP memory area which is only 0x178 bytes long (from
Marvell A3700 specification). Actually, starting from the offset
0xe0178, there is an area dedicated to the COMPHY driver.
Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add interrupt properties in the thermal node as well as a critical trip
point in the thermal-zone.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Add interrupt properties in the thermal node as well as a critical trip
point in the thermal-zone.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This reverts commit abd7d0972a. This
change was already partially reverted by John Stultz in
commit 9c6d26df1f ("arm64: dts: hikey: Fix eMMC corruption regression").
This change appears to cause controller resets and block read failures
which prevents successful booting on some hikey boards.
Cc: Ryan Grachek <ryan@edited.us>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: stable <stable@vger.kernel.org> #4.17+
Signed-off-by: Alistair Strachan <astrachan@google.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Somewhere along recent changes to power control of the wl1835, power-on
became very unreliable on the hikey, failing like this:
wl1271_sdio: probe of mmc2:0001:1 failed with error -16
wl1271_sdio: probe of mmc2:0001:2 failed with error -16
After playing with some dt parameters and comparing to other users of
this chip, it turned out we need some power-on delay to make things
stable again. In contrast to those other users which define 200 ms, the
hikey would already be happy with 1 ms. Still, we use the safer 10 ms,
like on the Ultra96.
Fixes: ea45267873 ("arm64: dts: hikey: Fix WiFi support")
Cc: <stable@vger.kernel.org> #4.12+
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
